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IEEE, the world’s largest technical professional organization dedicated to advancing technology for humanity, today announced the launch of the International Roadmap for Devices and Systems (IRDS), a new IEEE Standards Association (IEEE-SA) Industry Connections (IC) program to be sponsored by the IEEE Rebooting Computing (IEEE RC) Initiative in consultation with the IEEE Computer Society. Together, this group will ensure alignment and consensus across a range of stakeholders to identify trends and develop the roadmap for all of the related technologies in the computer industry.

The IRDS represents the next phase of work that began with the partnership between the IEEE RC Initiative and the International Technology Roadmap for Semiconductors 2.0 (ITRS 2.0). With the launch of the IRDS program, IEEE is taking the lead in building a comprehensive, end-to-end view of the computing ecosystem, including devices, components, systems, architecture, and software. The Methods of governance, reports, and strategic roadmaps developed by the ITRS and ITRS 2.0 will inform the IRDS within the IEEE-SA IC program.

“The computer industry has benefitted from roadmaps since it was first published in 1965,” said IEEE Fellow Thomas M. Conte, 2015 president, IEEE Computer Society; co-chair, IEEE Rebooting Computing Initiative; and Professor, Schools of Computer Science, and Electrical and Computer Engineering, Georgia Institute of Technology. “Bringing the IRDS under the IEEE umbrella will create a new ‘Moore’s law’ of computer performance, and accelerate bringing to market new, novel computing technologies.”

“The broad scope of IRDS spanning from base technology through systems and architecture will create an environment where known end-requirements will drive technological solutions and decrease the time to market for implementation, ultimately creating a new Moore’s law,” added IEEE Fellow and Senior Director, IEEE Future Directions, William R. Tonti. “The integration of the work of the IRDS into IEEE and governance of the semiconductor to system roadmap through the IEEE Rebooting Computing Initiative opens the door to innovative end-to-end computing solutions.”

“Over the past decade, the structure and requirements of the electronics industry have evolved well beyond the semiconductor’s industry requirements. In line with the changes in the new electronics ecosystem, the IRDS will build upon the past groundwork and move up a level to identify challenges and include recommendations on possible solutions,” said Paolo A. Gargini, IEEE Fellow and chairman, of IRDS. “The IRDS will deliver a 15-year vision that encompasses systems and devices, setting a new direction for the future of the semiconductor, communications, IoE and computer industries.”

Participants in the IRDS will convene 12-13 May 2016 in Leuven, Belgium. Over the course of the two-day workshop, the group will review the roadmap activities of the Focus Teams (FT) and of the International Technology Working Groups (ITWG) and lay out plans for additional activities in 2016. Some of the fields of discussion include System Integration, Heterogeneous Integration, Connectivity, Future IC Devices and Factory Integration.

The IEEE Rebooting Computing Initiative is a program of the IEEE Future Directions Committee, designed to develop and share educational tools, events and content for emerging technologies.

IEEE-SA’s Industry Connections Program helps incubate new standards and related products and services, by facilitating collaboration among organizations and individuals as they hone and refine their thinking on rapidly changing technologies.

By Ed Korczynski, Senior Technical Editor

The world’s leading lithographers gather each year in San Jose, California at SPIE’s Advanced Lithography conference to discuss how to extend optical lithography. So of all the NGL technologies, which will win out in the end?

“Mix and Match” has long been a mantra for lithographers in the deep-sub-wavelength era of IC device manufacturing. In general, forming patterns with resolution at minimum pitch as small as 1/4 the wavelength of light can be done using off-axis illumination (OAI) through reticle enhancement techniques (RET) on masks, using optical proximity correction (OPC) perhaps derived from inverse lithography technology (ILT). Lithographers can form 40-45nm wide lines and spaces at the same half-pitch using 193nm light (from ArF lasers) in a single exposure.

Figure 1 shows that application-specific tri-layer photoresists are used to reach the minimum resolution of 193nm-immersion (193i) steppers in a single exposure. Tighter half-pitch features can be created using all manner of multi-patterning processes, including Litho-Etch-Litho-Etch (LELE or LE2) using two masks for a single layer or Self-Aligned Double Patterning (SADP) using sidewall spacers to accomplish pitch-splitting. SADP has been used in high volume manufacturing (HVM) of logic and memory ICs for many years now, and Self-Aligned Quadruple Patterning (SAQP) has been used in at least one leading memory fab.

FIGURE 1. Basic tri-layer resist (TLR) technology uses thin Photoresist over silicon-containing Hard-Mask over Spin-On Carbon (SOC), for patterning critical layers of advanced ICs. (Source: Brewer Science)

FIGURE 1. Basic tri-layer resist (TLR) technology uses thin Photoresist over silicon-containing Hard-Mask over Spin-On Carbon (SOC), for patterning critical layers of advanced ICs. (Source: Brewer Science)

Next-Generation Lithography (NGL) generally refers to any post-optical technology with at least some unique niche patterning capability of interest to IC fabs: Extreme Ultra-Violet (EUV), Directed Self-Assembly (DSA), and Nano-Imprint Lithography (NIL). Though proponents of each NGL have dutifully shown capabilities for targeted mask layers for logic or memory, the capabilities of ArF dry and immersion (ArFi) scanners to process >250 wafers/ hour with high uptime dominates the economics of HVM lithography.

The world’s leading lithographers gather each year in San Jose, California at SPIE’s Advanced Lithography conference to discuss how to extend optical lithography. So of all the NGL technologies, which will win out in the end?

It is looking most likely that the answer is “all of the above.” EUV and NIL could be used for single layers. For other unique patterning application, ArF/ArFi steppers will be used to create a basic grid/template which will be cut/trimmed using one of the available NGL. Each mask layer in an advanced fab will need application-specific patterning integration, and one of the rare commonalities between all integrated litho modules is the overwhelming need to improve pattern overlay performance.

Naga Chandrasekaran, Micron Corp. vice president of Process R&D, provided a fantastic overview of the patterning requirements for advanced memory chips in a presentation during Nikon’s LithoVision technical symposium held February 21st in San Jose, California prior to the start of SPIE-AL. While resolution improvements are always desired, in the mix-and-match era the greatest challenges involve pattern overlay issues.

“In high volume manufacturing, every nanometer variation translates into yield loss, so what is the best overlay that we can deliver as a holistic solution not just considering stepper resolution?” asks Chandrasekaran.

“We should talk about cost per nanometer overlay improvement.”

Extreme Ultra-Violet (EUV)

As touted by ASML at SPIE-AL, the brightness and stability and availability of tin-plasma EUV sources continues to improve to 200W in the lab “for one hour, with full dose control,” according to Michael Lercel, ASML’s director of strategic marketing. ASML’s new TWINSCAN NXE:3350B EUVL scanners are now being shipped with 125W power sources, and Intel and Samsung Electronics reported run their EUV power sources at 80W over extended periods.

During Nikon’s LithoVision event, Mark Phillips, Intel Fellow and Director of Lithography Technology Development for Logic, summarized recent progress of EUVL technology: ~500 wafers-per-day is now standard, and ~1000 wafer-per-day can sometimes happen. However, since grids can be made with ArFi for 1/3 the cost of EUVL even assuming best productivity for the latter, ArFi multi-patterning will continue to be used for most layers.

“Resolution is not the only challenge,” reminded Phillips. “Total edge-placement-error in patterning is the biggest challenge to device scaling, and this limit comes before the device physics limit.”

Directed Self-Assembly (DSA)

DSA seems most suited for patterning the periodic 2D arrays used in memory chips such as DRAMs. “Virtual fabrication using directed self-assembly for process optimization in a 14nm DRAM node” was the title of a presentation at SPIE-AL by researchers from Coventor in which DSA compared favorably to SAQP.

Imec presented electrical results of DSA-formed vias, providing insight on DSA processing variations altering device results. In an exclusive interview with Solid State Technology and SemiMD, imec’s Advanced Patterning Department Director Greg McIntyre reminds us that DSA could save one mask in the patterning of vias which can all be combined into doublets/triplets, since two masks would otherwise be needed to use 193i to do LELE for such a via array. “There have been a lot of patterning tricks developed over the last few years to be able to reduce variability another few nanometers. So all sorts of self-alignments.”

While DSA can be used for shrinking vias that are not doubled/tripled, there are commercially proven spin-on shrink materials that cost much less to use as shown by Kaveri Jain and Scott Light from Micron in their SPIE-AL presentation, “Fundamental characterization of shrink techniques on negative-tone development based dense contact holes.” Chemical shrink processes primarily require control over times, temperatures, and ambients inside a litho track tool to be able repeatably shrink contact hole diameters by 15-25 nm.

Nano-Imprint Litho (NIL)

For advanced IC fab applications, the many different options for NIL technology have been narrowed to just one for IC HVM. The step-and-pattern technology that had been developed and trademarked as “Jet and Flash Imprint Lithography” or “J-FIL” by, has been commercialized for HVM by Canon NanoTechnologies, formerly known as Molecular Imprints (http://cnt.canon.com/). Canon shows improvements in the NIL mask-replication process, since each production mask will need to be replicated from a written master. To use NIL in HVM, mask image placement errors from replication will have to be reduced to ~1nm, while the currently available replication tool is reportedly capable of 2-3nm (3 sigma).

Figure 2 shows normalized costs modeled to produce 15nm half-pitch lines/spaces for different lithography technologies, assuming 125 wph for a single EUV stepper and 60 wph for a cluster of 4 NIL tools. Key to throughput is fast filling of the 26mmx33mm mold nano-cavities by the liquid resist, and proper jetting of resist drops over a thin adhesion layer enables filling times less than 1 second.

FIGURE 2. Relative estimated costs to pattern 15nm half- pitch lines/spaces for different lithography technologies, assuming 125 wph for a single EUV stepper and 60 wph for a cluster of 4 NIL tools. (Source: Canon)

FIGURE 2. Relative estimated costs to pattern 15nm half- pitch lines/spaces for different lithography technologies, assuming 125 wph for a single EUV stepper and 60 wph for a cluster of 4 NIL tools. (Source: Canon)

Researchers from Toshiba and SK Hynix described evaluation results of a long-run defect test of NIL using the Canon FPA-1100 NZ2 pilot production tool, capable of 10 wafers per hour and 8nm overlay, in a presentation at SPIE-AL titled, “NIL defect performance toward high- volume mass production.” The team categorized defects that must be minimized into fundamentally different categories—template, non-filling, separation-related, and pattern collapse—and determined parallel paths to defect reduction to allow for using NIL in HVM of memory chips with <20nm half-pitch features.

ams AG (SIX: AMS) today took a step forward in its long-term strategy of increasing manufacturing capacity for its high-performance sensors and sensor solution integrated circuits (ICs), holding a groundbreaking event at the site of its new wafer fabrication plant in Utica, New York.

An artist’s rendering of a semiconductor fab at the Marcy site.

The ceremony featured New York Lieutenant Governor Kathy Hochul, Utica Mayor Robert Palmieri, local dignitaries and senior executives from ams and SUNY Polytechnic Institute.

ams sensor solutions are relied upon globally by manufacturers of smartphones, tablets and other communications devices, automakers, audio and medical equipment manufacturers and others. ams sensors are used in hundreds of millions of devices to recognize light, color, gestures, images, motion, position, environmental and medical parameters and more.

With construction work now underway on the new fab, ams remains on track to reach its target for the first batches of wafers made at the plant in the first half of 2018.

Production capacity at the Utica fab will supplement ams’ existing 180nm and 350nm CMOS and SiGe fab at its headquarters near Graz, Austria. Adding this additional volume to its in-house chip manufacturing facilities positions ams to meet the forecasted growth in demand for its high-performance sensor solution ICs.

New York Governor Andrew Cuomo has made public-private partnerships an important part of this  Nano Utica initiative, which exceeds 4,000 projected jobs over the next decade. Designed to replicate the dramatic success of SUNY Poly’s Nanotech Megaplex in Albany, NANO Utica further cements New York’s international recognition as the preeminent hub for 21st century nanotechnology innovation, education, and economic development.

The Governor says the addition of ams and others to Nano Utica is creating an economic revolution around nano-technology in the Mohawk Valley region, and that the economy there is “gathering momentum unlike ever before.”

The new fab, which is being built to ams’s specifications and which ams will operate under a 20-year lease, is expected initially to offer capacity of at least 150,000 200mm-wafer equivalents per year. Planned expansion thereafter will eventually see the plant operating at a capacity of more than 450,000 200mm-wafer equivalents per year.

The new fab is located close to a campus of SUNY Polytechnic Institute in New York’s Tech Valley, the largest region focused on technology manufacturing in the US and home to other nanotechnology and semiconductor companies. The fab will be capable of producing wafers at the 130nm node, and more advanced nodes in the future.

Today’s celebratory event at the new fab site also marked the success of the partnership behind the project to build, equip and operate another high-technology manufacturing facility in the State of New York. This partnership has benefited from a wide-ranging collaboration between public sector bodies such as the New York governor’s office, the City of Utica and the State University of New York, and various private sector institutions including ams, the fab’s sole leaseholder.

Approximately 250 people gathered at the construction site to see Lt. Governor Hochul and ams CEO Alexander Everke break ground for the foundation of what will be, on completion in 2018, one of the world’s largest analog wafer fabs.

“Building this new wafer fab enables ams to achieve its plans for growth and to meet the increasing demand for sensor solutions produced at advanced manufacturing nodes. Our decision to locate the facility in New York was motivated by the availability of a highly skilled workforce, the proximity to prestigious educational and research institutions, and the favorable business environment, backed by public and private partners,” Mr. Everke said. “What we will create together in Utica will be the most productive ‘More than Moore’ fab worldwide,” he added.

IC Insights’ March Update to the 2016 McClean Report refreshed the forecasts for 33 major IC product categories through 2020.  The complete list of all 33 major IC product categories ranked by the updated forecast growth rates for 2016 is shown in Figure 1.  Fourteen product categories—topped by Cellphone Application Processors and Signal Conversion (analog) devices—are expected to exceed the 2% growth rate forecast for the total IC market this year. Another five product categories are expected to grow at the same 2% rate as the total IC market.  The total number of IC categories forecast to register sales growth in 2016 increases to 20 products from only nine in 2015.

Growth of Cellphone Application MPUs (10%) is forecast to remain near the top on the growth list for a fifth consecutive year. Though the rate of growth for cellphone application MPUs has cooled in recent years, IC Insights still forecasts a solid 10% growth year for this market as smartphone shipments remain an attractive end-use application for IC markets.  Signal Conversion (DAC analog, etc.) devices are also expected to show a 10% increase in 2016 thanks to their implementation across a wide variety of consumer, communication, and computing devices, and in other systems to monitor and control the interface between analog and digital signals.   The market for 32-bit MCUs is forecast to increase 8% with “intelligent” cars the catalyst for much of this growth.  Driver information systems and many of the increasing number of semi-autonomous driving features such as self-parking, advanced cruise control, and collision-avoidance rely on 32-bit MCUs. Complex 32-bit MCUs are expected to account for over 25% of the processing power in vehicles in the next few years.

Other notable categories include the previously high-flying Tablet MPU market, which is forecast to sputter to just 2% growth in 2016 as enthusiasm fades for these systems. DRAM is expected to show a steep market decline this year and drop to become the second-largest IC product category (trailing only the standard PC, server MPU market) in 2016.  After registering big gains in 2013 and 2014, the DRAM market fell 3% in 2015 and is forecast to tumble another 8% in 2016 as oversupply and waning desktop and notebook computer demand force suppliers to slash average selling prices to move product.  Worldwide DRAM ASP growth was down 4% in 2015 and is on track to fall 11% in 2016.

2016 forecast of ic market

Figure 1

By David W. Price, Douglas G. Sutherland and Kara L. Sherman

Author’s Note: The Process Watch series explores key concepts about process control—defect inspection and metrology—for the semiconductor industry. Following the previous installments, which explored the 10 fundamental truths of process control, this new series of articles highlights additional trends in process control, including successful implementation strategies and the benefits for IC manufacturing. For this article, we are pleased to include insights from our guest author, Kara Sherman.

As we celebrate Earth Day 2016, we commend the efforts of companies who have found ways to reduce their environmental impact. In the semiconductor industry, fabs have been building Leadership in Energy and Environmental Design (LEED)-certified buildings [1] as part of new fab construction and are working with suppliers to directly reduce the resources used in fabs on a daily basis.

As IC manufacturers look for more creative ways to reduce environmental impact, they are turning to advanced process control solutions to reduce scrap and rework, thereby reducing fab resource consumption. Specifically, fabs are upgrading process control solutions to be more capable and adding additional process control steps; both actions reduce scrap and net resource consumption per good die out (Figure 1).

Figure 1. The basic equation for improving a fab’s environmental performance includes reducing resource use and increasing yield. Capable process control solutions help fabs do both by identifying process issues early thereby reducing scrap and rework.

Figure 1. The basic equation for improving a fab’s environmental performance includes reducing resource use and increasing yield. Capable process control solutions help fabs do both by identifying process issues early thereby reducing scrap and rework.

Improved process control performance

Process control is used to identify manufacturing excursions, providing the data necessary for IC engineers to make production wafer dispositioning decisions and to take the corrective actions required to fix process issues.

For example, if after-develop inspection (ADI) data indicate a high number of bridging defects on patterned wafers following a lithography patterning step, the lithography engineer can take several corrective actions. In addition to sending the affected wafers back through the litho cell for rework, the engineer will stop production through the litho cell to fix the underlying process issue causing the yield-critical bridging defects. This quick corrective action limits the amount of material impacted and potentially scrapped.

To be effective, however, the quality of the process control measurement is critical. If an inspection or metrology tool has a lower capture rate or higher total measurement uncertainty (TMU), it can erroneously flag an excursion (false alarm), sending wafers for unnecessary rework, causing additional consumption of energy and chemicals and production of additional waste. Alternatively, if the measurement fails to identify a true process excursion, the yield of the product is negatively impacted and more dies are scrapped—again, resulting in less desirable environmental performance.

The example shown in Figure 2 examines the environmental impact of the process control data produced by two different metrology tools in the lithography cell. By implementing a higher quality metrology tool, the quality of the process control data is improved and the lithography engineers are able to make better process decisions resulting in a 0.1 percent reduction in unnecessary rework in the litho cell. This reduced rework results in a savings of approximately 0.5 million kWh of power and 2.4 million liters of water for a 100k WSPM fab—and a proportional percentage reduction in the amount of resist and clean chemicals consumed.

Figure 2. Higher quality process control tools produce better process control data within the lithography cell, enabling a 0.1 percent reduction in unnecessary rework that results in better environmental performance.

Figure 2. Higher quality process control tools produce better process control data within the lithography cell, enabling a 0.1 percent reduction in unnecessary rework that results in better environmental performance.

As a result of obtaining increased yield and reduced scrap, many fabs have upgraded the capability of their process control systems. To drive further improvements in environmental performance, fabs can benefit from utilizing the data generated by these capable process control systems in new ways.

Traditionally, the data generated by metrology systems have been utilized in feedback loops. For example, advanced overlay metrology systems identify patterning errors and feed information back to the lithography module and scanner to improve the patterning of future lots. These feedback loops have been developed and optimized for many design nodes. However, it can also be useful to feed forward (Figure 3) the metrology data to one or more of the upcoming processing steps [2]. By adjusting the processing system to account for known variations of an upcoming lot, errors that could result in wafer scrap are reduced.

For example, patterned wafer geometry measurement systems can measure wafer shape after processes such as etch and CMP and the resulting data can be fed back to help improve these processes. But the resulting wafer shape data can also be fed forward to the scanner to improve patterning [3-5]. Likewise, reticle registration metrology data can be used to monitor the outgoing quality of reticles from the mask shop, but it can also be fed forward to the scanner to help reduce reticle-related sources of patterning errors. Utilizing an intelligent combination of feedforward and feedback control loops, in conjunction with fab-wide, comprehensive metrology measurements, can help fabs reduce variation and ultimately obtain better processing results, helping reduce rework and scrap.

Fig 3

Figure 3. Multiple data loops to help optimize fab-wide processes. Existing feedback loops (blue) have existed for several design nodes and detect and compensate for process variations. New, optimized feedback loops (green) provide earlier detection of process changes. Innovative feed forward loops (orange) utilize metrology systems to measure variations at the source, then feed that data forward to subsequent process steps.

Earlier excursion detection reduces waste

Fabs are also reducing process excursions by adding process control steps. Figure 4 shows two examples of deploying an inspection tool in a production fab. In the first case (left), inspection points are set such that a lot is inspected at the beginning and end of a module, with four process steps in between. If a process excursion that results in yield loss occurs immediately after the first inspection, the wafers will undergo multiple processing steps, and many lots will be mis-processed before the excursion is detected. In the second case (right), inspection points are set with just two process steps in between. The process excursion occurring after the first inspection point is detected two days sooner, resulting in much faster time-to-corrective action and significantly less yield loss and material wasted.

Furthermore, in Case 1, the process tools at four process steps must be taken off-line; in Case 2, only half as many process tools must be taken offline. This two-day delta in detection of a process excursion in a 100k WSPM fab with a 10 percent yield impact results in a savings of approximately 0.3 million kWh of power, 3.7K liters of water and 3500 kg of waste. While these environmental benefits were obtained by sampling more process steps, earlier excursion detection and improved environmental performance can also be obtained by sampling more sites on the wafer, sampling more wafers per lot, or sampling more lots. When a careful analysis of the risks and associated costs of yield loss is balanced with the costs of additional sampling, an optimal sampling strategy has been attained [6-7].

Figure 4. Adding an additional inspection point to the line will reduce the material at risk should an excursion occur after the first process step.

Figure 4. Adding an additional inspection point to the line will reduce the material at risk should an excursion occur after the first process step.

Conclusion

As semiconductor manufacturers focus more on their environmental performance, yield management serves as a critical tool to help reduce a fab’s environmental impact. Fabs can obtain several environmental benefits by implementing higher quality process control tools, combinations of feedback and feedforward control loops, optimal process control sampling, and faster cycles of learning. A comprehensive process control solution not only helps IC manufacturers improve yield, but also reduces scrap and rework, reducing the fab’s overall impact on the environment.

References

  1. Examples:
    1. https://newsroom.intel.com/news-releases/intels-arizona-campus-takes-the-leed/
    2. http://www.tsmc.com/english/csr/green_building.htm
    3. http://www.ti.com/corp/docs/manufacturing/RFABfactsheet.pdf
    4. http://www.globalfoundries.com/about/vision-mission-values/responsibility/environmental-sustainability-employee-health-and-safety
  1. Moyer, “Feed It Forward (And Back),” Electronic Engineering Journal, September 2014. http://www.eejournal.com/archives/articles/20140915-klat5d/
  2. Lee et al, “Improvement of Depth of Focus Control using Wafer Geometry,” Proc. of SPIE, Vol. 9424, 942428, 2015.
  3. Tran et al, “Process Induced Wafer Geometry Impact on Center and Edge Lithography Performance for Sub 2X nm Nodes,” 26th Annual SEMI Advanced Semiconductor Manufacturing Conference, 2015.
  4. Morgenfeld et al, “Monitoring process-induced focus errors using high resolution flatness metrology,” 26th Annual SEMI Advanced Semiconductor Manufacturing Conference, 2015.
  5. “Process Watch: Sampling Matters,” Semiconductor Manufacturing and Design, September 2014.
  6. “Process Watch: Fab Managers Don’t Like Surprises,” Solid State Technology, December 2014.
  7. “Reducing Environmental Impact with Yield Management,” Chip Design, July 2012.

About the Authors:

Dr. David W. Price, Dr. Douglas Sutherland, and Ms. Kara L. Sherman are Senior Director, Principal Scientist, and Director, respectively, at KLA-Tencor Corp. Over the last 10 years, this team has worked directly with more than 50 semiconductor IC manufacturers to help them optimize their overall inspection strategy to achieve the lowest total cost. This series of articles attempts to summarize some of the universal lessons they have observed through these engagements

IC Insights recently released its new Global Wafer Capacity 2016-2020 report that provides in-depth detail, analyses, and forecasts for IC industry capacity by wafer size, by process geometry, by region, and by product type through 2020.  In 2008, 300mm wafers took over as the industry’s primary wafer size in terms of total surface area used. Furthermore, the number of 300mm wafer fabrication facilities in operation continues to grow and is expected to reach 100 this year (Figure 1).

Some highlights regarding 300mm wafer fabs are shown below.

•    A couple fabs that were scheduled to open in 2013 were delayed until 2014.  That, in conjunction with the closure of two large 300mm fabs by ProMOS in 2013, caused the number of active volume-production 300mm fabs to decline for the first time in 2013.

•    At the end of 2015, there were 95 production-class IC fabs utilizing 300mm wafers (there are numerous R&D IC fabs and a few high-volume fabs that make “non-IC” products such as CMOS image sensors using 300mm wafers, but these are not included in the count).

•    Currently, there are eight 300mm wafer fabs scheduled to open in 2017, which would be the highest single-year increase since 2014 when nine 300mm fabs were added.

•    By the end of 2020 there are expected to be 22 more 300mm fabs in operation, bringing the total number of 300mm fabs used for IC fabrication to 117.  If 450mm wafers enter production, the peak number of 300mm fabs may be somewhere around 125.  For comparison, the highest number of volume-production 200mm wafer fabs in operation was 210 (in December of 2015 there were 148).

Today’s 300mm wafer fabs can be huge, but they are being equipped in a modular format, with each “module” generally having the capacity to process somewhere around 25K-45K wafers per month.  Each module is closely connected to nearby fab modules.  TSMC has perfected this modular approach, with its Fab 12, 14, and 15 sites being expanded in phases.

Figure 1

Figure 1

Development of 450mm wafer technology continues to progress toward production, albeit at a tempered pace. Since lithography is one of the biggest challenges in the 450mm wafer transition, ASM Lithography’s announcement in March 2014 that it would temporarily hold off on the development of equipment for 450mm wafers made some in the industry believe it was a signal that the transition would never happen.  ASML reported also that the decision to postpone its 450mm development program was made at the request of its customers.

IC Insights does not believe that ASML’s announcement, along with a couple other signs of a pause in 450mm development, means the 450mm wafer transition won’t happen, but they do indicate that the pilot production status for 450mm won’t be reached until probably 2019.  Volume production might start two to three years after that.

IC Insights’ Global Wafer Capacity 2016-2020—Detailed Analysis and Forecast of the IC Industry’s Wafer Fab Capacity report assesses the IC industry’s capacity by wafer size, minimum process geometry, technology type, geographic region, and by device type through 2020. The report includes detailed profiles of the companies with the greatest fab capacity and gives comprehensive specifications on existing wafer fab facilities.

By Paul Trio (SEMI); Dalia Vernikovsky (Applied Seals NA)

Evolving Industry Priorities

As the microelectronics industry becomes more mature and products become more advanced, there is greater emphasis on improving process control deeper within the supply chain. Whereas much of the attention has historically been at the fab as well as on equipment and materials, the spotlight is now focused on components and subcomponents.

As the industry prepares for 7nm and beyond, there is a realization that high-volume manufacturing at these advanced process nodes will be gated by equipment parts performance. With device manufacturers refining advanced process recipes pushing equipment, components, and subcomponents to the fringes of their performance envelopes, control is paramount. Industry standards will be as important in providing consistent parameters to enable users to compare similar parts and assess performance differences.

The Seal Situation

The subcomponent industry challenge outlined above certainly rings true for elastomeric seals. “Seals were invented near the end of the 19th century and the disturbing fact is that their manufacturing, material composition, and overall position in the vast industry is industrial in nature,” said Dalia Vernikovsky (Applied Seals North America), SCIS co-chair,  “Unless this industry comes together to forge guidelines or standards that correlate to SEMI’s stringent applications, and we bring the awareness that seal language still correlates to the mechanical make-up (thus the metal adders and constituents of things such as magnesium ferrous oxides), not the cleanliness specifications required, 7nm manufacturing will see defects traced to those components long after they are incorporated.”

Sealed with a Standard

With a myriad of applications and a variety of options, it is often difficult for users to select appropriate sealing materials. This problem is further compounded when O-ring suppliers use different criteria for quantifying O-ring performance coupled with inconsistent parameters and test methods. Control is key: making the right choice is essential for improving equipment uptime and reducing operational costs.

SEMI F51, Guide for Elastometric Sealing Technology, has been in publication since early 2000. This Document is a basic guide for the use of seals in semiconductor fabrication equipment. However, in order to meet the latest customer requirements, the standard needed an overhaul.

In 2014, the F51 Revision Task Force, under the North America Facilities Technical Committee Chapter was chartered to bring the standard to current industry specs. After a few ballot attempts, the task force’s 5080B proposal passed technical committee review at SEMICON West 2015 (July). By fall, the 5080B Ratification Ballot met the required acceptance conditions as well as clearing the necessary procedural reviews by the ISC Subcommittee on Audits & Reviews. The latest version of SEMI F51was published in November 2015 is now available for purchase from SEMI. It defines the criteria by which sealing performance can be judged in comparable measurements and seal materials can be chosen.

Behind the Scenes: A SEMI Special Interest Group

Determining how the SEMI F51 Standard would be revised didn’t happen overnight. Even before the F51 Revision Task Force was chartered, another SEMI group architected the characterization of seals parameters required at these advanced process nodes.

The Seals Group first identified seal performance criteria in several applications or process areas. The performance criteria was mainly divided into two groups: sealing requirements (e.g., etch rate, sealing force retention) and impurities (e.g., leachable, ash, outgassing, total organic carbon [TOC] testing). Process areas included: wet etch, etch, CVD/PVD, diffusion, and sub-fab.

Once the parameters were identified, the group prioritized which characteristics it needed to focus on. These included TOC, surface extractable metal contamination, and ash metal analysis. The Seals Group then developed test methodologies for measuring each performance. If test methods or standards already existed, the group simply referenced them.

Relative Importance of Seal Performance Criteria in Several Applications/Process Areas (1 – most important, 5 – least important) Figure 1

The Seals Group is part of a SEMI Special Interest Group (SIG) focused on Semiconductor Components, Instruments, and Subsystems (SCIS). SEMI SIGs provide a forum that fosters discussion and aligns stakeholders on industry-critical issues. SCIS represents companies that produce, package and/or distribute any of the following used in semiconductor or related industries:

  • Components such as seals, filters, mass flow controllers, valves, sensors, ion beam sources, etc.
  • Instruments for in-line and off-line data measurement, collection, and monitoring
  • Sub-systems that support process tools such as vacuum, robotics, power conversion, abatement, chillers, etc.

SCIS participation encompass Subcomponent-OEM-IDM stakeholders, including: Applied Seals NA; ASM; Brooks Automation; Busch Vacuum; Ebara; Edwards Vacuum; Entegris; Festo; GLOBALFOUNDRIES; Greene, Tweed; Horiba; Intel; KLA-Tencor; Lam Research; Pall; Parker; SMC; Swagelok; Texas Instruments; UltraClean Technology; VAT Valve.

SEMI SCIS SIG – Addressing Defectivity Problems in HVM

With defect and traceability playing a critical role in enabling high-volume manufacturing, SCIS is currently structured to focus on these problem areas. It aims to establish a framework that will enable industry partners to define:

  • Measurable defects for different components specific to intended process applications
  • Standardized test methods to measure the defects
  • Consistent methods for reporting the results

“Increased collaboration is required to establish new industry standards and parameters associated with semiconductor process control to meet the ever increasing yield, variability, and reliability challenges that comes with continued technology scaling,” said Gary Patton, CTO and SVP of WW R&D at GLOBALFOUNDRIES. “The SEMI SCIS group is playing a very crucial role in driving alignment between semiconductor manufacturers and equipment and sub-component suppliers on successful standards for sub-component defectivity and traceability needed for future technology nodes.”

The Seals Group is just one of four subteams under SCIS focused on defectivity. Subteams are established in the following areas:

  • Valves, Seals, and Pumps
  • Liquid and Gas Delivery
  • Critical Chamber Components and RF
  • Automation

As of this writing, each SCIS subteam has identified at least one process-critical component considered to be a primary contributor to defects:

Scope of Defectivity Components Figure 2

The subteams are now focusing on establishing a standard system of comparable metrics which will be used to rate, compare, and classify each of these identified components. This process is dictated by the following template:

SCIS Defectivity Template Figure 3

The Seals Group is not resting on its laurels with the latest revision to SEMI F51. The Seals team is now working on the next set of parameters including: sealing force retention, etch rate (range), permeation, and particles (size and range).

Visibility with Traceability

SCIS is also addressing the need for improved component parts traceability that will enable effective problem diagnosis and faster resolution.

Consider this rather common scenario: Fab yield excursion is traced to a batch of custom machined parts manufactured by Supplier A on a pump supplied by Supplier B on a process tool manufactured by Supplier C.  Fab engineer requests Supplier C to provide a list of all affected systems and spares to enable global containment plan. Without a standardized traceability process in place, the list takes a week to compile, introducing delays to the corrective action. 

The Traceability Verification Subteam under SCIS is chartered to implement an industry standard parts traceability process that will:

  • Define standardized formats and protocols
  • Facilitate communication among suppliers, OEMs, and IDMs.
  • Enable efficient problem diagnosis and resolution

“The Traceable Verification Model ensures Key Characteristics are controlled with compliance information easily accessed via a cloud based application. Intellectual property is secured via pre-approved access levels. The model holds all suppliers accountable but also ensures proprietary information is not compromised.” said Lance Dyrdahl (Lam Research), Defect Traceability Subteam leader.

Full Circle Engagement

As with the F51 seals activity, output from these SCIS Subteams will feed in to the various committees and task forces under the SEMI International Standards Program. As these Standards are used by the industry, new requirements will emerge and it will be up to SEMI Members to address them.

“Components standards should be effectively linked to the field performance for all-around benefits to component makers, OEMs and IDMs. The committee deliverables are structured to allow competitors to work together in driving commonality. Standardization and normalization methodology will provide IP-free participation.” said Ya-hong Neirynck (Intel), SCIS RF subteam co-leader. Lance Dyrdahl further pointed out, “Speedy ratification occurs when all participants agree on self-evident non-proprietary methods.”

The demands of the next-generation high-volume manufacturing will no doubt require a concerted effort among device manufacturers, OEMs, and suppliers. Diverse stakeholder participation is critical in solving these problems proactively. Failure to do so will certainly result in greater challenges (and pain) that will be shared by all.  “A piece of equipment or process line is only as strong as its weakest component,” said Sanchali Bhattacharjee (Intel), SCIS cochair.

Engaging in these SEMI SCIS initiatives provides a very strong value proposition for IDM-OEM-suppliers alike.

Engaging in SEMI SCIS Benefits All Industry Stakeholders Figure 4

The SEMI SCIS Special Interest Group is open to all SEMI Members. There will be an SCIS face-to-face meeting in conjunction with the SEMI Advanced Semiconductor Manufacturing Conference (ASMC) – May 16-19, 2016 – in Saratoga Springs, New York. Conference attendees are welcome to attend this face-to-face meeting. Future face-to-face meeting are also scheduled for SEMICON West 2016 (July) as well as the SEMI Strategic Materials Conference (SMC) in September. SCIS subteams meet via teleconference in between these face-to-face meetings. For more information or to join the SCIS SIG, please contact Paul Trio at SEMI ([email protected]).

Samsung Electronics Co., Ltd. announced today that it has begun mass producing the industry’s first 10-nanometer (nm) class, 8-gigabit (Gb) DDR4 (double-data-rate-4) DRAM chips and the modules derived from them. DDR4 is quickly becoming the most widely produced memory for personal computers and IT networks in the world, and Samsung’s latest advancement will help to accelerate the industry-wide shift to advanced DDR4 products.

Samsung 10nm-class DRAM-Group_002

Samsung opened the door to 10nm-class DRAM for the first time in the industry after overcoming technical challenges in DRAM scaling. These challenges were mastered using currently available ArF (argon fluoride) immersion lithography, free from the use of EUV (extreme ultra violet) equipment.

Samsung’s roll-out of the 10nm-class (1x) DRAM marks yet another milestone for the company after it first mass produced 20-nanometer (nm) 4Gb DDR3 DRAM in 2014.

“Samsung’s 10nm-class DRAM will enable the highest level of investment efficiency in IT systems, thereby becoming a new growth engine for the global memory industry,” said Young-Hyun Jun, President of Memory Business, Samsung Electronics. “In the near future, we will also launch next-generation, 10nm-class mobile DRAM products with high densities to help mobile manufacturers develop even more innovative products that add to the convenience of mobile device users.”

Samsung’s leading-edge 10nm-class 8Gb DDR4 DRAM significantly improves the wafer productivity of 20nm 8Gb DDR4 DRAM by more than 30 percent.

The new DRAM supports a data transfer rate of 3,200 megabits per second (Mbps), which is more than 30 percent faster than the 2,400Mbps rate of 20nm DDR4 DRAM. Also, new modules produced from the 10nm-class DRAM chips consume 10 to 20 percent less power, compared to their 20nm-process-based equivalents, which will improve the design efficiency of next-generation, high-performance computing (HPC) systems and other large enterprise networks, as well as being used for the PC and mainstream server markets.

The industry-first 10nm-class DRAM is the result of Samsung’s advanced memory design and manufacturing technology integration. To achieve an extremely high level of DRAM scalability, Samsung has taken its technological innovation one step further than what was used for 20nm DRAM. Key technology developments include improvements in proprietary cell design technology, QPT (quadruple patterning technology) lithography, and ultra-thin dielectric layer deposition.

Unlike NAND flash memory, in which a single cell consists of only a transistor, each DRAM cell requires a capacitor and a transistor that are linked together, usually with the capacitor being placed on top of the area where the transistor rests. In the case of the new 10nm-class DRAM, another level of difficulty is added because they have to stack very narrow cylinder-shaped capacitors that store large electric charges, on top of a few dozen nanometer-wide transistors, creating more than eight billion cells.

Samsung successfully created the new 10nm-class cell structure by utilizing a proprietary circuit design technology and quadruple patterning lithography. Through quadruple patterning, which enables use of existing photolithography equipment, Samsung also built the core technological foundation for the development of the next-generation 10nm-class DRAM (1y).

In addition, the use of a refined dielectric layer deposition technology enabled further performance improvements in the new 10nm-class DRAM. Samsung engineers applied ultra-thin dielectric layers with unprecedented uniformity to a thickness of a mere single-digit angstrom (one 10 billionth of a meter) on cell capacitors, resulting in sufficient capacitance for higher cell performance.

Based on its advancements with the new 10nm-class DDR4 DRAM, Samsung expects to also introduce a 10nm-class mobile DRAM solution with high density and speed later this year, which will further solidify its leadership in the ultra-HD smartphone market.

While introducing a wide array of 10nm-class DDR4 modules with capacities ranging from 4GB for notebook PCs to 128GB for enterprise servers, Samsung will be extending its 20nm DRAM line-up with its new 10nm-class DRAM portfolio throughout the year.

The Semiconductor Industry Association (SIA) today announced worldwide sales of semiconductors reached $26.0 billion for the month of February 2016, a decrease of 3.2 percent compared to the previous month’s total of $26.9 billion and 6.2 percent lower than the February 2015 total of $27.7 billion. Sales into the Americas fell sharply, decreasing 19.3 percent year-to-year, while year-to-year sales into China increased 3.5 percent. All monthly sales numbers are compiled by the World Semiconductor Trade Statistics (WSTS) organization and represent a three-month moving average.

“Global semiconductor sales slipped somewhat in February, due to normal seasonal trends, demand softening, and unfavorable macroeconomic conditions,” said John Neuffer, president and CEO, Semiconductor Industry Association. “Most regional markets have struggled to overcome these headwinds, and sales have dipped across the majority of semiconductor product categories.”

Regionally, sales decreased nearly across the board: China (-4.6 percent month-to-month/+3.5 percent year-to-year), Europe(-0.9 percent/-6.3 percent), Japan (-0.8 percent/-3.5 percent), Asia Pacific/All Other (-0.7 percent/-6.3 percent), and the Americas (-7.0 percent/-19.3 percent).

Sales also decreased across most major semiconductor product categories, with the notable exception of microprocessors, which increased year-to-year by 3.4 percent.

February 2016

Billions

Month-to-Month Sales                               

Market

Last Month

Current Month

% Change

Americas

5.41

5.03

-7.0%

Europe

2.72

2.70

-0.9%

Japan

2.49

2.46

-0.8%

China

8.42

8.03

-4.6%

Asia Pacific/All Other

7.85

7.80

-0.7%

Total

26.89

26.02

-3.2%

Year-to-Year Sales                          

Market

Last Year

Current Month

% Change

Americas

6.23

5.03

-19.3%

Europe

2.88

2.70

-6.3%

Japan

2.55

2.46

-3.5%

China

7.76

8.03

3.5%

Asia Pacific/All Other

8.32

7.80

-6.3%

Total

27.74

26.02

-6.2%

Three-Month-Moving Average Sales

Market

Sep/Oct/Nov

Dec/Jan/Feb

% Change

Americas

6.07

5.03

-17.1%

Europe

2.93

2.70

-8.1%

Japan

2.68

2.46

-8.0%

China

8.67

8.03

-7.4%

Asia Pacific/All Other

8.53

7.80

-8.6%

Total

28.88

26.02

-9.9%