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The European Commission has approved under the EU Merger Regulation the acquisition of Broadcom Corporation by Avago Technologies Limited. Both companies are global manufacturers of semiconductors. The Commission concluded that the merged entity would continue to face effective competition in Europe.

Commissioner Margrethe Vestager, in charge of competition policy, said: “Thanks to very good cooperation with the companies the Commission has been able to approve this multi-billion dollar takeover within a very short space of time while preserving effective competition in this crucial high-technology sector.”

The Commission’s investigation showed that the portfolios of the companies are mainly complementary since Broadcom makes “off-the-shelf” chips for the broadband and connectivity market segments, while Avago makes custom-built chips for special applications in the analog wireless integrated circuits, enterprise, storage and industrial segments.

Nevertheless, the Commission had some concerns about the vertical relationship created by the transaction, since Avago supplies certain intellectual property (technology for allowing fast data transmission between chips) to some of Broadcom’s competitors. The Commission’s concern was that after the takeover Avago could have had an incentive to withhold this intellectual property in order to extend the merged entity’s leading market position in the so-called “switch chips” market.

However, already during the Commission’s assessment of the case, Avago addressed these concerns by entering into commercial agreements with other “switch chip” manufacturers. These agreements will ensure that other “switch chip” manufacturers will continue to have access to the necessary intellectual property on reasonable terms. Thanks to this up-front solution, the Commission has been able to unconditionally clear the proposed transaction, which was notified on October 2, 2015.

Related news: 

Avago Technologies acquisition of Broadcom creates a new semiconductor powerhouse

Historic era of consolidation for chipmakers

ON Semiconductor Corporation and Fairchild Semiconductor International Inc. today announced plans for ON Semiconductor to acquire Fairchild for $20.00 per share in an all cash transaction valued at approximately $2.4 billion. The acquisition creates a leader in the power semiconductor market with combined revenue of approximately $5 billion, diversified across multiple markets with a strategic focus on automotive, industrial and smartphone end markets.

“The combination of ON Semiconductor and Fairchild creates a power semiconductor leader with strong capabilities in a rapidly consolidating semiconductor industry. Our plan is to bring together two companies with complementary product lines to offer customers the full spectrum of high, medium and low voltage products,” said Keith Jackson, president and chief executive officer of ON Semiconductor. “The immediate EPS accretion and potential to significantly augment ON Semiconductor’s free cash flow, make the Fairchild acquisition an excellent opportunity for ON Semiconductor stockholders.”

“As part of ON Semiconductor, Fairchild will continue to pioneer technology and design innovation in efficient energy consumption to help our customers achieve success and drive value for our partners and employees around the world,” stated Mark Thompson, chairman and chief executive officer of Fairchild. “We look forward to working closely with the ON Semiconductor team to ensure a smooth transition.”

Following consummation, the transaction is expected to be immediately accretive to ON Semiconductor’s non-GAAP earnings per share and free cash flow, excluding any non-recurring acquisition related charges, the fair value step-up inventory amortization, and amortization of acquired intangibles. ON Semiconductor anticipates achieving annual cost savings of $150 million within 18 months after closing the transaction.

The transaction is not subject to a financing condition. ON Semiconductor intends to fund the transaction with cash from the combined companies balance sheet and $2.4 billion of new debt. The debt financing commitment also includes provisions for a $300 million revolving credit facility which will be undrawn at close. ON Semiconductor remains committed to its share repurchase program, and the agreed upon financing provides flexibility to continue share repurchases going forward.

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CEA-Leti and its partners in the European FP7 project PLAT4M today announced they have built three silicon photonics platforms. The four-year project, which launched in 2013, aims at building a European-based supply chain in silicon photonics and speeding industrialization of the technology. PLAT4M, which is funded by a European Commission grant of 10.2 million euros, includes 15 leading European R&D institutes and CMOS companies, key industrial and research organizations in design and packaging, as well as end users in different application fields, to build the complete supply chain.

Midway through the project, the consortium has developed advanced technologies and tools by building a coherent design flow, demonstrating manufacturability of elementary devices and process integration, and developing a packaging toolkit. The supply chain is based on technology platforms of Leti, imec and STMicroelectronics, supported by a unified design environment. The high level of maturity of the technology offered by these platforms makes them readily accessible to a broad circle of users in a fabless model.

Imec’s silicon photonics platform, based on 200mm substrates, has matured thanks to the PLAT4M project. The platform is based on SOI substrates with 220nm crystalline silicon on a 2,000nm buried oxide. During this project the existing fabrication processes and integration flow have been fine tuned to have stable and repeatable performance for all photonics building blocks (couplers, waveguides, phase shifters, photodetectors). This feeds the process design kit’s robust performance specifications and guarantees quality and first-time-right designs for the platform’s fabless users for high data-rate telecom and non-telecom applications. PLAT4M partners Thales, Polytec and TNO already are using the technology.

Beyond the 200mm platform, imec has pushed the limits of silicon photonics, exploiting advanced optical lithography with its 193nm immersion lithography scanner. It also has demonstrated very low propagation loss (~0.6dB/cm) for fully etched waveguides with excellent within-wafer linewidth control (standard deviation

Using the imec platform, Thales demonstrated a coherent combination of laser beams (CBC). Ultimately, this application aims at producing high-power, high-energy laser sources for sensing, industry or fundamental physics. The CBC rationale is to push the limits of single laser emitters (typically fiber amplifiers) by using a large number of amplifiers and coherently adding the output beams. The coherent addition requires locking the phase of all the amplifying channels. With the number of channels, potentially very large (from tens to thousands), an integrated technology is a major concern in terms of possible industrial products. The first generation CBC demonstrator of PLAT4M, which was packaged by Tyndall UCC, included a one-to-16 channel splitter tree, plus 16 independent thermal phase modulators. The CBC experiment showed the successful coherent addition of 16 laser beams at 1.55µm.

cea-leti supply chain

Leti has developed a new photonic platform based on 200mm SOI wafers. This process offers multilevel silicon patterning that allows the design of various passive and active devices (e.g. modulator and photodiode) with thermal tuning capability. Two AlCu levels are available for routing. A process design kit (PDK) is available for circuit design and an MPW service will be proposed in 2016. State-of-the-art performances have been demonstrated: insertion losses are below 2dB/cm for monomode waveguide and below 0.2dB/cm for multimode devices. Germanium photodiode responsivity is > 0.75A/W for a bandwidth >30GHz. Mach-Zehnder modulator VpLp is in the 2V.cm range for 2V operation with an E/O bandwidth > 25GHz. Moreover, Leti and III-V Lab have developed integrated hybrid III-V lasers and electro-absorption modulators (EAM) on silicon using a wafer-bonding technique. The hybrid lasers operate in the single-mode regime and the EAMs exhibit an extinction ratio higher than 20 dB with a drive voltage lower than 2V. Clear eye diagram has been achieved at a bit-rate of 25 Gb/s, confirming strong potential for telecom applications.

During the project, ST developed an additional silicon-photonic platform in 300mm technology to be used as an R&D tool for proof-of-concept purposes. The technology, called DAPHNE (Datacom Advanced PHotonic Nanoscale Environment), is designed for evaluating new devices and subsystems for demonstration. DAPHNE is a flexible platform that perfectly fits R&D needs. While developing it, ST demonstrated wavelength-division-multiplexing solutions using arrayed waveguide gratings, echelle gratings, cascaded Mach-Zehnder interferometers and side-coupled integrated spaced sequence of resonators. Some of the configurations are designed for the 100GBase-LR4 standard, and the experimental characterization results show insertion losses below 0.5dB and channel cross-talks above 25dB for a band flatness of 2nm. Furthermore, proper operation of receiver-and-transmitter blocks to be interfaced to optical devices above them has been demonstrated at 28Gbps, making use of 65nm-node technologies.

The PLAT4M WP2 work has led to a qualitative leap of the design flow for silicon photonics, allowing the photonics community to design more complex and more robust circuits. The electronics OpenAccess standard for data sharing between design-automation tools includes an extension for silicon photonics in a beta phase today. Simulation capabilities were leveraged thanks to an extensive characterization effort from the three partner fabs and thanks to the statistical data gathered for variability prediction. Paris-Sud University has studied theoretically the behavior of different phase shifters and photodetectors for a time-efficient and precise modeling. Mentor Graphics and PhoeniX Software partners have improved phase-aware routing and tool interoperability. Verification and manufacturability have reached industry-requirement standards thanks to the development of new techniques based upon the Mentor Graphics Calibre platform that delivers layout-versus-schematic comparison (Calibre nmLVS), photonic rule checks (PRC) and curvilinear-aware design-rule checks (Calibre nmDRC). Mask preparation is also improving with better pattern-density control and mask correction.

Vacuum technology trends can be seen over the period of innovation defined by Moore’s Law, particularly in the areas of increasing shaft speed, management of pumping power, and the use computer modeling.

BY MIKE CZERNIAK, Edwards UK, Crawley, England

The sub-fab lies beneath. And down there in that thicket of pipes amidst the hum of vacuum pumps, the sentinel of gas combustors and the pulse of muscular machinery doing real work — innovation has also played a crucial role in enabling Moore’s Law. Without it the glamor boys up top with their bunny suits and FOUPS would not have achieved the marvelous feats of engineering derring-do for which they are so deservedly celebrated.

Vacuum and abatement are two of the most critical functions of the sub-fab. Many process tools require vacuum in the process chamber to permit the process to function. Vacuum pumps not only provide the required vacuum, they also remove unused process gases and by-products. Abatement systems then treat those gasses so they are safe to release or dispose. Vacuum and abatement systems in the sub-fab have had to innovate just as dramatically as the exposure, deposition and etch tools of the fab. In many cases, new processes would not have been possible without new vacuum pumps that could handle new materials and new abatement systems that could make those materials safe for release or disposal.

Moore’s Law

Moore’s Law originated in a paper published in 1965 and titled “Cramming More Components onto Integrated Circuits,” written by Gordon Moore, then director of research and engineering at Fairchild Semiconductor [1]. In it Moore observed that the economics of the integrated circuit manufacturing process defined a minimum cost at a certain number of components per circuit and that this number had been doubling every two years as the manufacturing technology evolved. He believed that the trend would continue for at least the short term, and perhaps as long as ten years. His observation became a mantra for the industry, soon to be known as Moore’s Law (FIGURE 1).

Vaccuum 1

More an astute observation than a law, Moore’s Law is remarkable in several respects. First, the rate of improvement it predicts, doubling every two years, is unheard in any other major industry. In “Moore’s Curse” (IEEE, March 2015) Vaclav Smil calculated historical rates of improvement for a variety of essential indus- tries over the last couple of centuries and found typical rates of a few percent, and order of magnitude less than Moore’s rate [2]. Second, is its longevity. Moore thought it was good for the short term, perhaps as long as ten years. This is perhaps due, at least partly, to the unique role Moore’s Law has assumed within the semicon- ductor industry where it has become both a guide to and driver of the pace of innovation. The Law has become a guiding principle – you shall introduce a new generation with double the performance every two years. It is a rule to live by, enshrined in the industry’s roadmap, and violated only at great peril. Only painfully did Intel recently admit that the doubling period for its latest generation appeared to have stretched to something more like two and a half years [3]. To an extent the Law is a self-fulfilling prophecy, which some have argued works to the detriment of the industry when it forces the release of new processes before they are fully optimized. Whatever you might think of it, the Law’s persistence is remarkable. The literature is full of dire predictions of its demise, all of which, at least so far, have proven premature.

Finally we must ask, what is meant by the names assigned to each new node? What exactly does 14nm, the current state of the art, mean? Although Moore originally described the number of components per integrated circuit, the Law was soon interpreted to apply to the density of transistors in a circuit. This was variously construed. Some measured it as the size of the smallest feature that could be created, which determined the length of the transistor gate. Others pointed to the spacing between the lines of the first layer of metal conductors connecting the transistors, the metal-1 half-pitch. These may have been a fairly accurate measures twenty years ago at the 0.35μm node, but node names have since steadily lost their connection to physical features of the device. It would be difficult to point to any physical dimension at the 14nm node that is actually 14nm. For instance, the FinFET transistor in a 22nm chip is 35nm long and the fin is 8nm wide.

What remains true is that in each successive generation the transistors are smaller and more densely packed and performance is significantly increased. Each generation seems to be named with a smaller number that is approximately 70% of the previous generation, reflecting the fact that a 70% shrink in linear dimension equates to a 50% reduction in area and therefore a nominal doubling in transistor density.

Enabling Moore’s Law in the sub-fab: A brief chronology

In the 1980s, new semiconductor processes and increasing gas flows associated with larger diameter wafers led to problems with aggressive chemicals and solids collecting in the oil used in oil-lubricated “wet” pumps, resulting in short service intervals and high cost of ownership. These were resolved by the development and introduction of oil-free “dry pumps” which have subsequently become the semiconductor industry standard.

Dry rotary pumps require extremely tight running clearances and multiple stages to achieve a practical level of vacuum. Additional cost of these machines, however was more than offset by the benefits offered to semiconductor manufacturing. Dry pumps use a variety of pumping mechanisms — roots, claw, screw and scroll (FIGURE 2).

Vaccuum 2

Many of these are new concepts, but modern machining capabilities made it possible to produce them at a realistic cost, the most notable being Edwards’ introduction of the first oil-free dry pump in the 1980’s. Each pumping mechanism has been successfully deployed and each has its own advantages and disadvantages in a given application. The scroll pump, for example, is unique in its ability to economically scale down to much smaller sizes.

In the early 1990s it became apparent that with the introduction of dry pumps, the pump oil no longer acted as a “wet scrubber” to collect process by-product gases, which therefore passed into the exhaust system. The solution was the development of the Gas Reactor Column (GRC) to chemically capture process exhaust gases in a disposable/recyclable cartridge, minimizing exhaust emissions to the atmosphere.

At about the same, new, more aggressive process gases being used in leading-edge semiconductor processes posed significant challenges for turbo molecular pumps (TMPs) due to the damage they caused to the mechanical bearings used to support their high-speed rotating shafts (typically ~40,000 rpm). Turbo pumps use rapidly spinning blades to impart direction to gas molecules, propelling them through multiple stages of increasing pressure. Early turbo pumps used oil- or grease-lubricated bearings. Similar to the problems encountered with oil sealed rotary pumps, the new process chemicals tended to degrade the oil, frequently causing pumping failures in as little as a few weeks. This problem was solved by introducing magnetic bearings to levitate the pump drive shaft and eliminate the need for lubricating oil.

In the mid-1990s the semiconductor industry started to use perfluorinated compounds (PFC’s) as a convenient source of chamber cleaning and etch gases. However, since only ~30% of the input gas was consumed in the process chamber, there were considerable PFC emissions to the atmosphere. Of particular concern was CF4 due to its half-life of 50,000 years. The solution was the Thermal Processor Unit which offered the first system with proven destruction reaction efficiency (DRE) of 90% or more for CF4.

In the 2000’s safety concerns regarding the increasing use of toxic gases led to increasing concerns about the abatement of these materials before they were released to the environment and the safety of personnel within the fab. Integrated vacuum and abatement systems, where everything is contained in a sealed and extracted enclosure, offer a significant improvement in safety. Integrated systems have since been refined with improvements such as a common control system, reduced footprint and installation costs, and shorter pipelines to reduce operating and maintenance costs.

Abatement systems have continued to evolve. New processes using new materials often require a different approach the abatement. For example, new technologies were developed for high hydrogen processes, copper interconnects and low k dielectrics.

Trends and prospects

Certain vacuum technology trends can be seen over this history of innovation, particularly in the areas of increasing shaft speed, management of pumping power, and the use computer modeling to monitor performance and predict when maintenance will be required so that it can be synchronized with other activities in the fab.

Shaft Speed

When dry pumps were first introduced, they typically operated at around 3,000 to 3,600 rpm. Today’s dry pumps use electric drives to run considerably faster, typically 6,000 rpm for claw, screw, and multi-stage roots pumps (FIGURE 3).

Vaccuum 3

Increasing a pump’s rotational speed delivers a number of advantages. It makes it possible to build more compact pumps and motors, with less internal leakage, which in turn, enables a reduction in the number of pump stages required. It also allows the speed to be reduced when wafers are not being processed, thereby saving energy. Combined, these benefits help reduce the overall pump cost.

Each type of pumping mechanism has different characteristics in the size and shape of volume to fill. A scroll mechanism, with a narrow, ported inlet and long, thin volume space, is one of the slowest pumping mechanisms to fill, so its performance does not increase in proportion to increasing shaft speed. Most scroll pumps operate at just 1500 rpm. A roots mechanism, by contrast, has a very large opening and a short volume length, enabling it to fill quickly allowing efficient use of higher shaft speeds.

The conductance ceiling for roots and screw pumps is probably ~15,000 rpm. Achieving this speed, will require incremental improvements in materials, bearings, and drives. It is likely that we will reach the conductance ceiling for most of the current primary pumping mechanisms within the next decade, although some, such as roots and screw mechanisms, may prove more durable than others.

Turbomolecular pump conductance is governed by blade speed and molecular velocities. Turbo performance has been limited primarily by the maximum speed the bearings and rotor can withstand. The industry is looking for new materials that are lighter and stronger to enable increased speed. While this pump type may be reaching its conductive limit on heavier gases, it is far from reaching it for lighter gases, such as hydrogen. This may take a much longer time to achieve.

Power management

Significant advances have been made in improving the energy efficiency of both vacuum pumps and abatement systems. Improvements in pump design have increased energy efficiency. Variable speed motors and controllers allow better matching of the motor speed to varying pump requirements. Idle mode allows both pumps and abatement systems to go into a low power mode when not in use. Improvements in burner design have reduced the fuel consumption of combustion based abatement. With the increase in concern about environmental impact and carbon foot print continued improvement in this area can be expected.

Modeling

Computer modeling has been applied extensively to all stages of pump performance. Such variables as stage size, running clearance, leakage, and conductance can all be modeled quite effectively. This allows design simulation and the optimization of performance, such as the shape of the power and speed curve. In this way, a pump can be designed for specific duties, such as load lock pumping or processing high hydrogen flows (FIGURE 4).

Vaccuum 4

Vacuum pumps of the future will be more reliable and capable of operating for longer periods of time before requiring maintenance. They will be safer to operate, will occupy less fab space, run cleaner and require less power, as well as generate less noise, vibration, and heat. They will also have improved corrosion resistance and the ability to run hotter when required.

As a result, vacuum pumps will be more environmentally friendly, running cleaner and using less power to help reduce their carbon footprint. In addition, they will likely make much greater use of recycled materials and use fewer consumables, thereby helping to reduce overall pump costs. The pumps will be easier to clean, repair, and rebuild for reuse.

Likely technical developments will also include higher shaft speeds, a growing proliferation of pump mechanisms and combinations of mechanisms to increase performance. Finally, vacuum pumps will incorporate new materials and improved modelling to further sharpen performance and reduce system and operating costs.

References

1. G. Moore, “Cramming more Components onto Integrated Circuits” in Electronics, April 19, 1965.
2. V. Smil, “Moore’s Curse” in IEEE Spectrum, March 19, 2015.
3. R. Courtland, “The Status of Moore’s Law: It’s Complicated” in IEEE Spectrum October 28, 2013.

MIKE CZERNIAK is the Environmental Solutions Business Development Manager, Edwards UK, Crawley, England.

The availability of patterning alternatives in the lithography landscape represents a big opportunity to properly address the coming needs generated by the IoT.

BY LAURENT PAIN, RALUCA TIRON, LUDOVIC LATTARD, STEFAN LANDIS and CYRILLE LAVIRON, CEA-Leti, Grenoble, France

The Internet of Things (IoT) is expected to fuel significant growth opportunities for the semiconductor industry, as demand increases for wireless components and more and more embedded functionalities such as memory and sensors. This growth will affect almost all integrated circuit (IC) sectors (FIGURE 1). The chip industry will continue to need advanced technologies to provide the most powerful functionalized ICs with lower power consumption for the IoT, but manufacturing costs remain a key challenge. Lithography and related patterning technologies can represent up to 50 percent of total IC production costs, and significant efforts have to be made in the coming years to slow and even reverse this trend.

Litho Fig 1

In the lithography landscape for the development of advanced technology nodes, extreme-UV (EUV) lithography technology recovered some credibility at the beginning of 2015 with the release and installation of the first 80W power sources[1]. However, its adoption by the industry remains uncertain, because its infrastructure still requires significant development. Also, the recurrent questions about the real cost of ownership associated with the ability of the 0.33NA platform to address sub-7nm technology nodes continue to dominate the debate in the semiconductor community, especially since 3D-stacking strategies are being seriously investigated. This potentially could slow demand for high-resolution and therefore delay the new advanced lithography solutions.

Meanwhile, 193nm immersion lithography, with double- or quadruple-patterning strategies, supports the industry preference for advanced-node developments, despite the tremendous effort required for process controls (alignment, mask manufacturing etc.). In this landscape, lithography alternatives maintain promise for continued R&D because they may present competitive compromises for the industry. Massively parallel electron-beam and nano-imprint lithography techniques remain highly attractive, as they can provide noteworthy cost-of-ownership benefits for IC manufacturers. In addition, directed self-assembly (DSA) lithography with block copolymer shows promising resolution capabilities and appears to be an option to reduce multi-patterning strategies, and therefore the associated mask-set budgets. But what is the current status of these technologies? Are they really able to meet industry expectations for advanced technology nodes? Are they indeed able to reduce manufacturing costs? What are their introduction points into the production environment?

CEA-Leti is working to answer these questions and has initiated collaborative R&D programs to assess and boost the development of these alternative technologies through strategic partnerships. Three programs have been launched with the primary goals of demonstrating that these lithography options can meet industry needs, assessing industrial use of them and proposing to Leti’s IDM partners real turn-key integrated process-flow solutions.

  • IMAGINE: launched in 2009 with MAPPER Lithography, this program is pushing for the insertion of massively parallel direct-write electron-beam technology. Other participants include TSMC, STMicroelectronics, Nissan Chemical, Mentor Graphics, SCREEN, Tokyo Electron and Aselta Nanographics.
  • IDEAL: DSA lithography represents a promising solution for advanced patterning. Leti has worked with Arkema since 2011 on the qualification and demonstration of materials for insertion into industrial production flow. Other partners include ST, Tokyo Electron, SCREEN, Mentor Graphics and CNRS-LCPO.
  • INSPIRE: established in 2015 with the EV Group, this program will focus on the assessment of imprint technology on large-scale patterning.

Directed self assembly: the resolution is in polymer matrix

Since 2010, DSA has steadily attracted attention of R&D laboratories and the IDM industry. The natural high-resolution capability of the block copolymer (sub-10nm) may meet the requirements of future technology nodes. Significant work in this area is underway at R&D consortia such as imec, IBM Research in Albany, N.Y., and Leti, as well as directly in the fab[2,3]. For example, Leti and its partners put in place a full infrastructure to qualify the new material developed by the chemical company Arkema (FIGURE 2). A full 300mm line is operational at Leti using a Tokyo Electron track and a customized SCREEN DUO track able to handle the latest process possibilities. This type of infrastructure is required to validate in fab-like conditions the new materials (PS-PMMA and high chi platforms) and their associated integration flows. Those operating conditions give industry the capability to quickly evaluate the full process-flow performances with all the required classic statistical data for final validation.

Litho Fig 2

Focusing on defectivity Intel showed convincing data at 1def/cm2 on line-and-space structures, confirming the potential of DSA to reach the ITRS target and therefore to be used for manufacturing in the near future (FIGURE 3). As well, Leti results on grapho-epitaxy process are also very encouraging with zero visual-defect process flow for contact/via application measured with low statistical level[4]. Those results are the first positive key trends in the DSA technology. Evaluating the compatibility of DSA with semiconductor process flows is the next important step. The control of the iso-dense configuration focused a lot of attention on the grapho-epitaxy process, in which block copolymer film-filling uniformity is affected by the topography effects of the guide patterns. Leti developed and patented a flow allowing a proper control of CD and CDU in all density configurations. (FIGURE 4) This solution preserves the interest of DSA as it is integrated in the process flow itself and because it does not imply a need for any additional design-rule restriction[4].

Litho Fig 3

Nevertheless, some hurdles remain to be overcome before its final adoption. The control of the surface affinity is one key aspect. It can greatly affect the final defectivity level and impact the complexity of the integration flow (FIGURE 5). Any non-uniform control of the bottom residual polymer thickness in the bottom of the guide cavity may lead to post-etch opening issues and final circuit-yield drop. Moreover, to be fully adopted, DSA technology also must be aligned with the compatible design rule manuals. Insertion in the DRM is essential and it implies adding new specific constraints due to the nature of the block copolymer and to the lithography guide realization. All these R&D efforts must be pushed to value the advantages of DSA technology: the natural high resolution of this solution and its cost effectiveness from reducing multi-exposure strategy. In addition to ensuring DSA’s ability to extend 193nm immersion lithography,it also supports the use of the EUV 0.33NA tool for the development of 7nm nodes and below.

Litho Fig 4

Massively parallel electron-beam writing

Despite recurrent delays in new developments, parallel electron-beam lithography remains an attractive alternative option. The massively parallel writing solutions developed by MAPPER Lithography and IMS Nanofab-rication for wafer and mask writing, respectively, offer good compromises: a significant alliance of resolution and advantageous manufacturing costs. But this technology also benefits from additional advantages, such as writing flexibility and a significant throughput improvement due to the parallel exposure concept that can boost the throughput in the future up to 100 wafers per hour in a cluster-tool configuration. First pre-industrial units are today installed in pilot-line environments, foreshadowing their introduction into production lines in coming years.

MAPPER and Leti’s collaboration is focused on introducing this technology for direct-write application. This joint program started in 2009 around the MAPPER’s pre-alpha tool that validated the key concept of the MAPPER technology in terms of parallel writing and resolution capabilities (FIGURE 6). The partnership entered in a new phase in 2014 with the installation of the first FLX-1200 pre-production platform, (FIGURE 7), operating 1,300 beam lines for a targeted throughput of 1 wph and then scalable to 10 wph by increasing the beam line count up to 13,000.

Litho Fig 5 Litho Fig 6

This FLX-1200, which is being ramped up now, already has shown imaging performances that match its specifications. Full 300mm wafers can be printed in one hour with 32nm half-pitch resolution (FIGURE 8). In the IMAGINE program, Leti and its partners are also working to validate a complete turn-key integrated solution allowing fast and secure wafer processing from design to silicon. Such infrastructure developments around data treatment, materials, process, etch and metrology will be required to speed-up the insertion of the MAPPER technology into future production lines.

Litho Fig 7

Leti and MAPPER will demonstrate the operational capability of the FLX-1200 in its final configuration, including mix-and-match alignment performances. The achievement of this key demonstration milestone is essential to launching this technology. Then, after final ramp-up, the MAPPER platform is expected to be aligned in terms of specifications with 14nm technology (32nm hp). A wide range of potential applications based on its mask-less concept and throughput potential already have been clearly identified: CMOS prototyping and low-volume production, complementary lithography concept for high-end patterning[6], new industry segments (photonics, low-cost circuit functionalization, large field exposure, etc.).

Nano-imprint lithography

Nano-imprint lithography (NIL) stands out from the other conventional lithography processes (photo-lithography, electronic lithography, EUV lithography) because of the fundamental mechanism of creating the final structures. In the case of nano-imprint, the flow of the resist directly shapes the pattern through the stamp cavities, eliminating the need for chemical contrast, as is the case for optical lithography resists. In recent decades, significant efforts have been made to extend the distance between the photomask and the resist-coated wafer to reduce defectivity and enhance resolution. Therefore, for many scientists, NIL technology appeared to be a UFO, since the process is based on the intimate contact between the working stamp and the resist to be embossed.

In the past 20 years, significant progress has been made to make the technology more mature and ready for high-volume manufacturing. Among the several existing NIL technology alternatives, the UV-based imprint, using transparent stamp, is today the standard one. Two well-established options are now available on the market: the full-wafer imprint (the size of the stamp corresponds to the size of the wafer to be printed) and the step-and-flash imprint in which a small stamp (i.e. die size) is stepped, as in optical lithography across the wafer to be processed (FIGURE 9).

Litho Fig 8

If the step-and-flash NIL technology is better suited to address the semiconductor markets (NAND flash memory, DRAM and logic) with its high level-alignment capability and its good control of defectivity density[7], the full-wafer NIL option could quickly become the reference manufacturing option for the emerging and growing markets such as LED and photonics-based devices (FIGURE 10).

Litho Fig 9

However, this wafer-scale imprint solution still lacks quantitative data regarding its technology assessment for high-volume manufacturing. Commercial equipment[8] and resists, the cornerstones of this technology, are already available. But some links in the industrial supply chain (design rules, master manufacturing and repair, in-line defectivity and metrology controls, fully integrated process flows) still must be established and qualified to make this technology more mature.

To accelerate adoption of this technology, Leti and EV Group launched in June 2015 a new collaborative industrial program called INSPIRE, aimed at demonstrating the benefits of this full-wafer NIL technology and spreading its use for applications beyond the traditional semiconductor industry. Much more than a classic industrial partnership, the program is designed to support development of new applications from the feasibility-study stage up to the first manufacturing steps, including the prototyping phase in Leti’s clean room. INSPIRE is also designed to demonstrate the technology’s cost-of-ownership benefits for a wide range of application domains. The final objective of this program is to facilitate the transfer of the developed integrated process solutions to industrial partners. The steps should significantly lower the entry barrier for NIL technology and speed up its use in production lines.

Conclusion

The availability of patterning alternatives in the lithography landscape represents a big opportunity to properly address the coming needs generated by the IoT. Besides conventional optical lithography, they offer industry new and/or complementary advantages: innovation capability and opportunities to better manage cost of ownership. But not only that! The high-resolution potential, the ability to facilitate design-innovation validation, and the complementarity of these alternatives with other patterning solutions also highlight their strengths. The step now is to finalize the evaluation of these technologies with respect to industry standards and establish them as real and credible lithography alternatives.

References

1. A. Schafgans et al, Proc SPIE, Extreme Ultraviolet Lithography VI, Vol. 9422, 2015
2. S. Sayan et al, Proc. SPIE, Advances in Patterning Materials and Processes XXXII, Vol. 9425, 2015
3. H. Tsai et al, ACS nano, vol 8 (5), pp. 5227-5232, 2014
4. R. Tiron et al, Alternative Lithographic Technologies II, Vol. 9423, 2015

November 2, 2015 — Tsinghua Unigroup Ltd., a Chinese government-owned chipmaker will make a $600 million investment in Powertech Technology of Taiwan, according to multiple reports. Powertech Technology, which specializes in chip packaging and testing, will hand over 25% of the company in exchange, after new shares are issued.

According to the Wall Street Journal, Powertech will use the funds to “help it expand its assembly capacity in Taiwan, develop advanced production processes and recruit talent. It would also become Tsinghua Unigroup’s major chip assembly and testing partner.”

Tsinghua is the largest chip design company in China, and earlier this year attempted to acquire Micron Technology with a $23 billion bid. That bid ultimately failed, but it hasn’t stopped Tsinghua from investing in other US companies in the industry, including Western Digital ($3.78 billion for 15%) and Hewlett-Packard’s data-networking business (51%, $2.3 billion).

This continues the unprecedented consolidation that has come to the semiconductor industry in 2015. A trend that has shown no signs of slowing as we enter 2016.

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To help readers follow this constantly changing situation, Solid State Technology is keeping a running scorecard of all the significant transactions in the semiconductor market here: Historic era of consolidation for chipmakers.

 

 

One thing seems clear about the semiconductor market: consolidation is showing no signs of slowing down.

On the heels of two additional acquisitions in the space around semiconductors — LAM Research acquiring KLA-Tencor and Western Digital buying SanDisk — rumors have abounded this week that there is more to come.

First, Bloomberg reported that Texas Instruments, the world’s largest maker of analog chips, is in talks to buy Maxim Integrated. TI is said to have competition for Maxim from a competitor in the analog chip space, Analog Devices.

According to the Bloomberg report, Maxim may be holding out for a hefty premium, if it does, in fact, sell.

“When asked on an Oct. 22 conference call about a possible takeover by a larger company such as Texas Instruments, Maxim Chief Financial Officer Bruce Kiddoo said the company is big enough and profitable enough to survive on its own,” Bloomberg reported. “Maxim also has the resources to do its own acquisitions, he said.”

For Texas Instruments’ part, CFO Kevin March weighed in on potential acquisitions on October 21. Bloomberg quotes him as saying: “If we were to look at an acquisition, it would probably be a company that’s going to be broad in catalog, have a diverse customer base, have a large percentage of its revenue coming from industrial and automotive, probably have a very talented R&D team. So we really do focus on the numbers that that acquisition might lead us to.”

Following the Bloomberg story, the Chicago Tribune issued a report saying STMicroelectronics is considering a bid for Fairchild Semiconductor. STMicro is Europe’s biggest chipmaker, and would be looking to “increase growth and shore up its digital products business” with the purchase, according to the report.

For its part, Fairchild, which is one of the oldest chipmakers in the US, has hired Goldman Sachs to help it find a buyer. In recent months the company has conducted talks with ON Semicondor and Infineon Technologies about being purchased, according to the Tribune.

It is still uncertain whether anything will come of either report, but it seems clear that the merger madness in the semiconductor industry is far from over.

To help readers follow this constantly changing situation, Solid State Technology is keeping a running scorecard of all the significant transactions in the semiconductor market here: Historic era of consolidation for chipmakers.

 

Growing Conference Business at Extension Media Brings Experienced Events Producer Onboard

SAN FRANCISCO, October 28, 2015 – Extension Media announced today the addition of Sally L. Bixby as Senior Events Director for Extension Media’s fast-growing conference division. She will be based in the downtown Portland, Oregon office where Extension Media has editorial staff.

Ms. Bixby is an accomplished corporate events producer with nearly 16 years of in-depth experience in operations and marketing, holding senior staff positions in multiple events projects. To date, she has managed more than 450 business conferences in North America alone and produced several internationally as well. She brings to the role a significant track record of increasing event attendance, managing large- and small-scale budgets and driving lead generation for companies such as: AMD, Avnet, Curtiss-Wright, Intel, Kontron, MathWorks and more. Throughout her career, Ms. Bixby has cultivated relationships in the embedded systems, semiconductor and medical electronics industries, as well as academia and several professional organizations, building mutually beneficial and long-term business relationships.

“We are thrilled that Sally is leading the conference operations management team and will also be focusing her energy on growing the conference and exhibition side of our business, adding several events aimed at the embedded and growing IoT market segments as well as the semiconductor manufacturing and design market,” said Vince Ridley, president and founder of Extension Media. “Her professionalism and passion for delivering successful events will benefit both Extension Media and our clients. Sally’s attention to exceeding expected goals make her an ideal fit.”

“I look forward to expanding the conference business at Extension Media, connecting knowledgeable, responsive leaders and influencers,” said Ms. Bixby. “Recent experience creating a successful China-U.S. IoT Summit for a Fortune 100 company – that resulted in 120% of the attendee goal and a 10.5% budget savings – has me looking forward to helping our clients achieve impressive results.”

Prior to joining Extension Media, Ms. Bixby was an independent senior events producer running her own company, EventBelle Productions. In 2014 and 2015, she managed all operations, budgets and the VIP program for The ConFab, the preeminent semiconductor manufacturing conference and networking event for leaders and decision-makers addressing the economics of semiconductor manufacturing.

About Extension Media
Extension Media is a privately held company operating more than 50 B2B magazines, engineers’ guides, email newsletters, web sites and conferences that focus on high-tech industry platforms and emerging technologies such as: chip design, semiconductor and electronics manufacturing, embedded systems, software, architectures and industry standards.

Extension Media produces industry leading events including The ConFab, the Internet of Things Developers Conference (IoT DevCon) and the Multicore Developers Conference (Multicore DevCon), and publishes Embedded Systems Engineering, EECatalog.com, Embedded Intel® Solutions, EmbeddedIntel.com, Chip Design, ChipDesignMag.com, Solid State Technology, Solid-State.com and SemiMD.com.

Extension Media Contacts
Vince Ridley
[email protected]
415-255-0390
Sally L. Bixby
[email protected]
503-705-8651

A report that resulted from a workshop funded by Semiconductor Research Corporation (SRC) and National Science Foundation (NSF) outlines key factors limiting progress in computing—particularly related to energy consumption—and novel device and architecture research that can overcome these barriers. A summary of the report’s findings can be found at the end of this article; the full report can be accessed here.

The findings and recommendations in the report are in alignment with the nanotechnology-inspired Grand Challenge for Future Computing announced on October 20 by the White House Office of Science and Technology Policy. The Grand Challenge calls for new approaches to computing that will operate with the efficiency of the human brain. It also aligns with the National Strategic Computing Initiative (NSCI) announced by an Executive Order signed by the President on July 29.

Energy efficiency is vital to improving performance at all levels. This includes from devices and transistors to large IT systems, as well from small sensors at the edge of the Internet of Things (IoT) to large data centers in cloud and supercomputing systems.

“Fundamental research on hardware performance, complex system architectures, and new memory/storage technologies can help to discover new ways to achieve energy-efficient computing,” said Jim Kurose, the Assistant Director of the National Science Foundation (NSF) for Computer and Information Science and Engineering (CISE). “Partnerships with industry, including SRC and its member companies, are an important way to speed the adoption of these research findings.”

Performance improvements today are limited by energy inefficiencies that result in overheating and thermal management issues. The electronic circuits in computer chips still operate far from any fundamental limits to energy efficiency, and much of the energy used by today’s computers is expended moving data between memory and the central processor.

At the same time as increases in performance slow, the amount of data being produced is exploding. By 2020, an estimated 44 zettabytes of data (1 zettabyte equals 1 trillion gigabytes) will be created on an annual basis.

“New devices, and new architectures based on those devices, could take computing far beyond the limits of today’s technology. The benefits to society would be enormous,” said Tom Theis, Nanoelectronics Research Initiative (NRI) Executive Director at SRC, the world’s leading university-research consortium for semiconductor technologies.

Inspired by the neural architecture of a macaque brain, this neon swirl is the wiring diagram for a new kind of computer that, by some definitions, may soon be able to think. (Credit: Emmett McQuinn, IBM Research - Almaden)

Inspired by the neural architecture of a macaque brain, this neon swirl is the wiring diagram for a new kind of computer that, by some definitions, may soon be able to think. (Credit: Emmett McQuinn, IBM Research – Almaden)

In order to realize these benefits, a new paradigm for computing is necessary. A workshop held April 14-15, 2015 in Arlington, Va., and funded by SRC and NSF convened experts from industry, academia and government to identify key factors limiting progress and promising new concepts that should be explored. The report being announced today resulted from the workshop discussions and provides a guide to future basic research investments in energy-efficient computing.

The report builds upon an earlier report funded by the Semiconductor Industry Association, SRC and NSF on Rebooting the IT Revolution.

To achieve the Nanotechnology Grand Challenge and the goals of the NSCI, multi-disciplinary fundamental research on materials, devices and architecture is needed. NSF and SRC, both individually and together, have a long history of supporting long-term research in these areas to address such fundamental, high-impact science and engineering challenges.

Report Findings

Broad Conclusions

Research teams should address interdisciplinary research issues essential to the demonstration of new device concepts and associated architectures. Any new device is likely to have characteristics very different from established devices. The interplay between device characteristics and optimum circuit architectures therefore means that circuit and higher level architectures must be co-optimized with any new device. Devices combining digital and analog functions or the functions of logic and memory may lend themselves particularly well to unconventional information processing architectures. For maximum impact, research should focus on devices and architectures which can enable a broad range of useful functions, rather than being dedicated to one function or a few particular functions.

Prospects for New Devices

Many promising research paths remain relatively unexplored. For example, the gating of phase transitions is a potential route to “steep slope” devices that operate at very low voltage. Relevant phase transitions might include metal-insulator transitions, formation of excitonic or other electronic condensates, and various transitions involving structural degrees of freedom. Other promising mechanisms for low-power switching may involve transduction. Magnetoelectric devices, in which an external voltage state is transduced to an internal magnetic state, exemplify the concept. However, transduction need not be limited to magnetoelectric systems.

In addition to energy efficiency, switching speed is an important criterion in choice of materials and device concepts. For example, most nanomagnetic devices switch by magnetic precession, a process which is rather slow in the ferromagnetic systems explored to date. Magnetic precession switching in antiferromagnetic or ferrimagnetic materials could be one or more orders of magnitude faster. Other novel physical systems could be still faster. For example, electronic collective states could, in principle, be switched on sub-picosecond time scales.

More generally, devices based on computational state variables beyond magnetism and charge (or voltage) could open many new possibilities.

Another relatively unexplored path to improved energy efficiency is the implementation of adiabatically switched devices in energy-conserving circuits. In such circuits, the phase of an oscillation or propagating wave may represent digital state; devices and interconnections must together constitute circuits that are non-dissipative. Nanophotonic, plasmonic, spin wave or other lightly damped oscillatory systems might be well-suited for such an approach. Researchers should strive to address the necessary components of a practical engineering solution, including mechanisms for correction of unavoidable phase and amplitude errors.

Networks of coupled non-linear oscillators have been explored for non-Boolean computation in applications such as pattern recognition. Potential technological approaches include nanoelectromechanical, nanophotonic, and nanomagnetic oscillators. Researchers should strive for generality of function and should address the necessary components of a practical engineering solution, including devices, circuits, and architectures that allow reliable operation in the presence of device variability and environmental fluctuations.

Prospects for New Architectures

While appropriate circuits and higher level architectures should be explored and co-developed along with any new device concept, certain novel device concepts may demand greater emphasis on higher-level architecture. For example, hysteretic devices, combining the functions of non-volatile logic and memory, might enhance the performance of established architectures (power gating in microprocessors, reconfiguration of logic in field programmable gate arrays), but perhaps more important, they might play an enabling role in novel architectures (compute in memory, weighting of connections in neuromorphic systems, and more). As a second example, there has been great progress in recent years in the miniaturization and energy efficiency of linear and non-linear photonic devices and compact light emitters. It is possible that these advances will have their greatest impact, not in the ongoing replacement of metal wires by optical connections, but rather in enabling new architectures for computing. Computation “in the network” is one possible direction. In general, device characteristics and architecture appear to be highly entwined in oscillatory or energy-conserving systems. Key device characteristics may be inseparable from the coupling (connections) between devices. For non-Boolean computation, optimum architectures and the range of useful algorithms will depend on these characteristics.

In addition to the examples above, many other areas of architectural research might leverage emerging device concepts to obtain order of magnitude improvements in the energy efficiency of computing. Research topics might include architectures for heterogeneous systems, architectures that minimize data movement, neuromorphic architectures, and new approaches to Stochastic Computing, Approximate Computing, Cognitive Computing and more.

Slideshow: 2015 IEDM Preview


October 20, 2015
The 2015 IEDM Conference will be held in Washington DC.

The 2015 IEDM will be held in Washington DC.

This year marks the 61st annual IEEE International Electron Devices Meeting (IEDM). It is arguably the world’s pre-eminent forum for reporting technological breakthroughs in semiconductor and electronic device technology, design, manufacturing, physics, and modeling. The conference focuses not only on devices in silicon, compound and organic semiconductors, but also in emerging material systems.

As usual, Solid State Technology will be reporting insights from bloggers and industry partners during the conference. This slideshow provides an advance look at some of the most newsworthy topics and papers that will be presented at this year’s meeting, which will be held at the Washington, D.C. Hilton from December 7-9, 2015.

Click here to start the slideshow

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