Tag Archives: Small Times Magazine

Click to Enlargeby Neha Choksi, contributing editor

June 30, 2010 – Proteomics is an important field for the pursuit of drug discovery, vaccine development, and drug manufacturing. However, prevalent methods require fluorescent labeling and 2D evaluation through electrophoresis or mass spectrometry. Hus Tigli, CEO of Silicon Kinetics, shared an alternative approach that leverages nanotechnology, at the San Francisco Bay Area IEEE Nanotechnology Sixth Annual Symposium: "Nanotechnology: State of the art and applications" (May 18-19 in Santa Clara, CA).

The company’s SKi biosensor consists of nanoporous silicon chips embedded in probes or flow cells, technology developed over approximately three years. By starting with n-type silicon and employing wet etch techniques, the resulting sensor area can achieve 70%-90% porosity with an average pore diameter of 80nm. This design was chosen to allow molecules to enter and exit as needed. Thickness, diameter, and etch uniformity are carefully controlled through statistical process control methods. The nanopores are important because they provide a large surface area for binding the first molecule of interest to create the desired surface chemistry. This functionalized sensor can then be used to detect the biomolecule of interest present in the solution that is being analyzed.

These biosensors are used in the company’s SKi Pro nanoporous optical interferometry (NPOI) platform. Depending on what molecule attaches to the first molecule of interest, the effective refractive index changes in the nanopore, leading to an optical path difference. Utilizing the platform’s interferogram, software is utilized to study the resultant pattern changes which form through constructive and destructive interference. The rate of change over time can be studied to extract information regarding the amount of molecule of interest that has bound to the biosensor.

Click to Enlarge

Because the nanopores are at a depth of 1.5-2nm into the wafer, the light used in the system passes through multiple layers of biomaterial, yielding a high throughput 3D approach. This "label free" method does not require sample preparation and does not interfere with the structure of the molecule of interest. The sensor is reusable 10-50×, and the company’s platform has automated cleaning using a solvent solution.

The company has taken the need for flexibility into account with the design of their system. "In addition to being highly sensitive, the NanoPore Optical Interferometry (NPOI) platform uniquely allows dual format experiments on the same instrument, either high-throughput ranking of interactions as well as detailed kinetic analysis," according to Tigli. Either way, the company aims to have an impact in the fields of drug discovery and disease research.

Neha K. Choksi is an independent consultant based in Mountain View, CA. She has worked for a variety of MEMS companies including as director of product engineering at Silicon Microstructures and as a consultant focusing on commercialization and high-volume production of MEMS devices. E-mail: Choksi [at] gmail.

June 25, 2010 – A three-day event put on by the Center for High-Rate Nanomanufacturing (CHN), one of four US nanomanufacturing centers and a collaboration of regional institutes (U. of Massachusetts/Lowell, Northeastern U., and the U. of New Hampshire), offered insights and updates on all things nano, from self-assembly and measurement techniques and requirements to applications in batteries, photovoltaics, and sensors.

Thomas Russell of UMass/Amherst discussed bottom-up self-assembling block copolymers, with the highly directional field & mobility of solvent, to create "perfect" hexagonally packed arrays (3×3 cm2) area, and areal densities of -10.5 TB/in2 — the equivalent of ~25 DVDs, he said. One problem: "the industry can’t write to it, and can’t read to it!" He suggested the data storage industry will have to push further into SSDs, though this will mean having to "push the limits" of etch and evaporation processes — e.g., etching along a crystal’s surface and controlled directionally. His team has not yet made such a high-density device, he noted.

JA Liddle from NIST looked at measurement challenges with the need to find a functional sweetspot of defectivity, high throughput, and tiny size. Measuring for "fundamental understanding" is too slow, expensive, and infrequent — but measuring for "process and quality control" is fast, cheap, and offers periodic/continuous results, both offline and in real time. He led this discussion into understanding more about self-assembly, which has limited control except for setting boundaries. Diblock copolymers can put small features close together, but measuring line-edge roughness with SEM looks "terrible," possibly because of damage caused by the technique itself. Resonant x-ray scattering, which can measure interfacial width/roughness to sub-0.5nm accuracy, he called "a lot more encouraging," and it can also be used for sidewall angles. For roll-to-roll diblock copolymers, techniques must be specific to the type of pattern being measured, and models must be developed for data extraction. A laser gauge sensor, he pointed out, looks a lot like a spinning HDD — so it’s feasible, he said. To follow the behavior of a single molecule, where Brownian motion limits dwell times, Liddle suggested tracking fluorescence correlation spectroscopy (FCS).

One challenge in measurements: morphological diversity in CNTs (single-walled, multiwalled, double-walled), which depend on finding the right combination of catalyst, temperature, precursor, pressure, etc. For now, measuring both process control and quality control (end-of-line) is "a really good problem statement," he said. Invoking the rule of "maximum laziness," he suggested defect location could be as simple as thermal examination (e.g., to find a short between two films, as in a PV application), but for a single pixel out of alignment, "near-field is the only chance."

Continuing on the CNT theme, David Arthur from CNT supplier Southwest Nanotechnologies (SWeNT, one of the event’s sponsors) noted the price/demand differences between the different types of CNTs. Multiwalled nanotubes are available in hundreds of tons/year, from lots of suppliers, at prices as little as $0.05/$0.50/g, for more general bulk applications. Single-wall nanotubes, meanwhile, are relegated to mainly niche coating applications due to their low volumes/availability and related high prices ($50-2000/g). But there’s an emerging opportunity in between, he said, that SWeNT wants to tap: specialty multiwall nanotubes (~3-6 walls), with better properties than normal MWNTs (e.g. easier to disperse, high ~10,000:1 aspect ratios), priced somewhat cheaply )$0.50-$50/g). SWeNT has ramped its output of CNTs to about 1kg/day, and plans to scale to 1 ton/day by 2012, while reducing costs by 10x. (He noted that the company’s products well exceed — though not with precise determination — industry standards (e.g., 90% semiconducting and 40% type [6,5]). Targeted applications include a CNT ink printable using standard manufacturing equipment, and printed LED lighting. Another key area is in new cathode materials for Li-ion batteries that meet cycle/life, low-weight, and cost needs. Initial data Arthur showed from RIT suggests comparable metrics to conventional cathode materials — same profile discharge, but better across cycling. Arthur also described fiber-reinforced fabrics (dipped in a CNT solution) for use as structural sensors, taking advantage of a correlation between measurable mechanical strain and conductivity. Such fabrics are already installed in two bridges in Alabama, he noted.

Asked about the biodegradability of CNTs — EHS is a critical concern with nanomaterials, and took up an entire day’s worth of presentations at the nano event’s first day — Arthur acknowledged that they are "likely to have a pretty high persistence in the environment," and the best approach may be to rely on encapsulation to "minimize their release."

Returning to self-assembly themes, Joey Mead of UMass/Lowell explained directed self-assembly with polymers, where current work emphasizes determining the effectiveness of the template and polymer blends. These blends can be assembled in 30sec with no anneal and in uniform patterns (e.g., 90o, T-junction, circle and square arrays). Patterning multiple length scales is possible, with 100-300nm spacing on a single template — her team wrote "CHN" using polymers (the name of the joint nano center). Key is knowing the interdependence and thus sweetspots of three factors: domain size, spin speed, and concentration. As an example, domain size and pattern pitch should be within 10% of each other. Mead also discussed work in transferring CNTs from a surface (e.g. PDMS stamp) — the opposite of what the previous speaker from SWeNT would want! — using a type of thermoforming similar to making yogurt cups: heat a polymer sheet, put the template into the base of the mold, and push it up to transfer. This works for conducting polymers as well as CNTs, she noted.

Tom Van Vechten, representing NanoComp (another event sponsor), talked about CNTs’ synthesis and application in thermoelectrics, where change in temperature is utilized to create electricity. (In cars, 44% of fuel is exhausted through the radiator, equivalent to ~10s of kW, he noted.) He discussed putting n-type and p-type semiconductors in series, and the company’s creation of a flexible CNT "felt" as an alternative generator material vs. typically Bi2Te3 — but as comparative numbers showed, there’s a very long way to go. "We have ideas about how to continue" the progress of CNT felt material, ultimately targeting $1/W in five to seven years. Possible application would be taped to the back of a solar collector to increase overall system output.

Morphology was the main topic of discussion for Konarka’s Eitan Zeira, as the company works to increase PV efficiency with a new polymer structure, and devising morphology is the main challenge for spontaneous phase separation and making polymers that stack up quickly. Efforts with PCBM only show up to 6% efficiency, he noted.

Another take on nano in PV was offered by Loucass Tsakalakos of GE Global Research Center, who talked about the group’s work on nanowire solar cells, which promise "excellent optical properties" (better than planar/solid thin film), angular dependence, and can be doped n- or p-type. GE developed the nanowire process flow from scratch, he noted. Asked how to apply back contacts to such a nanowire array, e.g. on a low-cost metal foil, he explained that there "a lot of considerations," e.g. developing different barriers, but they can grow the NTs on a 4-in. stainless steel metal foil. Another issue is depositing a uniform coating, i.e. with PECFD for SiO2. More work is needed to model, for example, electric fields, the effect of gas transport on the wires, etc. A prototype a-Si device initially showed just 1.2% efficiency in first tests, but he hinted that new results forthcoming later this year will show ~11%, using compound semiconductor devices — comparable to organic & inorganic PV materials.

by Karey Holland, Techcet Group

June 21, 2010 – The Greener Nanotech 2010 conference (June 16-18, U. of Oregon, Portland, OR) focused on both the importance of verifying that any nanomaterials products are safe for the environment and health, as well as importance of continuing to move beneficial side of nanomaterials forward. Oregon has been involved in green chemistry initiatives for over 15 years, and thus is applying these basic principles to drive for green nanotech. In the last 10 years, nanotechnologies have matured from initial "dot-com" like exuberance, where concept was enough to start a business, to a more mature development phase with significant focus on reproducible manufacturing, quality control, material stability, and environmental/health/safety (EHS).Click to Enlarge

What follows are overview key messages and information from the conference; presentations are available to anyone interested (please feel free to contact me or the authors).

Robert "Skip" Rung, president and executive director of ONAMI (Oregon Nanoscience and Microtechnologies Institute), gave an excellent presentation on the benefits of nanotechnologies to the Oregon and US economies. While anything 1-100nm in at least one dimension is lumped into the "nanotechnologies industry," he reminded that it is more relevant to consider each nanomaterial within its application industry — e.g., cosmetic, biomolecular, biomedical, semiconductor, micromachine, solar, battery, military, water purification, and most high-tech industries. (For example, 75% of all leading-edge high-tech and biomedical products include nanomaterials.) Nanomaterials can allow us to reduce the amount of materials required (read: cost), and have access to interactions not available to larger particles. In 2007, the US invested $1.8B in nanotechnologies, and $13.7B was invested worldwide. Russia has funded the Russian Corporation for Nanotechnology to the tune of $5B, with the majority of this funding being used to buy existing nanotech companies. Oregon itself has a large number of companies involved in nanomaterials: Intel, HP, Life Technologies (Invitrogen) and solar companies Solexant , REC, SolarWorld, Spectrawatt, etc. He reaffirmed that while Oregon benefits from the economic and business opportunities afforded by nanotechnologies, it is also committed to doing this without harming the environment or health.

While there is much excitement about the numerous potential improved products that use nanomaterials, there is a growing concern about the nanotech risks: airborne nanoparticles could affect the cells in our lungs, production of materials can product hazardous waste, etc. Correct choices must be made while in the materials development phase, but an impediment to development is the lack of appropriate government regulation of nanomaterial — which instead of hastening nanomaterial development has instead hampered development. Jim Hutchison, conference chairman and U of OR professor of chemistry, and member of the Safer Nanomaterials and Nanomanufacturing Initiative, reviewed 15 principles of green technology and how they apply to nanotechnology. Key to greener nanotech is reduction/elimination of hazardous materials in all aspects of the nanomaterials, from the starting materials, through the fabrication and application, to disposal.

Other speakers echoed these commitments to develop nanotechnology with low risk to ESH as a starting goal. Silver nanoparticles are known to be antimicrobial agents — e.g., Dune Sciences’ LinkedON silver nanoparticle product that is adhered to socks and other fabrics. Ag disrupts cell membranes and prevents bacterial reproduction. Ag is now being regulated as a biocide/pesticide.

Richard Denison from the Environmental Defense Fund noted that there have been beneficial materials in the past that were touted as non-hazardous, that years later were found to have a "dark side" (think: asbestos). EDF aims to determine hazards before the materials are throughout our environment, and wants to insure safety in the development phase. As an example, Ag nanoparticles are excellent antibacterial agents, but if those nanoparticles enter sewage treatment centers via clothes washing machines they could kill beneficial bacteria. Clearly there is not much science on the health and environmental risks of nanomaterials or their manufacture. Policies have even changed with administrations — in 2007 the EPA required no new reviews for nano forms of existing materials, but since 2009, nano forms of existing materials for significant new uses will be subject to EPA notification/review (this is not retroactive to any nanoproduct before 2009, however).

NIST discussed only nanomaterials where at least two dimensions are 1-100nm. Of all current nanomaterial products, Ag nanoparticles make up a significant majority of total, used as antimicrobials in numerous applications from catheters to socks and washing machines. Carbon, titanium, and zinc are also important — titanium oxide and zinc oxide nanoparticles are used is some sunscreen and cosmetic products, for example. The current NIST standards have been made with gold particles (AFM, SEM, TEM, and suspensions for light diffraction), as stable silver particles are hard to produce and keep in a stable composition. One NIST presentation pointed out that nanoparticles actively interact with their environments.

Despite wide agreement that there are perceived and real risks, there are few studies on nanoparticle effect on health and safety — so today perceived risks dominate, often resulting in the public fearing (the unknown) nanoparticles. To make this more confusing, some of the studies may not have validated the contamination vs. the major component in the nanoparticle, further confusing the issue as to where the risk originates. One example is a zero valent iron nanoparticle suspension in development as an anti-cancer agent, which has been pulled from development until risks can be properly evaluated. NIST has been developing standards for particle which is required to start risk assessments of nanomaterials: (1) size, shape, volume; (2) chemical composition and contaminants; and (3) surface chemistry and charge.

John Busbee from the Air Force Research Lab said that the AFRL is now interested only those nanomaterials that have shown technical viability and manufacturing feasibility demonstrated — no longer are concept particles being pursued due to the poor track record of these materials becoming reproducible realities. The first nanomaterials in use by AFRL are those that are replacing traditional materials (e.g., C nanoparticles replacing C powder in solder), but they are now moving to novel applications of these materials.

Scott McNeil of the National Cancer Institute reviewed several nanomaterials that are being evaluated, or have in fact been approved by the FDA for cancer treatments. These particles have numerous substituents, including targeting molecules, cancer treatment drugs, and a PEG shield. He showed that certain particle attributes make it more effective in treating cancer without being harmful to the body. PEG keeps the particle hydrophilic, key to protecting it from the body’s immune system. Particle size will determine if it is accumulated in the spleen or liver (particles 30-220nm are best). When properly formulated, an anti-cancer drug attached to a nanoparticle will be effective at 1/10th the dose of the same drug not attached to the nanoparticle. Studies have also shown that an anti-cancer drug attached to a nanoparticle is safe at a dose that is 3× the lethal dose of non-particle attached drug. Thus, although NCI wants to insure that all nanomaterials pose no ESH issues, they also want to collaborate with the FDA and help companies bring new drugs to market that can treat cancer so effectively.

Travis Earles of the US Office of Science and Technology Policy shared the current administration’s views and priorities with respect to nanotechnology. The administration wants to encourage innovation and acknowledges the need to minimize risk. He discussed the National Nanotech Initiative that is funding basic science that leads to innovation that can lead to start-ups which hopefully becomes manufacturing (in the US) — and that all leads to new economic growth.

Bryan Monroe from Life Technologies (Invirogen) reviewed the biomed pharma challenges and translated these into lessons-learned for nanotechnology companies. Efforts to protect, he said, can cut off from public science — i.e., IP paralysis.

The forum held two sessions of "Rapid Fire" presentations, 7min each with questions afterwards, where researchers could bring ideas to the forum, generate interest, input, and new ideas:

  • Prof. Erik Richman discussed using zebrafish embryos with nanoparticles, and the difficulty in determining exactly where inside the embryo the nanoparticles reside.
  • Mike Jespersen (AFRL) discussed the interesting characteristics of nanoparticles certain surface groups (e.g. PEG) that cause the material to act as a liquid.
  • Donald Baer (Pacific Northwest National Laboratory) showed data on Fe metal core particles with oxide shells. Particles varied too much from batch in manufacturing; and the changed properties with time (low shelf life), some of this was due to contaminants that were not originally well controlled.
  • Prof. John Conley talked about "greener" nanowires. Currently nanowires are grown and then moved into place, leaving the majority as waste. His approach selectively grows wires only where you need them, ZnO or Au seed, pattern & grown. Unfortunately, this requires carbonizing resist, which requires 800-900°C.
  • Grad student Matt Beekman discussed a method of using aqueous solutions to make spin-on thin films of HfOx and similar materials for ICs.
  • Paul Schuele discussed his challenges at Sony in nanomanufacturing for large-scale electronics (think large flat-panel TVs). The customers and people that manufacture the electronics don’t care about "cool"; manufacturing wants lower cost, higher performance, well characterized, and low yield risk. Learning curves are steep to making enough (>83M) yielding devices on a 3’×4′ substrate.

 

Karey Holland, Ph.D., managing partner at Techcet Group, has 25 years of experience in semiconductor technology, including: CMP equipment company SpeedFam-IPEC; IBM (where she contributed to interconnect technology development and manufacturing introduction of IBM’s 4Mb DRAM); Sematech’s deep-UV lithography Micrascan II project; and Motorola’s microprocessor and memory technology group. Contact: [email protected].

June 17, 2010 – Toshiba Corp. is revealing at this week’s VLSI Symposium in Hawaii a new silicon nanowire transistor for system LSI for 16nm node and beyond.

The device achieves a 1mA/μm on-current, a record for a Si nanowire transistor, thanks to reduced parasitic resistance and 75% better on-current levels, the company says.

As planar transistor architectures scale down in size, current leakage between the source and drain at off-stage ("off-leakage") is a critical problem; to answer this, transistors with 3D architectures are being investigated. Among these options are Si nanowires, which can suppress off-leakage and achieve further short-channel operation because their thin wire-shaped silicon channel is controlled by the surrounding gate — but parasitic resistance (especially under the gate sidewall) is still a problem.

Click to Enlarge
Figure 1: Structure of a silicon nanowire transistor. (Source: Toshiba)

To address this, Toshiba optimized gate fabrication and reduced the gate sidewall thickness from 30nm to 10nm. Epitaxial Si growth on the source/drain with such a thin gate sidewall improved on-current by 40% and realized low parasitic resistance. A further 25% increase in current performance was achieved by changing the direction of the Si nanowire channel from the <110> to <100> plane direction. The result: on-current level of 1mA/μm and off-current of 100nA/μm — a 75% increase in on-current, with no change in off-current condition.

Click to Enlarge
Figure 2: Comparison with the previous work. (Source: Toshiba)

Toshiba says it will continue to push development of this transistor, toward "establishing fundamental technologies for high-performance, low-power system LSIs." The work was partly supported by the New Energy and Industrial Technology Development Organization (NEDO).

June 14, 2010- – Researchers from Cornell and the Semiconductor Research Corporation (SRC) say they have devised a method for visualizing and identifying detailed structure of low-k insulating materials at a sub-nanometer scale.

Porous low-k materials have been replacing SiO2 as the insulator between copper wires to speed up electrical signals while also reducing power consumption — the ITRS requires k=2.1-2.5 for 36nm-28nm hp structures. Knowing the detailed structure and connectivity of the nanopores in such materials will be valuable to understanding impacts on mechanical strength, chemical stability, and reliability. Measurements using gas adsorption, X-ray reflectivity, small angle X-ray diffraction, neutron scattering, and positron annihilation all lack two key functions — spatial resolution, with which to explore process variations around individual devices where damage could occur; and no direct information about individual 3D pore shapes, connectivity, and variations when integrated into an actual device.

"Knowing how many of the molecule-sized voids in the carefully-engineered Swiss cheese survive in an actual device will greatly affect future designs of integrated circuits," explains David Muller, prof. of Applied and Engineering Physics and co-director of Cornell U.’s Kavli Institute for Nanoscale Science, in a statement. "The techniques we developed look deeply, as well as in and around the structures, to give a much clearer picture so complex processing and integration issues can be addressed."

Click to Enlarge
Credit: Huolin Xin, Muller Group, Cornell University

In joint work, published in the June 2 issue of Applied Physics Letters, Cornell and the Semiconductor Research Corp. (SRC) devised their new method: 3D reconstruction of a porous low-k (k=2.5) film, resolving pores down to 1nm, using annular darkfield scanning transmission electron tomography — an extension of 2D STEM techniques that leverages 3D imaging used in CT scans and MRIs to extract 3D images from 2D images taken at multiple angles, notes Scott List, SRC’s director of interconnect and packaging sciences. The result: quantitative measurements of pore morphologies and size distribution.

Some of their observations, as noted in the journal paper:

– Most large pores as elliptical; along with log-normal pore-size distribution, this suggests pore coalescence during material growth.
– Ellipsometric porosimetry indicates a high degree of interconnectivity between pores.
– Tomography showed little large-scale pore connectivity, indicating interconnections were no bigger than 1nm.
– Systematic errors in the tomographic and ellipsometric size distributions appear to be largely complementary.

"The techniques we developed look deeply, as well as in and around the structures, to give a much clearer picture so complex processing and integration issues can be addressed, noted Muller. For semiconductor manufacturers, added List, the near-atomic-resolution 3D imagery offers "new insights into scaling low-k materials for several additional technology nodes."

May 28, 2010 – Researchers at Rice U. say they have figured out how to carve up graphane sheets to create spaces of pure graphene with properties of semiconducting quantum dots, results that point to possible future work in nanoelectronics.

The subject material, graphane, is a sister to graphene but with hydrogen atoms attached to both sides of the matrix, making it an insulator and thus a target for research into manipulating its semiconducting properties. Removing islands of hydrogen from both sides of a 2D graphane sheet, they calculate, leaves a "well" of pure graphene that exhibits all the properties of a quantum dots — crystalline molecules with size-determinant bandgap and tunability, applicable in devices from chemical sensors to solar cells to nanoscale circuitry.

"This phase transformation (from graphene to graphane), accompanied by the change from metal to insulator, offers a novel palette for nanoengineering," states Boris Yakobson, research team leader and Rice professor of mechanical engineering and materials science and of chemistry.

When chunks of the hydrogen are removed, the area left behind is always hexagonal, with sharp interface between the graphane and graphene — which means each dot is highly contained, and very little charge leaks into the graphane host material. "You have an atom-like spectra embedded within a media, and then you can play with the band gap by changing the size of the dot," noted postdoc contributor Abhishek Singh. "You can essentially tune the optical properties."

Precise removal of the hydrogen atoms is still being determined, they admit, and more work is needed to make arrays of quantum dots in a sheet of graphane. Future use could be in optics, single-molecule sensing, and ultimately nano-transistors and semiconductor lasers. "We think the major conclusions in the paper are enough to excite experimentalists," added Singh.

Their work has been published in ACS Nano.

Click to Enlarge
Electron densities created from graphane-embedded quantum dot calculations. The isosurfaces depict electrons in the valance band that, in reality, would be confined within the quantum dot, and demonstrate that very little charge would leak from the hydrogen-defined boundaries of such a dot. (Source: Rice U.)

 

By Jerôme Baron, Yole Développement

May 24, 2010 – It’s not just 3D packaging technology where CMOS image sensors are driving IC technology these days. Ultrathin silicon that enables back-side illumination (BSI), and integrated wafer-level optics are bringing sharply improved performance, lower costs, and smaller size, driving CMOS image sensors into more and more markets — and these technologies may soon impact other IC manufacturing as well.

Thinning silicon wafers down to 5μm transparent films to let light through the back side is driving a 2× to 5× improvement in sensitivity for smaller pixel image sensors. Yole Développement sees CMOS sensors now moving quickly into higher performance applications, including high resolution digital SLR cameras and digital video recorders, as they come to match the performance of CCDs at lower cost. These thinning and annealing technologies may also open new possibilities for 3D stacking and integration of very thin layers of memory and logic devices in the future. Wafer-level optics are also starting to reduce camera module size and cost in even demanding handset applications, and could also bring similar improvements to projection lens systems for gaming stations and micro displays.

CMOS image sensors drive ultrathin wafer technology roadmap

One of the key breakthroughs that enables these major improvements in performance and price is backside illumination, which requires thinning the silicon wafer down to a transparent 5μm active layer, so the light can come in directly to the photo diode from the backside. Putting the electrical distribution layers behind the photo diode allows a simpler and more flexible BEOL architecture design, eliminating the need to leave openings in the pattern to let light through, and naturally lets in much more light, allowing higher resolution or higher sensitivity for the same given sensor size and cost. Next step, now in the development stage, is to take advantage of this increased design flexibility and add more intelligence to the system, by stacking a microprocessor DSP below the sensor — moving towards the ideal of controlling each pixel individually as in the human eye, for much improved sensor performance across different light conditions.

Click to Enlarge
Figure 1. Example of CMOS BSI "SOI" process flow. (Source: Yole Développement, "CMOS Image Sensors: Technology and Markets 2010")

The BSI process flow starts with making the photo diodes. Then the device wafer is bonded at low temperature to a silicon or glass carrier, using either adhesive polymers or molecular oxide-to-oxide bonding. US-based 3D-IC company Ziptronix offers one low-temperature bonding solution, which presses together ultraflat wafers, well prepared through specific surface preparation treatments. Next, the 1mm thick photo diode wafer is thinned down to 40-50μm with Disco or Accretech grinding tools, then thinned further with CMP, and finally etched down to an etch-stop layer at 5μm. This radical wafer thinning typically requires precise control of wet etching after initial grinding and CMP. One option, used by Sony and others, is to use SOI wafers from Soitec, using the buried oxide layer as an inner etch stop layer at the oxide interface — though the high cost of SOI wafers may limit the process to high-end imaging applications only. Others, including OmniVision, working with TSMC and Xintec, claim to have developed a lower-cost alternative process using bulk silicon wafers with graded implant layers. The trick is to find a highly selective etch chemistry that will stop precisely at the required 5μm thin silicon interface, just before reaching the photodiode structures.

Also critical is the annealing process, since this 5μm thin silicon film needs to include a very narrow implant gradient, to prevent recombination in the epi silicon and to push the photons down to the photo diodes. Since typical annealing ovens can only be controlled to about 30μm layer precision, the finer implant gradients require annealing with a nano-second, local heating laser process. The French equipment company Excico supplies a tool that uses a UV excimer type of laser source with a large spot for tight precision with better image quality and higher throughput.

This ability to build and handle these ultrathin layers also opens new possibilities for 3D stacking and integrating very thin active layers monolithically on top of other semiconductor applications. Indeed, such type of process set-up has the potential to be re-used in the future for 3D integration of memory + memory, logic + memory or MEMS + logic applications.

Coming next: Wafer-level integration of optics

The next development just starting to impact the CMOS image sensor business is wafer-scale integration of the optics, to drastically reduce size and cost, and to simplify the assembly process and supply chain. The camera module unit remains one of the largest components in most cell phones, and among the most complex to manufacture, requiring sourcing and assembly of up to 15 different components, including not only lenses, but also IR filters, caps, barrels, spacers, autofocus mechanisms, and other parts. An attractive alternative is wafer-level processing of optical lenses, today already in low-volume production by Heptagon for STMicroelectronics and by Anteryon for Toshiba camera modules.

Click to Enlarge
Figure 2. Wafer-level camera module assembly steps. (Source: Yole Développement, "CMOS Image Sensors: Technology and Markets 2010")

A typical wafer-level optic process involves dropping a polymer layer on to a glass wafer, pressing in the desired pattern through molding and UV replication with nanoimprint lithography tools, to imprint some 4000 lenses at once on each 8-in. wafer. This wafer is then aligned and bonded to another lens or spacer wafer, then tested and finally diced into small, low-cost optical lens camera-module cubes.

Companies are also working on integrating autofocus functions at the wafer level. A number of players, including SEMCO, are working on electro active polymers, whose thickness can be controlled and driven electrically by applying a defined voltage. Others like Siimpel (recently acquired by Tessera) have a MEMS- based solution, using a spring-like silicon structure.

But the front-runner currently appears to be a potentially breakthrough technology using liquid crystal polymers. The startup LensVector plans to start production this year of a four-layer stack of 8-in. glass wafers, encapsulating liquid crystal polymers that change shape when voltage is applied to the driving electrodes — all in less than 500μm total thickness. This technology has the potential to significantly bring down the size and cost of camera modules in the future.

These increasingly integrated optics will likely find application in other products as well, to simplify the manufacture and reduce the size and cost of other optoelectronics, across applications ranging from biomedical endoscopy to consumer products like digital cameras, pico projectors, headsup automotive displays, projection systems for gaming, and LED lighting.

Wafer-level packaging moves to higher-performance devices, more applications

Image sensor makers were among the first to move to volume production of wafer-level packaging and through-silicon vias (TSVs), as the technologies offered a solution to the big yield losses from the complex demands of alignment in packaging and assembling the optics with the high cost sensor chips into plastic modules. From initial use of Tessera’s ShellcaseOP glass-capping technology with low-end CIF and VGA format single megapixel camera units, the WLP technology has moved upstream to more complex and finer pitch devices up to 2-3 megapixels. TSMC’s Xintec packaging unit is currently running more than 200,000 8-in. WLPs a year, mostly for OnmiVision. Toshiba, Samsung, and STMicroelectronics are producing internally in volume. Considerable MEMS volumes, and some LEDs and memory chips as well, are also starting to use similar technology as the infrastructure builds up worldwide and costs come down with volume.

Click to Enlarge
Figure 3. CMOS image sensors technology drivers — new challenges to face. (Source: Yole Développement, "CMOS Image Sensors: Technology and Markets 2010")

Jerôme Baron tracks MEMS and advanced packaging technologies and markets at Yole Développement. He recently authored the report "CMOS Image Sensors: Technology and Markets 2010".

(May 17, 2010) LYON, France — An IC foundry has made it into the ranks of the Top 20 MEMS foundries for the first time, as TSMC’s roughly $10 million in MEMS foundry revenues put it into 14th place on Yole Developpement’s 2009 listing. STMicro improved slightly, continuing to dominate the MEMS foundry arena. TI slipped, holding onto #2; Dalsa gained, and grabbed the #3 slot.

Click to Enlarge
TOP 20 MEMS Foundries – 2009 revenues.

In 2010, STMicroelectronics continues to dominate the MEMS foundry business, with some 40% share, up slightly in 2009, as its revenues held up significantly better than most of the other major foundries in the downturn in consumer electronics and automotive sales. Healthy 19% growth pushed Dalsa Corp. past Micralyne Inc. to become the largest of the pure-play MEMS foundries with $31 million in revenues. Dalsa moved into third place overall, closing the gap with number two Texas Instruments (TI), who saw its foundry business slip 24% last year to $45 million. Perennial MEMS market leaders TI and Hewlett Packard (HP) were the top overall MEMS suppliers in 2009, although they were no longer dominant in the market like in the past.

Foundries continued to gradually take a larger share of total MEMS production, with total foundry revenues at the leading companies holding up somewhat better than MEMS sales overall. Top 20 foundry revenues, which account for the vast majority of the foundry business, declined about 3% in 2009, slightly less than the roughly 5% drop in MEMS sector revenues overall.

Asia Pacific Microsystems (APM) and Touch Microsystems (TMT) rode the Asian growth wave to 17% and 29% increases in sales, respectively. Jazz Semiconductor saw 25% growth, as startups started production of some new MEMS applications.

HP is now the largest customer for MEMS foundry services, as the inkjet nozzle maker pursues a fab-light strategy. InvenSense and Knowles Electronics follow as the next largest users, and the first companies to make a significant success — with revenues of more than $80 million — using the fabless model to build a business in innovative MEMS products, with their low-cost consumer gyroscopes and sector-leading MEMS microphones, respectively.

IC companies with their available 8″ fab capacity will continue to make inroads in the MEMS business, as they master different MEMS product technologies and figure out how best to manage the multiple different process flows. Meanwhile the specialty MEMS foundries — all still under $35 million in annual sales, and most much under that — have to figure out how to afford advanced production technology for larger volumes, at consumer product margins. That may leave foundries focusing on a bimodal distribution of tasks — doing, on one hand, the more standard volume manufacturing of mainstream technology that is not key to product differentiation, and on the other hand doing the development of the most sophisticated leading-edge devices where specialized manufacturing experience can provide faster time to market.

More of the big IDMs that dominate the MEMS market are also offering or using foundry services to make most efficient use of their capital investment. MEMS makers from Sony to GE Sensing and Olivetti are offering their production services to select outside customers to help fill their fabs. Even Robert Bosch has restarted offering limited foundry services in its fab, helping companies with prototyping and running multi project wafers — as long as customers use Bosch technology blocks without customization.

Meanwhile, other MEMS producers are turning to external foundries instead of adding or updating their own captive capacity. Yole figures another five major MEMS systems makers are now looking to use external foundries, which will boost the foundry business by some $350 million.

Read the 2009 MEMS suppliers report from Yole.

For more information, visit www.yole.fr

(May 13, 2010) ELK GROVE VILLAGE, IL — As part of its bonded wafer inspection technology, Sonoscan demonstrated acoustic imaging of defects in the seal that surrounds and protects the cavities in MEMS devices.

Click to EnlargeThe defects most frequently take the form of voids (Device 1) within the seal, Click to Enlargewhich may be direct silicon (Si), metallic, glass, or polymer, depending on the reliability level of hermetic seal required as per SEMI MS8-0309. In some locations on a wafer, the seal may be breached (Device 2). Another frequent defect is delamination of the seal from one or both substrates, the result of poor wetting or contamination during fabrication.

The defects are risky because thermal and mechanical stresses can cause them to grow until they result in a leak in the seal and subsequent loss of the desired cavity atmosphere. The seal prevents outside particles, gases, and humidity from reaching the cavity. Humidity, for example, can result in freezing up of moving parts within the cavity.

Defects in the seal may be only a few tens of microns in diameter and of submicron thickness, but can be imaged by Sonoscan’s C-SAM systems because they represent a gap that reflects >99.99% of the VHF/UHF ultrasonic pulse.

In production, a percentage of MEMS devices may be imaged with C-SAM acoustic micro imaging systems to verify that process parameters are preventing the formation of voids. Where high reliability is essential, as in mil/aero or medical MEMS, 100% of devices may be inspected.

For more information on inspection services, contact SonoLab manager Ray Thomas at (847) 437-6400 x245. For more information on inspection systems, contact Sonoscan’s technical marketing manager Steve Martell at (847) 437-6400 x240.

The images show Sonoscan acoustic images of voids (Device 1) and a breached seal (Device 2) in MEMS devices before wafer dicing.

by Neha K. Choksi

May 12, 2010 – Optical lithography methods are expensive, lack flexibility, and lack resolution for the sub-50nm node. Nanoimprint lithography (NIL) is considered an attractive alternative. NIL is a method of patterning in which a three-dimensional surface pattern of a stamp is transferred onto a moldable surface film on a substrate through mechanical contact. The resulting 3-dimensional pattern on the surface coating is then transferred to the underlying wafer by common semiconductor processing techniques.

Most imprint lithography vendors use spin on tools to create a 50nm thin-film surface coating before embossing. Molecular Imprints, however, has a different approach: Jet and flash imprint lithography (J-Fil). S.V. Sreenivasan, founder and CTO of Molecular Imprints, shared the company’s approach with attendees at the IEEE San Francisco Bay Area Nanotechnology Council seminar on April 20, 2010.

Because real world applications of nanolithography entail pattern complexity and density variations at both the macro and micro scale, this technique deposits the surface coating where it is most needed on the substrate by leveraging standard inkjet technology (see figure). After low-pressure embossing, the resist is UV cross-linked before the mask is separated from the surface, eliminating the use of solvent. The mask makes contact in the middle of the field with radial sweeping action to minimize bubble formation.

The key to this inkjet deposition method is a low-viscosity monomer resist and the use of small volume droplets (on the order of 1.5pL). Because the droplet density can be tailored to the desired pattern density, the fluid travels less distance during the stamping process. Also, the use of this "drop on demand" technique reduces the thickness and the variation of the residual layer that is inevitably left on the lower surfaces of the 3-D resist imprint. This reduces overall non-uniformities of the final pattern. The inkjet tool itself must be carefully calibrated, as variation exists even between same inkjet models.

Click to Enlarge
Step-and-flash imprint lithography process. Benefits include throughput (room-temperature process) and lower capital cost (no track system). (Source: Molecular Imprints)

The company is careful to control the surface energy of the mask. The need to keep the surface energy low enough to allow easy release of the mask from the resist, but not so low that the mask surface itself will not consistently wet, must be carefully controlled. Initially, this technique leveraged a stepper technique for imprinting — the precise fluid deposition reduces the edge bead challenges enabling successful stitching of fluid fields. However, the company now has the option of whole substrate printing as well.

By leveraging its NIL technique for a variety of applications, the company aims to be a market leader in the field. Because the cost-sensitive magnetic storage industry requires a high-density of precise islands of magnetic material separated by non-magnetic material, their high-resolution, low-cost patterning technique of NIL is an attractive solution when compared to the costly 193nm optical lithography method. The company has also demonstrated 2.55nm linewidth roughness and 18nm half-pitch using their stepper patterning technique for non-volatile memory applications. In this case, NIL can be mixed and matched with mainstream photolithography to achieve the associated critical dimensions where necessary.

Furthermore, researchers at the University of Texas are exploring the use of NIL technology for biomedical applications. By leveraging the J-Fil technique to create well-controlled dot structures, researchers are able to study the impact of particle shape, aspect ratio, and size on the effectiveness of particles for targeted nanoparticle drug delivery to fight lung cancer. Because the process selectively deposits the material before patterning, the material waste is less than that of spin or roll-on techniques. This enables a lower cost per dose when compared to other techniques.

Despite its success, Sreenivasan concedes that imprint lithography is not yet ready for all applications. For example, silicon microprocessors have a low tolerance for defects thus making it an unlikely fit at this time. Regardless, Sreenivasan is optimistic that the company’s non-traditional approach to NIL will enable it to further lower cost and reach 10nm feature sizes for production solutions on the horizon.

Neha K. Choksi is an independent consultant based in Mountain View, CA. She has worked for a variety of MEMS companies including as director of product engineering at Silicon Microstructures and as a consultant focusing on commercialization and high volume production of MEMS devices. E-mail: Choksi [at] gmail.