Wafer Level Packaging

WAFER LEVEL PACKAGING ARTICLES


Georgia Tech targets thin 3D packaging with new consortium

04/11/2012 

Georgia Tech's Packaging Research Center proposes a new consortium on 3D semiconductor packaging called 3D ThinPack for ultra-miniaturized 3D heterogeneous, RF, digital and power modules in partnership with global companies.
Invensas face-down die packaging replaces SODIMM

04/11/2012 

Invensas Corporation, a wholly owned subsidiary of Tessera, unveiled a DIMM-IN-A-PACKAGE multi-die face-down (xFD) packaging architecture for memory semiconductors in low-profile devices.
Endicott Interconnect names David Van Rossum new CFO

04/10/2012 

Endicott Interconnect Technologies has appointed David W. Van Rossum to the position of Chief Financial Officer, effective immediately.
ONNN

04/09/2012 

ON Semiconductor (Nasdaq: ONNN) will develop a next-generation star tracker CMOS image sensor with the European Space Agency. The sensor will be used in star trackers, sun sensors and other scientific applications.
Terepac builds miniaturized embedded circuits with wireless connectivity

04/03/2012 

Terepac Corporation, developer of tiny digital electronics, has launched the TereTag miniaturized circuit design that is embedded in items to enable the "Internet of Things."
Semiconductor wafer fab utilization rates bucked expectations in late 2011

03/29/2012 

The Global Semiconductor Alliance (GSA) released its GSA Q1 Wafer Fabrication & Back-End Pricing Reports, tracking fab utilization rates, wafer and mask costs, and package pricing.
Cypress Semiconductor transfers back-end packaging lines to China

03/27/2012 

Cypress Semiconductor transferred 7 back-end semiconductor package assembly lines from its Philippines facility to Chinese packaging subcontractor Jiangsu Changjiang Electronics Technology Co.
TI adds bare die to small-quantity semiconductor packaging options

03/27/2012 

Texas Instruments Incorporated (TI, TXN) now offers bare die in quantities as low as 10 pieces for initial prototyping, and larger quantities (full waffle trays) for production volumes.
Imec ultrathin chip packaging yields improved

03/23/2012 

Research organization imec introduces important changes to its ultrathin chip packaging (UTCP) technology, increasing yields 15-20%.
SEMICON Europa 2012 seeks presenters

03/23/2012 

SEMI is seeking papers for technical sessions and presentations at the upcoming SEMICON Europa 2012, October 9-11 in Dresden, Germany. Technical presentation abstracts are due April 30.
Texas Instruments (TI) embedded die package teardown report released

03/22/2012 

Texas Instruments' MicroSiP module is the first embedded die package in high volume production. Yole D
Taiwan allows higher Chinese investments in LCDs, semiconductors, fab equipment, more

03/21/2012 

Taiwan raised investment ceilings for Chinese investors in LCDs, semiconductors, IC assembly and test, microelectronics production equipment, and metal tool manufacturing.
Altera taps Amkor for molded flip chip packaging of FPGA family

03/21/2012 

Altera Corporation will use an exposed-die molded flip chip technology from Amkor on its 28nm Arria V FPGA. Amkor
Amkor (AMKR) names Taiwan leader with semiconductor packaging background

03/16/2012 

Amkor Technology Inc. (Nasdaq: AMKR) added Mike Liang as president of Amkor Technology Taiwan. Liang's background includes stints with Phoenix Semiconductor, Ti-Acer, UMC, and others.
IBM drills optical vias in chip for 1Tbit/sec transmission

03/09/2012 

IBM scientists developed a prototype optical chipset, Holey Optochip, that can transfer 1Tbit per second as a parallel optical transceiver, using optical vias through a standard 90nm CMOS chip.
AMAT, Singapore's microelectronics institute open 3D semiconductor packaging R&D lab

03/07/2012 

Applied Materials Inc. (AMAT) opened the new Centre of Excellence in Advanced Packaging at Singapore
STATS ChipPAC brings FOWLP to stacked packages for <1mm profile

03/06/2012 

STATS ChipPAC Ltd. (SGX-ST:STATSChP) uncrated its next-generation eWLB package-on-package (PoP) technology, with a package profile height below 1.0mm.
Flip chip bumping, WLP partnership unites FCI and NANIUM

03/06/2012 

"Together, FCI and NANIUM offer a complete WLP service portfolio covering 150, 200 and 300mm wafer sizes," summarized Armando Tavares, NANIUM president of Executive Board.
Plessey Semiconductors debuts ECG sensor from passive component project

03/05/2012 

Plessey Semiconductors developed the Electric Potential Integrated Circuit (EPIC) sensor, optimized for use as an ECG sensor, at a reportedly lower cost and better resolution than conventional electrodes. It enables ECG monitoring in mobile phone applications.
Two-element wafer-level camera from Nemotek boasts low distortion

02/28/2012 

Nemotek Technologie uncrated a two-element wafer-level camera, Exiguus H12-A2. The two-element lense gives Exiguus H12-A2 high resolution and low (<0.5%) distortion.



WEBCASTS


Environment, Safety & Health

Date and time TBD

The semiconductor industry is an acknowledged global leader in promoting environmental sustainability in the design, manufacture, and use of its products, as well as the health and safety of its operations and impacts on workers in semiconductor facilities (fabs). We will examine trends and concerns related to emissions, chemical use, energy consumption and worker safety and health.

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Wafer Processing

Date and time TBD

As the industry moves to 10nm and 7nm nodes, advances in wafer processing – etch, deposition, planarization, implant, cleaning, annealing, epitaxy among others – will be required. Manufacturers are looking for new solutions for sustained strain engineering, FinFETs, FDSOI and multi-gate technologies, 3D NAND, and high mobility transistors.

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