Wafer Level Packaging

WAFER LEVEL PACKAGING ARTICLES



Will PoP delay TSV adoption? TechSearch International analyzes the 3D technologies

05/19/2011 

PoP provides a cost/performance solution that solves business and logistics issues associated with stacking devices directly. 3D TSV, with its associated uncertainties, cannot yet meet PoP's benefits, says TechSearch International (TSI).

Non-planar device scaling: SEMATECH talks TSV, SoC, SiP

05/19/2011 

The semiconductor industry is moving to 3D device structures, says Raj Jammy, SEMATECH, at The ConFab 2011, discussing TSV and system-in-package (SiP) opportunities and challenges. He also summarizes logic and memory roadmaps.

Ramtron taps KYEC for SATS on its F-RAM

05/18/2011 

Ramtron (NASDAQ: RMTR) named Taiwan-based King Yuan Electronics Co., LTD (KYEC) to provide semiconductor assembly and test services (SATS) for its entire line of F-RAM products.

More Moore & More than Moore require fabless, foundry, and packaging houses on board

05/17/2011 

Complex supply chain. SOURCE: Yu, The ConFabToday at The ConFab, John Chen (Nvidia), Jeong-ki Min (Samsung Electronics), and Abraham Yee (Nvidia) gathered foundry, OSAT, and chip maker leaders to discuss what happens beyond Moore's Law. The following are key points from "Collaboration to Strengthen the IC Supply Chain."

Benchmark "mid-end" tools and materials for 3DIC and wafer-level packaging (WLP)

05/13/2011 

Yole Développement released "Equipment & Materials for 3DIC and Wafer-Level-Packaging," a database and complete report analyzing in detail the equipment and materials tool-box for wafer-level packaging (WLP). This semiconductor packaging technology falls into the "mid-end," where frontend semiconductor wafer fabs and backend packaging facilities both operate.

3D packaging disrupts the IC supply chain -- ConFab session dedicated to the OSAT/foundry/fabless relationship

05/13/2011 

The ConFab gathers semiconductor industry leaders to discuss the biggest trends in the chip manufacturing sector. One of these major trends is 3D packaging, and Session 2 on Monday (May 16) will combine packaging house, fabless, and foundry approaches to the new supply chain, with speakers from Amkor, GLOBALFOUNDRIES, STATS ChipPAC, and Qualcomm.

Rudolph's 3D package inspection system meets TSV, RDL, bump inspection needs

05/12/2011 

Rudolph Technologies' Wafer Scanner 3880 inspection and measurement systemRudolph Technologies (NASDAQ: RTEC) released the Wafer Scanner 3880 to inspect micro and standard bumps, through silicon via (TSV) post-via-fill copper protrusions (nails) and re-distribution layers (RDL) used in 3D IC packaging.

Tessera CEO & president Nothhaft resigns, Young takes his place

05/12/2011 

Tessera Technologies, Inc. (NASDAQ: TSRA) Board of Directors appointed Robert A. Young, Ph.D., as president and CEO, taking over for Henry R. Nothhaft, who resigned to pursue his advocacy of smart innovation policies in Washington DC.

CoolChip's thermal management tech brings in MIT prize

05/11/2011 

CoolChip Technologies won the MIT Clean Energy Prize for their technology that reduces data center cooling needs with air-based CPU cooling.

RFaxis' pure-CMOS on-die coexistence filter reduces package size, current consumption

05/10/2011 

RFaxis released its patent-pending On-Die Coexistence Filter technology, designed to replace "bulky and expensive" stand-alone coexistence filters for cellular, mobile, and other devices.

Multitest adds extended temp control to MT9510 test handler

05/06/2011 

Multitest, a designer and manufacturer of final test handlers, contactors and load boards, now provides extended temperature control with its extended temperature calibration (XTX) on the MT9510 test handler.

CSCD WLCSP HVM test probe card retains pin, scales from x1 to x8

05/06/2011 

Cascade Microtech (CSCD) launched a WLCSP probe card series that retains pin position, scales from x1 to x8 on a per-die basis, and can be configured for individual die testing. The Viper series will be used for high-volume test to qualify known good die (KGD).

SRC attacks 3DIC reliability, design tools with new effort

05/05/2011 

Semiconductor Research Corporation is leading an effort to address key roadblocks for wide-scale adoption of the emerging 3D ICs and systems. These new initiatives will address critical reliability and design tool issues and leverage partnership between researchers from universities and the semiconductor industry.

NXP metrology labs tap Tektronix for test/measurement equip calibration and repair

05/05/2011 

NXP named Tektronix Service Solutions to provide calibration and repair services for all test and measurement instruments at NXP's production and development sites in the Netherlands.

Leadframe package design tool combines CAD Design, Cadence IP

05/04/2011 

CAD Design Software combined its Electronics Packaging Designer (EPD) and Cadence Design Systems' Allegro IC Package design and analysis environment to create a "Silicon Realization" flow for ICs in leadframe packages.

STATS ChipPAC invests in copper wire bonding for 45nm, low-k

05/04/2011 

STATS ChipPAC Ltd. (SGX-ST: STATSChP), semiconductor test and advanced packaging service provider, has shipped over 300 million semiconductor packages with copper wire-bond interconnects. The SATS provider is investing in Cu wire bonding for finer silicon nodes (45/40nm) and low-k/extra low-k.

GN ReSound taps eSilicon for ASIC ramp up

05/03/2011 

Hearing aid maker GN ReSound contracted with eSilicon Corporation, independent semiconductor Value Chain Producer, for production of the AD4.0 ASIC. This ASIC is a key component in next-generation hearing instruments from GN ReSound.

NASA orders Flexpoint Bend Sensors

05/02/2011 

Flexpoint was unable to reveal the application in which NASA is using Bend Sensors, though Clark Mower, president of Flexpoint, called the project a "new and expansive area of potential use of our technology."

RDL: an integral part of today's advanced packaging technologies

05/01/2011  RDL technology has been instrumental in the development of many advanced packaging technologies such as fan-in and fan-out WLP, and TSV applications. Philip Garrou, MCNC, Research Triangle Park, NC; Alan Huffman, RTI Int., Research Triangle Park, NC

IC packaging report covers 12 package types + bare die, SATS providers

04/28/2011 

New Venture Research will release "The Worldwide IC Packaging Market, 2011 Edition" in May 2011. It provides analysis of packaging by I/O count and package type, bare die interconnect, and looks at the major semiconductor assembly and test services (SATS) providers.




WEBCASTS



Environment, Safety & Health

Date and time TBD

The semiconductor industry is an acknowledged global leader in promoting environmental sustainability in the design, manufacture, and use of its products, as well as the health and safety of its operations and impacts on workers in semiconductor facilities (fabs). We will examine trends and concerns related to emissions, chemical use, energy consumption and worker safety and health.

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Wafer Processing

Date and time TBD

As the industry moves to 10nm and 7nm nodes, advances in wafer processing – etch, deposition, planarization, implant, cleaning, annealing, epitaxy among others – will be required. Manufacturers are looking for new solutions for sustained strain engineering, FinFETs, FDSOI and multi-gate technologies, 3D NAND, and high mobility transistors.

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