Wafer Level Packaging

WAFER LEVEL PACKAGING ARTICLES



Semiconductor packaging substrates future wiring density needs: Join the discussion

09/16/2010 

Meeting these future needs will require radical improvements and innovations in all aspects of organic packaging substrate technology. A pre-competitive iNEMI R&D project plan, currently under development, will identify approaches capable of meeting wiring density needs for future generations of organic semiconductor packaging substrates. Meeting these future needs will require radical improvements and innovations in all aspects of organic packaging substrate technology.

STATS ChipPAC opens 300mm embedded WLP BGA (eWLB) manufacturing fab

09/15/2010 

STATS ChipPAC Ltd. opened a new 300mm embedded Wafer-Level Ball Grid Array (eWLB) manufacturing facility, switching over from 200mm technology. The official inauguration was held at STATS ChipPAC's Yishun facility in Singapore with more than 150 local dignitaries, customer representatives, business partners and management participating.

PoP rework: Process control and using the right materials increases yield

09/13/2010 

POP after package rework.PoP packages present some unique rework challenges, such as how to rework an underfilled package; also, these packages are prone to warpage. Inspecting the area array devices can be a challenge. Bob Wettermann, BEST Inc., discusses rework solutions.

Freescale licenses RCP to Nepes, brings redistributed chip packaging to 300mm in Singapore

09/13/2010 

Freescale will license its redistributed chip packaging technology to Nepes, Korean semiconductor parts and materials specialist. Nepes and Freescale will also collaborate on RCP development.

SATS providers join top 20, says Gartner

09/10/2010 

Gartner VP of semiconductor manufacturing research, Jim Walker, notes that, for the first time, 2 SATS companies joined the top 20 capital spenders in 2010. He also predicts solid growth for advanced packaging tooling with memory ATE and copper wire bonders being the top performers. Walker says the conversion to copper wire from gold is a wise move.

Low-k dielectric family introduced by SBA Materials

09/07/2010 

The IC community has been searching for a manufacturable low-k dielectric which could scale to below K = 2.0, says Dr. Phil Garrou. Microindent photos of uLK 124, released by SBA Materials show a clean ductile indent. SBA reports that their uLK materials can be integrated into existing fab lines using equipment and process flows already in place.The IC community has been searching for a manufacturable low-k dielectric which could scale to below K = 2.0, says Dr. Phil Garrou. Microindent photos of uLK 124, released by SBA Materials show a clean ductile indent. SBA reports that their uLK materials can be integrated into existing fab lines using equipment and process flows already in place.

Next-gen bond tester software launch from Nordson DAGE

09/07/2010 

Nordson DAGE, a subsidiary of Nordson Corporation (NASDAQ: NDSN) and provider of bond testing technology, introduced Paragon intelligent bond testing software for semiconductor packaging.

Flip chip bonding, printed electronics, no-litho subjects of IeMRC Conference

09/02/2010 

The 5th annual IeMRC Conference, September 21 in Loughborough, UK, will include 4 sessions: Advanced packaging, Materials processing and assembly, Printed electronics, and EPSRC.

KGD Packaging and Test Workshop keynote, panel on TSV, and more

09/01/2010 

KGD (Known Good Die) Packaging and Test Workshop 2010 will focus on semiconductor die products test, assembly, manufacturing, and business issues in the microelectronics industry. Bill Bottoms will keynote, covering deep submicron and 3D integration.

GaAs test services debut from WIN Semiconductors, Presto Engineering

09/01/2010 

Users of WIN's GaAs foundry services can engage in wafer-level and package test in Silicon Valley, CA, and Grenoble, France.

Fraunhofer's Ramm will open International Wafer-Level Packaging Conference

08/31/2010 

Peter Ramm, Fraunhofer EMFT, will be the Opening Speaker at the 7th Annual International Wafer-Level Packaging Conference (IWLPC). Ramm will present "The European 3D Technology Platform for Heterogeneous Systems" at the Kick-Off Reception.

QFN chip packaging expansion at Carsem

08/30/2010 

Carsem is aggressively expanding its MLP/QFN package manufacturing capacity in Ipoh, Malaysia and Suzhou, China factory locations. This capacity expansion in assembly is matched with an equal proportion of test capacity expansion.

Murata nibbles RFMI stocks, signs collaboration agreement

08/26/2010 

Murata purchased 533,000 shares of RF Monolithics Inc. (RFMI) common stock at a small premium over RFM’s recent 30 day volume weighted average price, in a private transaction. RFM and Murata Manufacturing Co. Ltd. have entered into a collaboration agreement.

DSP on FPGA workshops planned by Avnet, MathWorks, TI

08/25/2010 

The series of workshops focuses on digital signal processing (DSP) system design using Xilinx FPGAs with high-speed data converters. These workshops are being offered to design engineers in North America.

Wire-bonding/AOI, chip mounting areas linked: Case study from IPTE

08/24/2010 

Continental Corporation applied economic conveyor and handling modules from IPTE’s EasyLine product portfolio to link its gold and aluminum wire bonding, mounting, and AOI areas. Continental Corporation applied economic conveyor and handling modules from IPTE’s EasyLine product portfolio to link its gold and aluminum wire bonding, mounting, and AOI areas.

Combination chipset shipments will near 280M in 2010, says ABI Research

08/24/2010 

Shipments of “combo” chipsets for mobile devices that gather a variety of connectivity types in one small package are expected to approach 280 million worldwide by the end of 2010. Integrating different radio technologies such as FM, Bluetooth, Wi-Fi and GPS on a single chip may sometimes involve performance compromises, but saves money, space and power.

Gyroscope integrates MEMS/ASIC in custom package

08/23/2010 

Sensonor Technologies is developing SAR500, a novel high-precision, low-noise, high-stability, calibrated and compensated digital oscillatory gyroscope with SPI interface housed in a custom-made ceramic package.

SiliconBlue highest logic capacity FPGA in 6x6mm package

08/23/2010 

SiliconBlue Technologies, provider of custom mobile devices for consumer handset applications, debuted two device packages for its iCE65 mobileFPGA family. The iCE65L01 FPGA device with 1,280 logic cells is now offered in a 5x5 mm, 81-ball BGA package with 63 user I/O pins, and the iCE65P04 device with 3,520 logic cells is now offered in a 6x6 mm, 121-ball BGA package with 95 user I/O pins.

IDTechEx launches active RFID and sensor networks report

08/16/2010 

The IDTechEx report, "Active RFID and Sensor Networks 2011-2021," comprehensively analyzes the technologies, players and markets with detailed 10-year forecasts, including tag numbers, unit prices and interrogator numbers and prices.

TSV: Current challenges and solutions with Novellus

08/13/2010 

In this video interview, Sesha Varadarajan, Novellus, says that capacitance issues must be overcome, and the PVD step must provide good enough coverage to properly apply copper. CTE mismatch can also cause issues.




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Environment, Safety & Health

Date and time TBD

The semiconductor industry is an acknowledged global leader in promoting environmental sustainability in the design, manufacture, and use of its products, as well as the health and safety of its operations and impacts on workers in semiconductor facilities (fabs). We will examine trends and concerns related to emissions, chemical use, energy consumption and worker safety and health.

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Wafer Processing

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As the industry moves to 10nm and 7nm nodes, advances in wafer processing – etch, deposition, planarization, implant, cleaning, annealing, epitaxy among others – will be required. Manufacturers are looking for new solutions for sustained strain engineering, FinFETs, FDSOI and multi-gate technologies, 3D NAND, and high mobility transistors.

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