Wafer Level Packaging

WAFER LEVEL PACKAGING ARTICLES



Power savings of embedded computing modules (ECMs) over FR-4 implementations

12/31/2009 

Silicon circuit board (SiCB) technology allows bare-die FPGAs, CPUs, and memory to be placed together on a single silicon substrate. Embedded computing modules using SiCB offer better performance than FR-4 material -- notably 22% reduced power consumption in a typical system, reports David Blaker from siXis Inc.

Ultrathin, stackable QFN packages

12/08/2009 

Tom Adams from Sonoscan describes advances with "chip-in-polymer technology, developed at Germany's Fraunhofer IZM, which achieves 3D packaging advantages through better shock/vibration protection and shorter interconnect distances.

IMAPS 2009: Fusion bonding for 3D/TSV, wafer-level/multichip packaging for MEMS

11/30/2009 

Presentations at this year's International Symposium on Microelectronics (IMAPS, San Jose, Nov. 1-5) included discussion of TSV/3D integration challenges and temporary bonding steps qualified for different process flows, and a wafer-level packaging (WLP) encapsulation process and stacked multi-chip package (MCP) for a MEMS variable capacitor and control IC chip.

AMAT buys Semitool, deepens inroads into AP, Cu for memory

11/17/2009 

Execs from Applied Materials and Semitool discuss the motivations behind AMAT's $364M acquisition, to solidify and widen a presence in two key growth segments: advanced packaging and copper interconnects for memory.

Avoiding ASIC expense and risk with SiCB technology

10/26/2009 

Embedded computing modules employing "silicon circuit board" technology as an alternative to expensive ASIC developments offer advantages in performance and power for integrating memory and logic -- and are a practical alternative to 3D integration due to thermal and supply chain issues, explains siXis' David Blaker.

Rudolph scores backend inspection biz from ASE

10/09/2009 

Taiwanese subcon ASE has ordered "multiple" tools for backend inspection from Rudolph Technologies, illustrating a trend to incorporate real-time process control into advanced backend fabrication processes.

TI: Fast ramp at backend site to meet "steep demand"

09/22/2009 

SST/AP gets an update on Texas Instruments' progress ramping its new assembly/test facility in the Philippines -- which had been ramped far ahead of schedule in response to "unprecedented" demand.

Canada opens 200mm MEMS, 3D WLP center

09/03/2009  September 2, 2009: A new Microelectronics Innovation Center is being formed at the Université de Sherbrooke in Bromont, Québec, to focus on 200mm MEMS and 3D wafer-level packaging, and other "advanced technologies associated with the assembly and packaging of silicon chips."

Nemotek Technologie sizes up its future in wafer-level cameras

09/01/2009  (September 1, 2009) MOROCCO — Jacky Perdrigeat, CEO of Nemotek Technologie, discusses the company's technology and business strategy, as it opens a new logistics center in Hong Kong with electronics component distributor Anglia.

Commercializing a WLCSP passivation layer solution

08/31/2009  Lord Corp. exec Russell Stapleton talks with SST about the company's first-generation passivation layer solution for wafer-level chipscale packaging, due to launch in 1Q10.

HyperBGA Product Line

08/27/2009  August 27, 2009 -- Endicott Interconnect Technologies (EI) announced improved capabilities of HyperBGA® PTFE-based "coreless" semiconductor package. Now packing more power and density with the addition of signal layers, HyperBGA® enables semiconductor devices to run at extremely high speeds.

siXis partners with SVTC to commercialize silicon circuit boards

08/24/2009  August 24, 2009 -- SVTC was chosen by technology startup siXis, Inc. to supply silicon manufacturing services for their compact, high-speed embedded computing modules that bridge the gap between programmable devices and costly, customized semiconductors.

New Method to Form Ultra-Thin Device Wafers

08/11/2009  August 11, 2009

International Wafer-Level Packaging Conference (IWLPC) Finalized

07/22/2009  The 6th Annual International Wafer-Level Packaging Conference (IWLPC), October 27-30, 2009, Santa Clara, CA includes tutorials, expert panel discussions, Dr. Rao Tummala keynoting, and 18 tech sessions.

Interplex Acquires Quantum Leap Packaging

07/20/2009  Component and assembly maker Interplex Industries acquired Quantum Leap Packaging Inc. (QLP), an electronics packaging and polymer science company. Included in the transaction are all of QLP's proprietary technologies including resin technologies such as Quantech for hermetic semiconductor packaging.

SEMICON West: Jan Vardaman and Paul Siblerud Analysis

07/17/2009  Paul Siblerud, SEMITOOL, discusses the role of the EMC-3D consortium in developing new packaging technologies, such as through silicon vias (TSV). Jan Vardaman, TechSearch International, examines the barriers, and breakthroughs, around 3D integration.

Nanolab Technologies Adds X-Ray Capabilities

07/01/2009  July 1, 2009 -- Xradia, Inc., a developer and manufacturer of high-resolution 3D X-ray imaging systems, announced a partnership with NanoLab Technologies. The companies will offer 3D X-ray imaging as part of a service model that enables customers in the electronics and semiconductor industry to address semiconductor packaging development and failure analysis challenges while evaluating the purchase of their own systems.

Xradia adds 3-D X-ray capabilities to Nanolab Technologies

06/09/2009  June 9, 2009: Xradia Inc. and NanoLab Technologies Inc. have formed a partnership to offer 3D X-ray imaging as part of a service model to help address semiconductor packaging development and failure analysis challenges.

Conference on 3D Architectures for Semiconductor Integration and Packaging

06/02/2009  The 2009 3D Architectures for Semiconductor Integration and Packaging Conference and Exhibition will bring together industry leaders to examine the practical and competitive landscape on the path to implementation of 3D integration and packaging technologies, December 9 through 11, 2009, in Burlingame, CA.

ECTC 2009 In Review

06/01/2009  In a time when R&D is at the forefront of the industry, events like ECTC 2009 become critical for showcasing research achievements, as well as providing venues for learning about the latest developments across the spectrum of device manufacturing. With 16 professional courses, 39 sessions of 6 papers each, two poster sessions, and the opportunity to mix it up with prestigious members of academia and research institutes, calling the event informative would be an understatement.




WEBCASTS



Environment, Safety & Health

Date and time TBD

The semiconductor industry is an acknowledged global leader in promoting environmental sustainability in the design, manufacture, and use of its products, as well as the health and safety of its operations and impacts on workers in semiconductor facilities (fabs). We will examine trends and concerns related to emissions, chemical use, energy consumption and worker safety and health.

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Wafer Processing

Date and time TBD

As the industry moves to 10nm and 7nm nodes, advances in wafer processing – etch, deposition, planarization, implant, cleaning, annealing, epitaxy among others – will be required. Manufacturers are looking for new solutions for sustained strain engineering, FinFETs, FDSOI and multi-gate technologies, 3D NAND, and high mobility transistors.

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