12/11/2008  By Sergey Savastiouk, ALLVIA
Almost 10 years ago (January 2000) I wrote an article for SST titled "Moore's Law &#151 the Z-dimension". The call was to shift focus towards Moore's Law in the z-dimension and then invest in affordable, vertical miniaturization and integration, rather than continue to invest in further feature size reduction. A new term&#151through silicon vias (TSVs)&#151was first introduced in that article and is now commonly used.

12/11/2008  In a pre-emptive measure to avert an increase in unemployment throughout Europe, SEMI is appealing to EU and national policymakers to invest in Europe's semiconductor industry, citing its importance to the health and global competitiveness of the EU economy.

12/01/2008  By Gail Flower, editor-in-chief
One of the best parts of our industry is the spirit of cooperation, camaraderie, and outreach that seems to embody all that's best in human nature. Advanced Packaging often collaborates with industry organizations to plan and/or co-sponsor events. I recently returned from a cooperative effort with MEPTEC in honor of its 30th anniversary with a program titled, Packaging Developments and Innovations: From System Design to Integrated Delivery.

12/01/2008  I would like to clarify the comments you attributed to me as a result of our conversation at IMAPS International. I do not believe I said that through silicon vias (TSVs) were a pipedream, nor did I doubt that they would be adopted. What I said was that they would not be adopted at the rate projected. That is why I referenced the flip chip vs. wire bond issue as an historical reference.

11/25/2008  STATS ChipPAC Ltd. has expanded its quad flat no-lead (QFN) packaging portfolio with a strip-etch version for applications requiring increased design flexibility and higher input/output (I/O) performance in a small, thin package profile. The new QFN package family, referred to as QFNs-se, reportedly features a higher number of very thin I/O terminal pads than conventional single or dual-row QFN or leadframe-based quad flat packages (QFPs).

11/18/2008  by Julia Goldstein, Ph.D. contributing editor
Speakers at MEPTEC's Packaging Developments and Innovations Symposium, November 13, 2008 in San Jose, CA, presented various new technologies to enable package miniaturization while keeping costs in check. Much of the focus was on materials innovations that optimize the existing infrastructure. One departure from that was discussions surrounding through silicon via (TSV) advancements.

11/17/2008 

By R. Wayne Johnson, Ph.D., Auburn University

While $4/gal.gasoline prices have dropped, it is inevitable they will rise again. So what does this have to do with advanced packaging? A lot! While we hear discussions of alternate energy, we will continue to use oil for the foreseeable future. Electronics (and advanced packaging) are important for measurements during well drilling and for production management over the life of the well.

11/03/2008  Synergetix test socket interposers for wafer-level chip scale package (WLCSP) testing are used for vertical probing applications. The interposers have a plastic assembly containing IDI's semiconductor probe technology built in. Combined with an easy-to-design-and-fabricate load board, interposers require minimal attention throughout their life cycle.

11/01/2008  Typically, when we hear the phrase intellectual property, we immediately think about theft and protection.

10/31/2008  By Paul Collander, Poltronics, Inc. At the recent Advanced Packaging Conference at SEMICON Europe in Stuttgart, Germany, (October 7-9, 2008) Fran

10/30/2008  By Fran

10/29/2008  SUSS MicroTec and Surface Technology Systems (STS) are once again hosting a technology roadshow in five major Asian locations from October 29 to November 7. Similar to the US roadshow last spring, the series of one-day events is intended to provide a comprehensive overview of the latest developments 3D Integration and advanced packaging.

10/22/2008  Ziptronix execs reveal technical details on its direct bond interconnect technology, which the company says is key to low-cost wafer-to-wafer or chip-to-wafer bonding without high-temperature compression.

10/22/2008  MEPTEC, the MicroElectronics Packaging and Test Engineering Council, and Advanced Packaging magazine have finalized the program for their upcoming symposium titled "Packaging Developments and Innovations: From System Design to Integrated Delivery" to be held on Thursday, November 13, 2008 at the Wyndham Hotel, San Jose, CA.

10/14/2008  By Fran

10/13/2008  By V. Gektin, M. Stern, Sun Microsystems; L. Larson, D. Bhagwagar, J. Marin, Dow Corning Corp. K.Nakayoshi , Dow Corning Toray Co., Ltd.
As power levels and heat generation increase in high-performance CPUs and other semiconductor devices, the thermal performance of commonly used packaging components is becoming a limiting factor. A silver-filled silicone material specifically for TIM 1 applications (the die/lid interface) was designed to meet this challenge.

10/09/2008  In a keynote speech at SEMICON Europa, SEMI Europe president Heinz Kundert presented highlights from a paper urging renewed efforts to increase Europe's microelectronic industry competitiveness, highlighting increased R&D funding, cultivating the workforce, and protecting and enforcing IP.

10/09/2008  October 9, 2008: Holiday Creations/Diogen Lighting Inc. and Evident Technologies Inc. plan to enable a new type of LED based on semiconductor nanocrystals (quantum dots), that enable never-before-seen colors and new design possibilities, to be commercialized in the seasonal light strand market in the US and Canada.

10/07/2008  Suss MicroTec has replaced board member and CEO Stefan Schneidewind with Christian Schubert effective immediately, citing "differing views regarding the future strategy of the company." A search for a new permanent CEO will take place.

10/01/2008  A packaging engineer living in this Information Age has an obligation to keep on top of everything that’s happening.