Wafer Level Packaging

WAFER LEVEL PACKAGING ARTICLES



Vietnam - Chipscale Advanced Packaging Services Receives Certification

05/14/2008  Vietnam-Chipscale Advanced Packaging Services, an outsource semiconductor assembly and test services provider based in Vietnam, has been presented with its investment certificate from th Vietnamese government, recognizing the company as a 100% foreign owned venture.

STATS ChipPAC Completes Qualification of Fan-in PoP

05/13/2008  STATS ChipPAC Ltd. announced the completion of full internal qualification of its Fan-in Package-on-Package (FiPoP) technology. Fully functional electrical samples are available, and production volumes are expected to ramp by the end of 2008.

Renesas Adopts Cadence Tool for Large Scale SoC and Flip Chip Design

05/12/2008  Cadence Design Systems, Inc. announced that Renesas Technology Corp. has successfully taped out its most advanced and large-scale system-on-chip (SoC) design to date using the Cadence SoC Encounter system. Hisaharu Miwa, general manager, Design Technology Division LSI Product Technology Unit at Renesas credits the system's memory capacity and fast turnaround time as the reason for the successful tape out.

SMTA's 3D/SiP Symposium Promotes Industry-wide Collaboration

05/06/2008  Last week's 3D/SiP Symposium hosted by SMTA, and co-sponsored by Advanced Packaging magazine, turned out to be an intimate gathering of approximately 55 attendees representing not only the U.S., but Canada, France, Japan, Taiwan, United Kingdom, Austria and the Republic of Korea.

Chemical Monitoring and Replenishing Systems

05/06/2008  The Qual-Fil QF Series combines ECI Technologies' chemical monitoring technology with dosing capabilities to address the need for precision metal plating in advanced packaging applications. The modular system supports both electroplating and electroless deposition. It can manage multiple plating baths simultaneously due to online monitoring and automatic replenishment of multiple components.

Flip Chip Goes 3D

05/06/2008  By Daniel F. Baldwin, Ph.D. and Paul Houston, ENGENT, Inc.
With advances in wafer-thinning technology, 3D packaging now provides a robust platform for achieving high levels of integration, small package footprints, and thin package profiles. Further component miniaturization with the added benefit of 3D integration can be realized by face-to-face bonding of fine-pitch flip chip components and low-profile passives onto a redistribution layer (RDL) of another silicon component.

Oerlikon Esec Introduces Product Family at SEMICON Singapore

05/05/2008  Oerlikon Esec, provider of automated chip assembly equipment and system solutions for the semiconductor industry, formally introduced the introductory platform of an entirely new product family at an official unveiling during SEMICON Singapore. The Die Bonder 2100 xP targets the high-volume epoxy die attach market.

Choosing the Best Bump for the Buck

05/01/2008  Flip chip interconnect offers the advantages of smaller footprint on the PCB, improved electrical performance, reduced manufacturing steps at assembly, and excellent long-term reliability.

Who’s Who at BiTS, SEMICON China and IMAPS Device Packaging Symposium

05/01/2008  The Advanced Packaging editors covered a lot of ground this spring as co-sponsors of the Burn-in and Test Socket (BiTS) Workshop in Mesa, AZ, attending SEMICON China in Shanghai, and the IMAPS Device Packaging Symposium in Scottsdale, AZ.

Cleaning High-power Electronics A closed-loop SOlvent-Based Approach

05/01/2008  Flux residues must be be removed from flip chip components prior to subsequent processes to prevent malfunctions in high-power electronics.

3D Packaging Technologies Expected to Dominate Industry

04/23/2008  3D packaging is expected to emerge as a dominant performing solution in the electronic/chip packaging industry. Its performance promises to drive efforts across the entire supply chain to successfully deploy it, according to analysis reports from Frost & Sullivan's Global Trends in Electronic/Chip Packaging. Analysis indicates that the industry is moving beyond system on chip (SoC) to explore various forms of system in package (SiP).

Lee to Deliver Keynote at MEPTEC MEMS Packaging Symposium

04/18/2008  Luke P. Lee, Ph.D., from the Department of Bioengineering at UC Berkeley has been selected as keynote speaker for MEPTEC's 6th Annual MEMS Packaging symposium titled "MEMS Market Evolution: From Technology Push to Market Pull" on May 22, 2008. This one-day event will take place at the Wyndham Hotel, San Jose, CA.

BiTS Workshop: A Success Story

04/14/2008  By Gail Flower, editor-in-chief
The ninth annual Burn-in and Test Socket Workshop (BiTS 2008) on March 9-12, 2008 in Mesa, AZ, presented an interactive, growing, and technical successful forum for experts dedicated to sharing knowledge. BiTS brought together 350 conference attendees and 60 exhibitors worldwide from users of sockets, boards, burn-in systems, handlers, packaging engineers, and suppliers to the industry.

SEMICON China Expanding

04/14/2008  By Gail Flower, editor-in-chief
On March 18-19 2008, a constant stream of visitors flowed in to SEMICON China, held in the Shanghai New International Expo Centre, to attend grand new product introductions and educational forums that addressed the latest in growth areas for electronics. What a clip of activity surrounded the conference. All of the familiar players were there doing business.

STS Receives Order for DRIE Tool from TU Dresden

03/20/2008  ; Surface Technology Systems plc (STS) has announced that they have sold a Pegasus deep reactive ion etch (DRIE) tool to the Institut f

TU Dresden orders Pegasus system from STS

03/19/2008  Surface Technology Systems plc (STS), which deals with plasma process technologies required in the manufacturing and packaging of MEMS and advanced electronic devices, has sold a Pegasus Deep Reactive Ion Etch (DRIE) tool to the Institut für Halbleiter- und Mikrosystemtechnik (IHM, or Semiconductor & Microsystems Technology Laboratory).

Alchimer CEO Predicts Demise of Vapor Deposition Processes for TSVs by 2009

03/18/2008  ; After being appointed CEO of Alchimer SA, Steve Lerner immediately predicted the demise of vapor deposition processes for depositing nanoscale films in through silicon vias (TSVs) within a year. Steve Lerner is a technologist with 29 years' experience in semiconductor development and manufacturing. He founded advanced packaging and device companies Alpha Szenszor, GigSys, and CS2, and has held executive positions at Amkor, Swire, and AME.

Line of Assembly Materials
Heraeus Contact Materials Division


03/17/2008  This company's latest versions of its assembly materials will include conductive and nonconductive adhesives for die attach and flip chip applications, heat conductive adhesives for thermal management, and dippable solder pastes for BGA packaging. Given the increasing complexity of BGA packages and the sensitivity of the polymer substrates to multiple thermal processes, the ball dippable (BD) paste series enables manufacturers to utilize SOP substrates while maintaining outstanding yields.

Advanced Placement System
Juki Corp.


03/17/2008  The CX-1 advanced placement system is capable of placing SiP, MCM and other mixed-technology applications. The CX-1 is built on the base of a standard SMT machine, but with highly accurate glass linear encoders. Special software periodically checks and calibrates to ensure ultra-high accuracy.




WEBCASTS



Environment, Safety & Health

Date and time TBD

The semiconductor industry is an acknowledged global leader in promoting environmental sustainability in the design, manufacture, and use of its products, as well as the health and safety of its operations and impacts on workers in semiconductor facilities (fabs). We will examine trends and concerns related to emissions, chemical use, energy consumption and worker safety and health.

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Wafer Processing

Date and time TBD

As the industry moves to 10nm and 7nm nodes, advances in wafer processing – etch, deposition, planarization, implant, cleaning, annealing, epitaxy among others – will be required. Manufacturers are looking for new solutions for sustained strain engineering, FinFETs, FDSOI and multi-gate technologies, 3D NAND, and high mobility transistors.

Sponsored By:

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