Wafer Processing

WAFER PROCESSING ARTICLES



SEMICON West 2011: New product roundup

07/27/2011 

SEMICON West may not be the big-iron displayfest it once was, but there are still plenty of new product introductions to go around. Here's just a brief rundown of some of the ones we tracked from this year's show.

EVG expands HQ, hiring 100

07/27/2011 

EV Group (EVG), wafer bonding and lithography equipment supplier, began a manufacturing capacity expansion at its Austrian headquarters, adding floorspace, equipment, worker comforts, and a state-of-the-art visitor area. EVG will hire about 100 new staff members as part of the expansion.

Green wafer fab chemistries that work

07/27/2011 

ATMI's SVP/CTO, Larry Dubois shares the 3 guidelines ATMI keeps in mind when designing eco materials for semiconductor wafer fab, and gives an update on the materials supplier's LED fab products.

Wall Street view: Top takeaways from SEMICON West

07/26/2011 

A trio of analysts who participated in SEMICON West's Bulls/Bears panel have some top-takeaways list for the industry: why WFE spending is slow, why it's only a short pause, and which will comes first, EUV or 450mm.

TSV zen comes down to wafer processing balance

07/26/2011 

3D semiconductor packaging processes involve various groups, and standards are important in the hand-offs between them, explains Mark Berry, sales director at Metryx. He covers how to use metrology to protect wafer yields in 3D packaging.

Suss MicroTec 3D IC workshop addresses thin wafer handling and testing

07/25/2011 

At SEMICON West, 100+ attendees gathered at the Suss MicroTec workshop "3D Integration: Are we there yet?" to hear technical experts from around the globe to present updates on the status of 3D technology.

First Semiconductor Fab for Central and South America Gains Design Approval

07/21/2011 

A four-month fab design verification project was approved for CEITEC S.A., for what is said to be the first semi conductor manufacturing facility to be built in Central and South America. CEITEC S.A. is a Brazilian company that produces application-specific standard products (ASSPs) for RFID, wireless communication and digital multimedia. The design verification project was overseen by Lotus Technical Services, one of five operational divisions of the LotusWorks based in Sligo, Ireland.


Translucent demos LED growth via one-step epitaxy with rare earth oxides on Si

07/18/2011 

Translucent demonstrated its Mirrored Si technology on a 100mm-diameter wafer that exhibits high reflectivity using a lattice-matched REO material grown on a Si substrate, capped by a GaN layer that can support further nitride epitaxy for LED structure growth.

How EVG accomplished the 1st 450mm printed wafer; HVM expected 2015-2017

07/18/2011 

SEMATECH announced a 450mm imprinted wafer, accomplished by EV Group (EVG). Markus Wimplinger, EVG, described the timeline for the 450mm effort and how the company decided to make a strategic move.

Replisaurus advanced Cu metallization process nears commercialization at Leti

07/15/2011 

CEA-Leti and Replisaurus Technologies will begin applying Replisaurus' ElectroChemical Pattern Replication (ECPR) metallization process to customer target products, following a near-100% yield master.

SEMATECH survey on 2.5D, 3D IC; gaps in the via-mid ecosystem

07/14/2011 

Sitaram Arkalgud, director of interconnect at SEMATECH, discusses the high-volume manufacturability issues and gaps in both 2.5D and 3D semiconductor technologies with respect to backside processing and wafer bonding, thinning, and handling. Standards are also covered.

450mm update: Participation rising, patterning defined, “low risk” determined

07/14/2011 

Updates from ISMI's 450mm industry briefing at SEMICON West reveal intensifying participation and development underway for most required capabilities, and evaluations showing "low risk" for factory integration.

MHI 8" wafer bonder produces 3D LSI ICs at room temp with FAB gun

07/13/2011  Mitsubishi Heavy Industries Ltd. (MHI) developed a fully automated 8" wafer bonding machine that bonds large-scale integration (LSI) circuits at room temperature, creating 3D ICs.

Cymer talks EUV, TCZ, light source monitoring upgrade

07/13/2011 

Nigel Farrar, Cymer, provides a status report on EUV lithography source technology, extensions to ArF lithography, the laser crystallization process from the company's TCZ display equipment product division, and Cymer's newest DUV source product the OnPulse Plus data monitoring system.

GLOBALFOUNDRIES uses Intermolecular combinatorial method to improve wafer fab

07/13/2011 

GLOBALFOUNDRIES will use Intermolecular's High Productivity Combinatorial technology on research and development of its next-generation and mature semiconductor manufacturing lines.

Thermal wafer processing for Ni(Pt)Si contacts beyond 45nm

07/12/2011 

The formation of advanced thin nickel-silicide films poses major challenges as devices integration moves beyond the 45nm technology node. X. Pages et al, Renesas Electronics, explain how optimized low-temperature rapid thermal processing (RTP) annealing schemes address this issue.

Olympus inspects bonded wafers with IR microscopy

07/12/2011 

Greg Baker, Olympus Integrated Technologies America, discusses why the company chose to focus its efforts on IR metrology for defect inspection of bonded wafers. Olympus-ITA launched the latest 3DIR Metrology and Defect Review System at SEMICON West 2011, booth 1524.

Suss joins imec's EUV mask integrity work

07/12/2011 

Suss Microtec and imec are expanding a research collaboration in mask cleaning to develop an in-fab approach to EUV lithography mask integrity, aiming to develop a sophisticated approach to preserving mask integrity prior to exposure.

AMEC reactive ion etch tool enables sub-28nm nodes

07/11/2011 

AMEC launched its Primo 300mm very-high-frequency advanced decoupled reactive ion etch tool for sub-28nm. AMEC's Ben Lee describes the tool's mini-batch cluster architecture, and the physics that makes it work.

EVG tool bonds 450mm SOI semiconductor wafers

07/11/2011 

EV Group (EVG) released a wafer bonding system for 450mm silicon-on-insulator (SOI) wafers: EVG850SOI/450-mm. EVG's Paul Lindner discusses the tool, and challenges of 450mm and SOI.




WEBCASTS



Environment, Safety & Health

Date and time TBD

The semiconductor industry is an acknowledged global leader in promoting environmental sustainability in the design, manufacture, and use of its products, as well as the health and safety of its operations and impacts on workers in semiconductor facilities (fabs). We will examine trends and concerns related to emissions, chemical use, energy consumption and worker safety and health.

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Wafer Processing

Date and time TBD

As the industry moves to 10nm and 7nm nodes, advances in wafer processing – etch, deposition, planarization, implant, cleaning, annealing, epitaxy among others – will be required. Manufacturers are looking for new solutions for sustained strain engineering, FinFETs, FDSOI and multi-gate technologies, 3D NAND, and high mobility transistors.

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