Wafer Processing

WAFER PROCESSING ARTICLES



TSMC begins "phase 1" for LED aspirations

03/26/2010 

TSMC has officially broken ground for its new LED lighting R&D center and fab in Taiwan's Hsinchu Science Park, part of its multibillion-dollar initiative to establish a foothold in higher-growth markets outside of core IC fabrication.

Tegal offloads legacy etch/PVD lines, forging ahead with DRIE

03/23/2010 

Amid efforts to keep afloat as the industry tides recover, Tegal Corp. has sold off much of its technology portfolio to the OEM Group, and is poised to forge on with DRIE and certain deposition technologies.

Analyst: Massive profits, but modest recovery

03/22/2010 

The semiconductor industry is at its most profitable point now than any other time in the past decade thanks to industrywide efforts to aggressively manage costs and capacity -- but wild optimism about surging growth forgets the truth that this recovery only resets to levels from three years ago, according to iSuppli.

Die attach equipment and ESD

03/17/2010 

Substantial amounts of electrostatic discharge (ESD) damage are not only possible, but probable in semiconductor die attach operations, leading to substantial yield losses. Roger Peirce and Brad Williford from Simco illustrate seven distinct mechanisms in typical die attach operations that cause electrostatic discharge (ESD) damage to chips being handled.

LED boom based on lighting expected to lead to "third cycle" in the market

03/12/2010 

The light-emitting diode (LED) market has gone through two cycles of major growth, but an even bigger "third cycle" based on super-efficient lighting looms ahead, reports SST's Bob Haavind from a recent SEMI breakfast at Teradyne near Boston on March 10. And the wide range of problems to be tackled will make it an attractive target for those now in the semiconductor processing markets.

Reports: LCD sector takes brunt of Taiwan quake

03/09/2010 

Last week's 6.4-magnitude earthquake in Taiwan caused some emergency evacuations and shutdowns among the island's electronics manufacturing sector, with the biggest impact so far seeming to be in the LCD manufacturing sector.

Gartner: Worldwide semiconductor capital equipment spending to grow 76% in 2010

03/08/2010 

Worldwide semiconductor capital equipment spending is projected to surpass $29.4 billion in 2010, a 76.1% increase from 2009 spending of $16.7 billion, according to Gartner Inc. Gartner cites a dramatic recovery in semiconductor orders for the equipment order surge.

SPIE Roundup: EUV/EBMI demo, 11nm NIL, ASML's EUV roadmap, the skinny on DOE...

03/02/2010 

Several discussions and presentations at last week's SPIE Advanced Lithography Conference deserve special note -- from work with e-beam EUV mask inspection, to nanoimprint achievements (11nm!), an EUV tool platform roadmap, mask productivity and cost issues at 22nm, and more on SMO and tunable DOEs.

Lithography and wafer bonding solutions for 3D integration

03/01/2010 

Given the advantages and technical feasibility of through-silicon vias (TSV), the major focus now is on the manufacturability and integration of all the different building blocks for TSVs and 3D interconnects. EV Group's Thorsten Matthias et al. review advances in lithography, thin wafer processing, and wafer bonding, and the integration of all these process steps.

Comparative study of advanced boron-based ULE doping

03/01/2010  B2H6 PLAD and B18H22 molecular implants demonstrate the best Rs-xj and abruptness characteristics, while beam-line BF2 implants as well as cluster B implants show worse Rs-xj characteristics.Shu Qin, Y. Jeff Hu, Allen McTeer, Micron Technology, Inc., Boise, ID USA

III-V MOSFETs: beyond silicon technology

03/01/2010  Results so far are highly encouraging for III-V MOSFETs to be used for ultra high speed, and ultra low power applications. Richard J.W. Hill, Jeff Huang, Joel Barnett, Paul Kirsch, Raj Jammy, SEMATECH, Austin TX USA

Burn-in and Test Socket (BiTS) Workshop Preview

02/26/2010 

The Burn-in & Test Socket (BiTS) Workshop will take place March 7–10, 2010 at the Hilton Phoenix East/Mesa Hotel in Mesa, AZ. More than 30 papers and posters will be presented; participants include end users and suppliers of sockets, boards, burn-in systems, handlers, and packages; and other related equipment, materials, and services. The TechTalk session on PCB design, fabrication and assembly is booked full, as is the tutorial on RF socket characterization by Gert Hohenwarter, Ph.D. of Gatewave Northern Inc. Here are some of the show highlights.

ESI appoints David Nierenber to board

02/26/2010 

Electro Scientific Industries Inc. (Nasdaq: ESIO), a provider of photonic and laser systems for micro-engineering applications, appointed a new member, David Nierenberg, to its Board of Directors. Nierenberg, with professional experience in investing and management consulting, comes to ESI with significant expertise in strategic planning and corporate governance matters.

KLA-Tencor brings stochastic modeling to virtual tool for EUV, DPL

02/22/2010 

Sanjay Kapasi from KLA-Tencor tells SST how the latest-generation PROLITH virtual lithography tool, PROLITH X3.1, takes aim at the skyrocketing R&D expenses being incurred at the 1X and 2Xnm nodes, by leveraging simulations rather than printed test wafers.

Keithley's latest system goes for ultra-fast I-V solution

02/19/2010 

Keithley exec Lee Stauffer explains how adding ultra-fast voltage waveform generation and current/voltage measurement capabilities to the company's Model 4200-SCS semiconductor characterization system benefits a range of applications, from flash memory to CMOS and MEMS.

Reverse costing analysis of the Infineon X-GOLD 213-eWLB fan-out wafer-level package

02/17/2010 

System Plus Consulting released its new reverse costing analysis of the enhanced Wafer Level BGA (eWLB) packaging used in the X-GOLD 213 circuit from Infineon. eWLB is a ball grid array (BGA) package based on the emerging fan-out wafer-level package (FO-WLP) concept. All the packaging operations are done at the wafer level, and a fan-out area is provided to extend the package size beyond the IC surface area to allow for higher ball counts. The ball pitch is 0.5mm and only one redistribution layer is used for this 217 balls, 8 × 8mm package.

SEMI: Wafer shipments retook lost ground in 2H10

02/16/2010 

After two months of punishing declines, worldwide silicon wafer shipments rebounded through most of 2010, though in terms of sales there's still a lot of ground to make up, according to new numbers from SEMI.

SMIC shuffles execs, confirms investor talks

02/10/2010 

Confirming rumors, Chinese flagship foundry Semiconductor Manufacturing International Corp. (SMIC) says it has appointed several new top execs, and that it is in talks with an unidentified investor for a financial infusion.

Chip tool demand still climbing through end of '09

01/25/2010 

Demand for semiconductor capital equipment continued to increase in the final month of 2009, and with the key book-to-bill ratio now six straight months above parity suggests growth still lies ahead, according to the latest industry data.

Novellus launches SOLA xT UVTP system for sub-45nm HVM

01/25/2010 

Execs from Novellus Systems describe how the company's new Sola xT ultraviolet thermal processing system addresses high-volume manufacturing of advanced logic devices at 45nm and below -- and how it potentially stacks up in wafer-to-wafer performance vs. competitors' offerings.




WEBCASTS



Environment, Safety & Health

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The semiconductor industry is an acknowledged global leader in promoting environmental sustainability in the design, manufacture, and use of its products, as well as the health and safety of its operations and impacts on workers in semiconductor facilities (fabs). We will examine trends and concerns related to emissions, chemical use, energy consumption and worker safety and health.

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Wafer Processing

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As the industry moves to 10nm and 7nm nodes, advances in wafer processing – etch, deposition, planarization, implant, cleaning, annealing, epitaxy among others – will be required. Manufacturers are looking for new solutions for sustained strain engineering, FinFETs, FDSOI and multi-gate technologies, 3D NAND, and high mobility transistors.

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