Wafer Processing

WAFER PROCESSING ARTICLES



Back-end Semiconductor Manufacturing Heating Up

09/16/2009 

Rudolph Technologies, Inc., announced that is has received orders for 20 tools from the world’s four largest outsourced assembly and test (OSAT) companies and major foundry companies. The orders are for Rudolph’s automated macro defect inspection equipment, which typically sell within a range of $600k to $1.2m. 

Controlling AMCs in semiconductor and LCD fabs

09/15/2009 

Researchers from Taiwan's ITRI, Winbond Electronics, and TPO Displays discuss case scenarios and follow-up procedures for mitigating airborne molecular contaminants (AMC) -- and improving yields -- in semiconductor and TFT-LCD manufacturing environments.

KLA-Tencor goes for 2xnm trifecta with Teron 600 reticle defect inspection platform

09/15/2009 

September 14, 2009 - KLA-Tencor exec Dan Lopez gives SST a preview of its new Teron 600 Series mask defect inspection system, with programmable scanner-illumination capability and improvements in sensitivity and computational lithography power to address a major transition in mask design at the 2Xnm logic (3Xnm half-pitch memory) node.

Ultratech: Melt LSA at sub-16nm, readying move to FinFETs

09/09/2009 

Ultratech execs Art Zafiropoulo and Jeff Hebb update SST on the status of laser-spike anneal (LSA) technology: readiness for 32nm, extendibility to 22nm, and evaluation for 16nm and beyond.

Abu Dhabi group pitches Chartered+GlobalFoundries merger combo

09/08/2009 

The Abu Dhabi backer of GlobalFoundries, the chip manufacturing spinoff of AMD, has pitched a $3.9 billion offer to take over Singapore's Chartered Semiconductor Manufacturing, creating a multifaceted and truly "global" foundry business.

Wafer-to-wafer Bonding: Using Pressure-indicating Film for Eutectic/Thermocompression Bonds

08/28/2009 

Kwan-yu Lai, Micralyne, and Jeffrey G. Stark, Sensor Products, describe the use of color-coded pressure-indicating film to ensure uniform, correct pressure during wafer bonding. Wafers are bonded by applying precise combinations of physical pressure, temperature, and/or voltage. Pressure is measured as an average, assuming perfectly flat pressure plates.

DirEKt Microsphere Ball Placement

08/28/2009 

Extending its capabilities for placing solder spheres at high speed, DEK's DirEKt Ball Placement process now enables accurate solder sphere deposition for spheres as small as 200µm in diameter with pitches as tight as 300µm.

Die-scale stress management to advanced annealing optimization

08/28/2009  Lithography overlay and leakage requirements are becoming increasingly stringent for the next-generation devices. Two case studies illustrate the role that stress non-uniformity has in misalignment and the effect of cumulative stress variations on device performance and leakage.

NIST, Maryland tout gold/Si "sandwich" for molecular switches

08/26/2009  August 26, 2009: Researchers from the U. of Maryland and the National Institute of Standards and Technology (NIST) say they've come up with a way to overcome a principle obstacle in creating molecular switches: sandwich organic molecules between silicon and metal.

Crystalline Si solar cells and the microelectronics experience

08/26/2009  This article from IMEC describes a roadmap for thin crystalline silicon, and the opportunities of using materials and process methods used in IC manufacturing.

TSMC adds low-power HK+MG to 28nm menu

08/25/2009  In a bid to "fully utilize" the benefits it can offer customers, Taiwan Semiconductor Manufacturing Co. (TSMC) says it will add a third flavor of its forthcoming 28nm process technology: a low-power high-k metal gate (HK+MG) one.

UK startup gets funding to push CNTs into chipmaking

08/24/2009  August 24, 2009: Carbon nanotube developer Surrey NanoSystems says it has secured a second round of funding totaling £2.5M (US $4.2M) to help commercialize its low-temperature growth process for carbon nanotubes, targeted for use as a replacement for copper interconnects in semiconductor devices.

Double-patterning design challenges

08/20/2009  With the move towards fabless models and the use of double-patterning, it is critical that layout designers and manufacturing engineers remain engaged in the discussion of effective design rules that provide the types of yield, predictability and cost information that IC companies require.

Developers push c-Si efficiency toward 20% with help from narrower interconnect

08/12/2009  Photovoltaic cells are getting steadily more efficient, and even the small area taken up by interconnect is shrinking to get more electrons flowing. Some of these developments were discussed at the recent Photovoltaic Specialists Conference in Philadelphia and at the accompanying PV America exhibition.

SEMI: Wafer shipments spike in 2Q

08/11/2009  More evidence of a pent-up semiconductor industry ready to surge (hopefully): global shipments of polysilicon in 2Q09 displayed by far the biggest growth spike of at least the past nine years, according to data from SEMI's Silicon Manufacturers Group (SMG).

Unlocking laser tools' potential in c-Si cell fabs

08/10/2009  Ensuring laser-based tools are accepted as standard equipment during the production of high-efficiency crystalline silicon (c-Si) cells requires better understanding of the process windows involved, qualification of new tooling optimized for specific applications, and a clearly identified supply-chain.

Behind Brewer Science's wafer bonding work

08/10/2009  (August 10, 2009) SAN FRANCISCO, CA -- Karen Twillmann, executive director of corporate marketing at Brewer Science, and Dan Wallace, the company's director of 3D packaging, discusses the advances made by the company's temporary bond adhesive for wafer bond applications.

IDT going fabless, partnering with TSMC

08/08/2009  August 7, 2009: Integrated Device Technology (IDT) is giving up on the fab-lite model and going completely fabless, transferring its fabrication processes to TSMC over the next two years.

Galaxy Thin Wafer System from DEK

08/05/2009  Building on its Galaxy imaging platform, DEK has used the foundation of the technology's supreme accuracy and precision to develop a system specifically for processing thinned silicon wafers.

EVGroup: Ready for whatever comes with 3D integration

08/05/2009  Steven Dwyer, VP & GM, North America at EV Group, provides highlights of 3D integration papers the company presented at SEMICON West. By achieving alignment accuracy down to 200nm, thin wafer handling at thicknesses <10μm, and 300mm-capable wafer bonding, he says the company is ready for whatever comes along.




WEBCASTS



Environment, Safety & Health

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The semiconductor industry is an acknowledged global leader in promoting environmental sustainability in the design, manufacture, and use of its products, as well as the health and safety of its operations and impacts on workers in semiconductor facilities (fabs). We will examine trends and concerns related to emissions, chemical use, energy consumption and worker safety and health.

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Wafer Processing

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As the industry moves to 10nm and 7nm nodes, advances in wafer processing – etch, deposition, planarization, implant, cleaning, annealing, epitaxy among others – will be required. Manufacturers are looking for new solutions for sustained strain engineering, FinFETs, FDSOI and multi-gate technologies, 3D NAND, and high mobility transistors.

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