Wafer Processing

WAFER PROCESSING ARTICLES



SEMI demand at historic lows...but now at bottom?

03/24/2009  Demand for semiconductor manufacturing equipment continues to plod along at historic lows, but those seeking any sign of optimism may have a little ray of hope to point to.

2009 Spending on Fab Construction Products Expected to Reach Lowest Level Since 1999

03/22/2009  MARCH 19, 2009 -- SAN JOSE, CA -- All regions are showing double-digit declines in construction spending in 2009, with the possible exception of the Americas.

Litho firms climb up heap in bloody 2008

03/18/2009  In a year that ultimately was terrible for the semiconductor industry, a few firms managed to claw their way up the list of sales leaders, though the top firms remain well entrenched, according to data from VLSI Research.

Slimmer, stickier nanorods give boost to 3-D chips

03/18/2009  March 18, 2009: Researchers at Rensselaer Polytechnic Institute have developed a new technique for growing slimmer copper nanorods, a key step for advancing integrated 3-D chip technology.

Megasonic cleaning tool seeks a clean sweep at ≤65nm

03/17/2009  David Wang, founder and CEO of ACM Research, tells SST about his company's new Ultra C 300mm single-wafer megasonic cleaning tool debuting at this week's SEMICON China, targeting advanced cleans at the 65nm and below technology nodes where mechanical damage and defect levels are more fragile and challenging.

Double-duty tool cuts costs for c-Si solar-cell wafering

03/16/2009  Reducing wafer fabrication cost is considered key to the goal of making solar energy competitive with grid power. To this end is the goal of a new platform from Applied Materials that slices ingots into ultra-thin wafers.

Innovative Advanced Packaging Technologies Enable Leading-edge Wireless Products

03/16/2009  By Manish Ranjan, Ultratech Inc.
Leading-edge consumer electronic products demand innovative silicon and packaging solutions. While front-end silicon technologies have progressed at a pace defined by Moore's Law, the back-end infrastructure has lagged in similar advancements. This has created an interconnect gap whereby the signal speed achieved on the silicon side is significantly higher than the speed achieved on the printed circuit boards.

New inspection tool addresses yield, solar cell classification

03/12/2009  A new inspection product from KLA-Tencor/ICOS offers optical in-line dual-sided inspection of photovoltaic (PV) wafers and cells for all stages of the production process, from bare wafer to silicon nitride (SiN) coating, metallization, and final classification.

Revisiting the Path to Burn-in

03/03/2009  by James A. Forster, Ph.D., Antares Advanced Test Technologies
As IC manufacturers rely more on the burn-in process to bring the latest devices from fabs to consumers, it is important to understand burn-in test. As feature size is reduced into the nanometer range, designers can place more circuits on a square of silicon. As the number of transistors and the total amount of circuitry on a chip increases, the potential for a defect increases, leading to immediate or future failures.

Thin Wafer Processing

03/03/2009  By Hans Hirsher, Ph.D. and Hans Auer, Oerlikon Systems The demand for thin and ultrathin semiconductor devices grows continuously. Discrete and bipolar IC's as well as devices for stacking or thin packages require thinner and thinner wafers. The challenge is to find a reliable processing method.

CleanRooms Europe 2009

03/01/2009  Conference preview and exhibitor showcase.

Research advances nanowires for large-scale applications

02/27/2009  February 27, 2009: Researchers at Northeastern University created a network of nanowires that can be scaled up more efficiently and cost-effectively to create bigger displays -- such as the Nasdaq sign in New York City's Times Square.

Chip tool demand hits floor, keeps going

02/24/2009  Everyone expects the industry climate to get worse before it gets better. But perhaps how bad and how quickly is catching some by surprise. By several metrics, SEMI's latest monthly summary of tool demand is as bad as seen in two decades -- and even longer.

AMAT Joins EMC-3D Consortium

02/24/2009  Applied Materials, Inc. has joined the international EMC-3D semiconductor equipment and materials consortium, which focuses on 3D chip stacking and MEMS integration.

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Burn-in Test Socket Challenges

02/19/2009  By Gail Flower, Editor-at-Large This article provides a broad review of the issues affecting socket usage: lead-free challenges, finer pitch adjustments, cost control, standardization, practical customer concerns, and improvements needed for 3D packages and other innovations on the horizon. Through conversations with industry experts, we explore a few common themes from this year's Burn-in and Test Socket Workshop (March 8 -11, 2009) in Mesa, AZ.

Parallel Universes Draw Closer

02/19/2009  By Fred Taber, General Chairman, BiTS For the most part, the universe of wafer probes and the one for sockets have customarily been separate and distinct. Yet they parallel each other in so many ways: they provide temporary electrical contact to a device under test, and have many common technical challenges, such as contact resistance, signal integrity, tight pitch and cleaning, among many others.

SRC, IMEC pair for "green" chipmaking

02/18/2009  University research consortium Semiconductor Research Corp. has brought onboard European nanoelectronics R&D consortium IMEC to join work in creating "environmentally friendly" processes and materials for advanced semiconductor manufacturing.

SEMI: Wafer shipments, sales slide in '08

02/18/2009  Worldwide silicon wafer area shipments and revenues fell in 2008 for the first time since 2001 as everything fell apart in the final months of the year, according to date from SEMI's Silicon Manufacturers Group (SMG).




WEBCASTS



Environment, Safety & Health

Date and time TBD

The semiconductor industry is an acknowledged global leader in promoting environmental sustainability in the design, manufacture, and use of its products, as well as the health and safety of its operations and impacts on workers in semiconductor facilities (fabs). We will examine trends and concerns related to emissions, chemical use, energy consumption and worker safety and health.

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Wafer Processing

Date and time TBD

As the industry moves to 10nm and 7nm nodes, advances in wafer processing – etch, deposition, planarization, implant, cleaning, annealing, epitaxy among others – will be required. Manufacturers are looking for new solutions for sustained strain engineering, FinFETs, FDSOI and multi-gate technologies, 3D NAND, and high mobility transistors.

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