Monthly Archives: March 2001

March 9, 2001–Hsinchu, Taiwan–Taiwan Semiconductor Manufacturing Co. (TSMC) today announced plans to decommission its Fab 1 on the Chung Hsing Compound at Taiwan’s Industrial Technology Research Institute on March 31, 2002, following a phased decommissioning plan.

TSMC has leased Fab 1 from Taiwan’s Ministry of Economic Affairs and the Industrial Technology Research Institute since 1987. This lease agreement expires on March 31, 2001. Fab 1 uses 6-in. wafers primarily to produce logic products, with a full operating capacity of approximately 20,000 6-in. wafers per month.

March 9, 2001–Boston, Massachusetts–Teradyne Inc. is lowering its guidance for sales and earnings for the first quarter of 2001 and has put several expense control measures into effect.

“The current economic environment has dramatically reduced demand for our customers’ products. They therefore need fewer products and services from us. This is resulting in new order delays, as well as in rescheduling and cancellation of some of our backlog,” says George Chamillard, Teradyne’s chairman and chief executive officer. “Our sales and earnings for the March quarter will be lower than previously expected. Our previous guidance was for sales to be down about 20% from the $789 million of the fourth quarter (pre-SAB 101), and we anticipated about $0.30/share in earnings. We also said that there would be an additional $0.25/share in earnings from sales recorded in the first quarter due to the effect of SAB 101, for a total of $0.55/share. Our current view is for sales to be down about 35% from the fourth quarter level (pre-SAB 101), with a corresponding reduction in EPS.”

Terdayne expects that the additional $0.25/share from sales recorded in the first quarter due to the effect of SAB 101 will still be realized. “Our visibility is very limited at this point and we don’t know how long the current downturn might last. We are also implementing a series of cost-cutting measures to bring our expenses more in line with the conditions we find in the marketplace,” says Chamillard.

Expense control measures implemented by Teradyne include a cutback of its temporary workforce by more than 1400 people since the peak level; a company-wide hiring freeze; production furloughs in some areas; a delay in several capital spending projects; and the imposition of tight expense controls.

March 9, 2001–Santa Clara, California–Intel Corp. yesterday lowered its revenue outlook for the first quarter of 2001 and announced plans to reduce its workforce by 5,000. Intel now predicts that revenue for the first quarter will be down approximately 25% from its fourth quarter 2000 revenue of $8.7 billion.

The company expects spending in the quarter, excluding in-process R&D, to be down approximately 15% from its fourth quarter expenses of $2.4 billion, primarily due to lower revenue and profit-dependent expenses and the impact of cost-cutting measures.

“While slashing nonessential spending across the company, we are protecting investments we believe will make Intel more competitive,” says Andy D. Bryant, Intel executive vice president, chief financial and enterprise services officer. “Our R&D spending for 2001 has been revised only slightly–now forecast at $4.2 billion, down from the previous expectation of $4.3 billion, but still up from $3.9 billion in 2000. The reduced R&D expenditure is a result of cuts in discretionary spending, not the result of program cuts. Intel’s capital spending budget for 2001 is unchanged at $7.5 billion. This will be used to expand production and implement new technologies such as ramping the Pentium 4; getting market segment share in chipsets; implementing the 0.13-micron process, which will enable more processors at higher levels of performance and lower costs; and preparing for production of 300mm wafers, which will make possible unit die cost reductions of 30% starting in 2002.”

Intel’s workforce reduction is expected to take place during the next 9 months.

Partnering with SEMICON West 2001, we will announce the winners of The Advanced Packaging Awards in San Jose at a no-holds-barred evening affair after the show on July 18, 2001. Individuals who are immersed in the industry, including many from highly esteemed university programs and consortiums, have already signed on to sit on our experienced and unbiased judging panel.

Packaging: The Next Step
The editors of Solid State Technology and Advanced Packaging magazines joined forces to create a special supplement for our readers. From electroplating to flip chip to the basics, we’re certain you’ll learn something in this must-read issue. Click on the articles below and enjoy!

March 8, 2001–Atlanta, Georgia–Georgia Institute of Technology researchers have created a new class of nanometer-scale structure that could be the basis for inexpensive ultra-small sensors, flat-panel display components, and other electronic nanodevices.

Made of semiconducting metal oxides, these extremely thin and flat structures–dubbed “nanobelts”–offer significant advantages over the nanowires and carbon nanotubes that have been extensively studied. The ribbon-like nanobelts are chemically pure, structurally uniform, and largely defect-free, with clean surfaces not requiring protection against oxidation. Each is made up of a single crystal with specific surface planes and shape.

“Current research in one-dimensional systems has largely been dominated by carbon nanotubes,” says Zhong Lin Wang, professor of Materials Science and Engineering and director of the Center for Nanoscience and Nanotechnology at the Georgia Tech. “It is now time to explore other one-dimensional systems that may have important applications for nanoscale functional and smart materials. These nanobelts are the next step in developing structures that may be useful in wider applications.”

Wang and colleagues Zhengwei Pan and Zurong Dai have produced nanobelts from oxides of zinc, tin, indium, cadmium, and gallium. This family of materials was chosen because they are transparent semiconductive oxides, which are the basis for many functional and smart devices being developed today. But Wang believes other semiconducting oxides may also be used to make the unique structures.

“The crystallographic structure varies a great deal from one oxide to another, but they all have a common characteristic as part of a family of materials that have ribbon-like structures with a narrow rectangular cross-section,” Wang explains. “In comparison to the cylindrical symmetric nanowires and nanotubes reported in the literature, these are really a distinctive group of materials.”

Nanobelts may not have the high structural strength of cylindrical carbon nanotubes, but make up for that with a uniformity that could make them useful in electronic and optoelectronic applications. Processes for producing carbon nanotubes still cannot be controlled well enough to provide large volumes of high purity, defect-free structures with uniform properties. However, the nanobelts can be well controlled, allowing production of large quantities of pure structures that are mostly defect-free.

“Defects in any nanostructures strongly affect their electronic and mechanical properties and possibly cause heating when electrical current passes through them. This creates problems if you want to integrate them into smaller and smaller devices at a high density,” says Wang. “More importantly, defects can destroy quantum mechanical transport properties in nanowire-like structures, resulting in the failure of quantum devices fabricated using them.”

Nanowires made of silicon and other materials have also generated interest, but these structures oxidize and require complex cleaning steps and handling in controlled environments. As oxides, nanobelts do not have to be cleaned or handled in special environments and their surfaces are atomically sharp and clean.

Based on known properties of the oxide nanobelts, Wang points to at least three significant applications. Zinc oxide and tin oxide nanobelts could be the basis for ultra-small sensors because the conductivity of these materials changes dramatically when gas or liquid molecules attach to their surfaces. Tin-doped indium oxide nanobelts provide high electrical conductivity and are optically transparent, making them candidates for use in flat-panel displays. And because of their response to infrared emissions, nanobelts of fluoride-doped tin oxide could find application in “smart” windows able to adjust their transmission of light as well as conduction of heat.

“This is a vitally important area of nanotechnology,” Wang said. “If we are successful at these applications, it may lead to major technological advances in nano-size sensors and functional devices with low power consumption and high sensitivity.”

March 8, 2001–Santa Clara, California–National Semiconductor Corp. (NEC) today reported net income of $48.9 million, or 27 cents per share, on revenues of $475.6 million for the third quarter of fiscal 2001, which ended February 25, 2001. This excludes a pretax charge of $12.1 million for in process R&D related to the acquisition of innoCOMM during the quarter. Including that charge, the company reported net earnings of $39.2 million, or 21 cents per share.

In a weak overall semiconductor market, National maintained profitability by achieving gross margins of 49% during the third quarter. Margins benefited from the increasing number of proprietary analog products in the company’s product mix, which are less vulnerable to price erosion, and from National’s ability to maintain manufacturing efficiencies. “We will continue to focus on profitability and critical investments during this period of slower demand and inventory corrections in the wireless handset and PC markets,” says Brian L. Halla, president and chief executive officer.

During the quarter, National completed the acquisition of innoCOMM, a privately held analog design company that is a leading developer of chipsets for wireless networking applications. This acquisition strengthened National’s intellectual property and market position in the wireless sector, especially in high-end wireless RF capabilities including home networking and Bluetooth technologies.

“Although we saw bookings and turns orders improve in February, we are still maintaining a cautious outlook,” Halla reports. Turns orders are orders requested for delivery in the same quarter.

The company reports that third quarter worldwide bookings declined 30% sequentially from the second quarter of fiscal 2001, and 38% compared to the robust bookings of the previous year’s third quarter. After 3 months of sequential declines through January, bookings grew in February.

“We now anticipate a slight sales decline in the fourth quarter,” says Halla. “However, we expect total fiscal year 2001 sales to marginally exceed last year’s revenues of $2.1 billion. Going forward, our goal is to maintain profitability, control costs, and continue investing in targeted high growth markets that will give shareholders the best rate of return.”

For its fourth quarter outlook, the company expects sequential sales to decline by as much as 10%. Gross margins also may decline around 5 percentage points, due to lower factory utilization. These factors may result in earnings of 3 to 5 cents per share.

March 8, 2001–Santa Clara, California–Intel Corp. today announced that its researchers have developed and delivered the first industry-standard format photomasks for extreme ultraviolet (EUV) lithography. This marks a significant milestone in the demonstration of EUV as the next generation lithography standard for the semiconductor industry.

Creating high-quality masks has been one of the fundamental challenges in the demonstration of EUV lithography. EUV masks differ from standard masks in several respects. Standard masks used today in IC manufacturing are designed to transmit light. Deep ultraviolet (DUV) light passes through conventional masks like light through a photonegative. EUV light, on the other hand, is absorbed in the atmosphere and by most materials. Therefore, EUV masks must reflect rather than transmit light. To achieve this, a special low thermal expansion substrate is coated with multiple layers of ultra-thin silicon and molybdenum using a novel fabrication process developed by the EUV Limited Liability Corp. (EUV LLC)–a consortium of semiconductor companies that includes Intel, Motorola, AMD, Micron, and Infineon. This special substrate creates a highly reflective mirror, which is tuned to match the frequency of the EUV exposure light. Patterns are then created on these special “mask blanks.”

Intel researchers have demonstrated that these new masks can be created using an extension of their existing mask-making technology, and with the current industry standard format. In particular, the Intel researchers demonstrated a new low temperature mask process to prevent intermixing of the multilayer reflector. In addition, Intel used a proprietary patterning process to demonstrate line widths 30% smaller than the most advanced masks in manufacturing today. The EUV masks delivered to the EUV LLC will print a minimum feature size of 50nm. Previously, both Intel and Motorola, as part of the EUV LLC, demonstrated the ability to make a mask in a format not standard within the industry today.

“Intel and its EUV LLC partners view EUV as the emerging next-generation lithography standard for the industry,” says Dr. Chiang Yang, director of Intel Mask Operations. “These masks help to ensure the continued progress of the EUV program, and demonstrate a lithography capability that can extend four generations beyond Intel’s current 0.13-micron process generation.”

These masks will be used by the EUV LLC to demonstrate the EUV process on the recently completed engineering test stand (prototype EUV machine). The EUV LLC member companies are funding 100% of the development of EUV lithography technology at the EUV Virtual National Laboratory (VNL)–combining the efforts of three U.S. Department of Energy laboratories (Lawrence Berkeley National Laboratory, Lawrence Livermore National Laboratory and Sandia National Laboratories). The charter of the EUV LLC is to develop and demonstrate EUV technology as a commercially viable technology for the next generation of lithography.

Moore’s Law scaling will continue on silicon wafers through the end of the decade using EUV lithography. Intel expects that the first EUV beta tools will be available by 2003 and manufacturing tools by 2005, with EUV becoming the dominant high volume production technology before the end of the decade.

CHESTERFIELD, MO — PortaFab Corp., a manufacturer of modular in-plant building systems and cleanroom wall systems, has acquired Henges Manufacturing product lines.

The acquisition allows PortaFab to manufacture both industrial mezzanine structure and modular building systems.

“The opportunity to acquire the Henges mezzanine manufacturing capabilities, as well as their key mezzanine management people fits very well into our growth strategy of becoming a single source for industrial in-plant solutions,” said Wayne McGee, president of PortaFab. “Our recent acquisitions have positioned PortaFab to be a leader in the market for pre-engineered technical building systems used in the fastest growing segments of the industrial market.”

Portafab has been in business for more than 25 years and has installed products in a variety of manufacturing facilities, including industrial plants, distribution facilities and high-tech cleanroom environments.

March 8, 2001–Fremont, California–Chartered Semiconductor Manufacturing and Virage Logic Corp. have announced efforts to develop Virage Logic’s Custom-Touch ASAP embedded memory compilers for Chartered’s all-copper, low-k dielectric, 0.13-micron “communications-smart” manufacturing process. The agreement provides chip designers using the new Chartered process with enhanced performance and accuracy for designs containing embedded memory.

Chartered’s communications-smart technology strategy, which is tuned to the needs of the high-growth and technically demanding communications segments of the electronics industry, requires an application-specific approach to dealing with memory-intensive chip designs typical of today’s high-speed and mobile communications products. Virage Logic’s ASAP embedded memory is optimized for density, speed, and low power. The companies’ relationship will enable Chartered’s customers to gain access to Virage Logic’s offerings, which are intended to provide improvements aimed at enhanced reliability and manufacturability.

In order to achieve the highest level of system reliability and to keep power consumption in the idle state as low as possible to extend battery life, Virage Logic has made several architectural improvements to minimize gate leakage current and to keep idle power consumption under check. For instance, Virage Logic has designed more robust memories with detailed layout guidelines. In addition, the company has included proprietary technology that minimizes the possibility of data corruption through the addition of sense amplifiers that operate at the lower voltages typical of the 0.13-micron process.

“Chartered was the first foundry to work with Virage Logic, and we remain committed to working with them as we advance our process technology,” says Michael Buehler-Garcia, vice president of marketing and worldwide EDA at Chartered. “The production-proven and reliable memory solutions they offer are of great benefit to our customers who value the efficiency and reliability of the Virage Logic family of embedded memories.”

“Chartered is a key partner for us and their communications-smart processes are a valuable way for us to reach important customers of our technology. The close working relationship we enjoy with their teams has allowed us to develop critical solutions for our mutual customers,” says Vin Ratford, vice president of marketing at Virage Logic. “We are pleased to be able to continue the progress we’ve achieved with earlier processes, and look forward to defining new and improved approaches in the future.”

Chartered, which has an extensive network of electronic design automation (EDA) and intellectual property (IP) partners, has reached an agreement with Virage Logic to jointly define a memory solution based on mutual customer input. These solutions are designed to consider such issues as redundancy and optimized core, bit-cell sizes. Previous generations of the Virage Logic compilers have been used successfully for designs manufactured with Chartered’s 0.35-micron through 0.18-micron processes.

Within the ASAP compiler family, Virage Logic has the following compilers available in the Chartered 0.13 micron process: 1- and 2-port register files, 1-port high-density SRAM and dual port high-density SRAM. The Chartered 0.13 micron design kit for early adopters is expected to be available in the first quarter of 2001, and target availability for silicon-validated compilers from Virage Logic is the third quarter of 2001.

March 8, 2001–San Jose, California–The critical battle for the future of DRAM technology is being waged in the PC memory arena between DDR DRAM and RDRAM, but San Jose, CA-based market research firm Gartner Dataquest cautions not to expect to see an end to the dispute this year.

Microprocessors with clock speeds measured in GHz are expected to be the norm in the future. Increasing clock speeds have been driven by the demands of the PC, which accounted for about 75% of the DRAM market in 2000, and enabled by advances in semiconductor design and manufacturing. Memory buses cannot supply data fast enough for these new microprocessors, which require data transfer rates of 1.6GB/sec. and higher.

“While microprocessor vendors have continued to increase microprocessor performance, access time to data held in a system main memory has struggled to keep pace, creating a bottleneck to higher system performance,” says Richard Gordon, principal analyst with Gartner Dataquest’s worldwide semiconductors group. “This data transfer rate, or bandwidth, shortfall has led to the development of new DRAM technologies such as RDRAm and DDR DRAM.”

Intel and AMD have been the leading PC microprocessor vendors, reports Gartner Dataquest, but AMD has stopped relying on Intel to provide a lead and is following its own path in support of DDR DRAM.

“Through DDR DRAM, DRAM vendors have seized the only chance they have to keep control of the DRAM technology roadmap, and to avoid the ignominy of becoming little more than silicon foundries for Intel and Rambus,” Gordon says.

To avoid the recurrence of this technology transition debacle, Gartner Dataquest analysts are suggesting that DRAM vendors should make more of an effort to form an industry-wide DRAM alliance–which must include AMD and Intel–to develop a credible technology roadmap. The alliance should strive for transparency between participants to avoid conflict and the possibility of damaging legal action.

“The next couple of years could see a highly fragmented DRAM market in technology terms. The year 2001 is likely to see shortages occur, owing to product-mix issues, so DRAM vendors must plan for flexibility in their strategy for wafer starts,” says Andrew Norwood, senior analyst with Gartner Dataquest’s worldwide semiconductors group. “DRAM vendors should maintain equal support for both DDR DRAM and RDRAM, and be prepared to ramp up volume production for whichever technology the market adopts.”