03/30/2011 

Mechanical stresses can prevent successful implementation of 3D packaging technologies, says Larry Smith, SEMATECH. He argues for a DFM-like solution to identify and manage stress on thinned and stacked die in 3D ICs. To complicate matters, foundries, OSATs, and memory suppliers could inflict different stresses on the die, and the whole industry is too new at 3D packaging to present concrete answers.

03/29/2011 

Xradia has unveiled its latest micro computed tomography (CT) 3D X-ray imaging system, the VersaXRM. Kevin Fahey, PhD, VP of marketing at Xradia, discusses how the new platform uses geometrical magnification in tandem with an X-ray microscope.

03/28/2011 

Tabula will use the new capital to accelerate production of their 3PLD ABAX product family, expand customer and partner support infrastructures, and further next-generation product development in the rapidly growing programmable logic sector.

03/25/2011 

Sonix Inc., scanning acoustic microscope designer and manufacturer, introduced its Stacked Die Imaging (SDI) enhancement, which effectively inspects for defects in semiconductor stacked die and wafer level packages (WLP) by selectively increasing the ultrasonic signal gain for deeper interfaces of interest.

03/22/2011 

Dr. Phil Garrou reports on several talks and trends of note from the recent IMAPS meeting and Device Packaging Conference: the readiness of 3D IC toolsets, what's holding back Cu bonding; and rumors of interposers failing thermal tests.

03/21/2011 

Victor Moroz discusses the strong but doable effects of stress on TSVs. TSV stress ranges are comparable to the size of the TSV, and analog behaves differently than digital. Synopsys recently presented results (part of a collaboration with imec) at a SEMATECH event.

03/21/2011 

CEA-Leti and IPDiA have formed a common lab to capitalize on their complementary expertise in miniaturization and 3D integration on silicon. The common lab will develop very high-end passive components that will resist harsh environments, functional sub-mounts for LEDs, and assembly technologies.

03/18/2011 

At the recent CeBIT Fair in Hanover Germany, IBM announced that its 3D technology to appear in its Power8 processor by 2013 will incorporate microchannel cooling.

03/17/2011 

Applied Materials Inc. (AMAT) introduced the Applied Centura Conforma, with conformal plasma doping (CPD) targeted for 22nm and beyond logic and memory chips. The technology replaces ion beam implantation for conformal doping of complex 3D structures.

03/15/2011 

TeraView and HELIOS are partnering to improve semiconductor package failure analysis using terahertz technology. The technology was originally developed with Intel and isolates faults in advanced 3D semiconductor packages.

03/09/2011 

SEMATECH experts reported new breakthroughs in wafer bonding at the 7th Annual Device Packaging Conference (DPC), March 7-10 in Scottsdale, AZ. Low-temp die tacking has yielded faster die-to-wafer integration.

03/09/2011 

Hynix Semiconductor Inc., DRAM and flash memory supplier, joined SEMATECH's 3D Interconnect program at CNSE's Albany NanoTech Complex to address industry infrastructure and technology gaps in materials, equipment, integration and product-related issues for high-volume adoption of through silicon vias (TSV).

03/08/2011 

Optomec Aerosol Jet product manager Mike O’Reilly will give a presentation titled "Aerosol Jet Printing as an Alternative to Wire Bond and TSV Technology for 3D Interconnect Applications" at the IMAPS Device Packaging Conference on March 9.

03/03/2011 

Cascade Microtech Inc. (NASDAQ: CSCD) and imec entered into a collaborative research partnership for testing and characterization of 3D integrated circuit (IC) test structures. Imec will work closely with Cascade Microtech to develop test methods and methodologies for emerging 3D through silicon via (TSV) structures, and to develop global standards.

03/03/2011 

As it developed an improved FPGA technology, the NuPGA team discovered a path for practical monolithic 3D ICs. MonolithIC 3D changed its strategy to focus on monolithic 3D IC technology as a pure IP innovator organization.

02/27/2011 

Weeks after announcing a 40nm 8GB DDR3 memory with 3D through-silicon vias (TSV), Samsung is showing a wide I/O 1GB DRAM also utilizing 3D TSVs, targeting mobile applications.

02/23/2011 

As gold becomes more expensive, copper wire bonding becomes more appealing for chip packaging. Reverse bonding, fine-pitch bonding, looping, second bonds, and other technologies are ramping on roadmaps, according to Kulicke & Soffa (K&S).

02/18/2011 

Jamal Izadian, co-founder & president of RFCONNEXT, makes the case for shaped membrane transmission lines (SMTL) for use in high-speed 3D packaging applications. SMTL supports and improves flip-chip, micro-bumping, wafer thinning, system-in-package (SiP), package-on-package (PoP), and other packaging processes by extending the bandwidth and high-speed limits of these technologies.

02/09/2011 

SPP Process Technology Systems (SPTS) received a follow-on purchase order from CEA-Leti for its Sigma fxP PVD system. The 300mm system will be used for advanced TSV development at Leti's new 300mm fab extension in Grenoble.

02/08/2011 

ElectroIQ caught up with Suresh Ramalingam, director of advanced package design and development at Xilinx, at the January MEPTEC luncheon, where he gave a presentation on the company's stacked silicon interconnect technology. In an interview with Debra Vogler, Ramalingam discusses SSIT in relation to die stacking and TSV.