07/13/2010 

SEMATECH and Fraunhofer IZFP hosted a follow-up meeting in conjunction with SEMICON West (Tuesday, July 13) to evaluate a design-for-manufacturing (DFM) approach to managing stress in 3D interconnects, and to drive consensus and support for these techniques across the industry.

07/13/2010 

This report from Research and Markets covers new and established technologies for embedded package integration. Benefits of embedded package integration include miniaturization, improvement of electrical and thermal performance, cost reduction and simplification of logistic for OEMs.  

07/13/2010 

In this video, Matt Nowak, Qualcomm, talks about his keynote at ASMC on through silicon technologies for stacking die in advanced packaging applications.

07/12/2010 

Alchimer S.A., a provider of nanometric deposition technology for through-silicon vias (TSV), semiconductor interconnects, and other electronic applications, announced that Panasonic Corporation (NYSE: PC) has become an equity investor in the company.

07/08/2010 

Lasertec joined SEMATECH’s 3D Interconnect program to develop robust, cost-effective process metrology technology solutions for readying high-volume via-mid through silicon via (TSV) manufacturing. This article includes a video interview with SEMATECH about the partnership.

06/22/2010 

Elpida Memory and Taiwanese chip firms Powertech Technology Inc. (PTI) and United Microelectronics Corp. (UMC) are banding together to push 3D IC integration for advanced semiconductor processes.

06/17/2010 

Presenting at the VLSI Symposium, Toshiba says it has developed a silicon nanowire transistor with vastly improved on-current levels, targeting 16nm and beyond system LSIs.

06/04/2010 

In a SiP chip stack, space constraints can lead to large parasitic inductances in the packaging. Planarity, processing, high-temperature exposure, and other factors also present challenges. A new anisotropic conductive adhesive technology could enable low-cost flexible packaging via a multi-layer particle structure. S. Manian Ramkumar, Ph.D., RIT, reviews the adhesives benefits to various levels of electronics interconnect.

05/20/2010 

High-density through-silicon stacking (TSS) shows promise for very high-volume applications, but work still needs to be done to "tame" key issues in manufacturing, improve costs, and smooth out the supply-chain, said Matt Nowak, director of engineering in Qualcomm's VLSI technology group, in a presentation at The ConFab in Las Vegas.

05/20/2010 

Tony Flaim, CTO at Brewer Science, describes the work the company is doing to enable 3D integration. While progress is moving forward, he tells SST's Debra Vogler that end users are still somewhat unsettled in their choices of manufacturing technologies.

04/27/2010 

Imbedded component/die technology is a method of imbedding active and passives into cavities within a multi-layer PCB to decrease the surface area required to implement the circuit design and increase the robustness of the overall assembly. Casey H. Cooper, STI, discusses the design methodology, packaging processes, and test data gathered during imbedded die/component packaging implementation in a mixed-signal prototype. The prototype was subjected to reliability testing and demonstrated in a test flight.

03/29/2010 

Kedar Sapre from Applied Materials talks with SST about the company's new Producer InVia CVD system targeting via-first/via-middle through silicon vias (TSV) for 3D IC packaging.

03/09/2010 

Novellus Systems (NASDAQ: NVLS) created an advanced copper barrier-seed physical vapor deposition (PVD) process for the emerging through-silicon-via (TSV) packaging market. The process uses Novellus’ established INOVA platform with patented hollow cathode magnetron (HCM) technology to produce highly conformal copper seed films that are reportedly four times thinner than the conventional PVD seed approaches used for TSV applications. Novellus announced that the HCM TSV process delivers excellent sidewall and bottom coverage, and enables void-free copper fill during the subsequent TSV electroplating step.

03/03/2010 

Allvia says it has integrated embedded capacitors on silicon interposers, a key interface between silicon devices and organic substrates, achieving >1500nF/cm² capacitance.

03/01/2010 

Given the advantages and technical feasibility of through-silicon vias (TSV), the major focus now is on the manufacturability and integration of all the different building blocks for TSVs and 3D interconnects. EV Group's Thorsten Matthias et al. review advances in lithography, thin wafer processing, and wafer bonding, and the integration of all these process steps.

02/08/2010 

In a deal that will generate economical new process options for the 3D integration market, Alchimer S.A., a provider of nanometric deposition technology for semiconductor interconnects and through-silicon vias (TSV), and KPM Tech Co. Ltd., a manufacturer of plating materials and systems, announced a multi-level collaboration that gives KPM Tech exclusive rights to produce chemicals in Korea for Alchimer’s technology. The agreement also includes the manufacture of various configurations of wet processing tools to support the Alchimer TSV platform.

01/22/2010 

The Surface Mount Technology Association (SMTA) will host two 90-minute online sessions with Bob Willis, ASKbobwillis.com, on package-on-package (PoP) applications and implementation. The Webtorials will take place February 4 and February 11, 2010 from 1:00 to 2:30 pm EST.

01/15/2010 

Allvia says it has completed integration and full reliability testing of a silicon interposer between a semiconductor die and an organic or ceramic substrate.

01/08/2010 

Fabless giant Qualcomm has made two deals to reserve leading-edge semiconductor manufacturing capacity: one with longtime partner TSMC, and the other with upstart GlobalFoundries.

12/22/2009 

Nagesh Vodrahalli, VP of technology & manufacturing at Allvia, discussed some of the issues in developing through-silicon via (TSV) technologies with Solid State Technology/Advanced Packaging in conjunction with his presentation at the recent 3-D Architectures for Semiconductor Integration and Packaging conference.