02/24/2009  Applied Materials, Inc. has joined the international EMC-3D semiconductor equipment and materials consortium, which focuses on 3D chip stacking and MEMS integration.

02/23/2009  L

02/19/2009  By Gail Flower, Editor-at-Large This article provides a broad review of the issues affecting socket usage: lead-free challenges, finer pitch adjustments, cost control, standardization, practical customer concerns, and improvements needed for 3D packages and other innovations on the horizon. Through conversations with industry experts, we explore a few common themes from this year's Burn-in and Test Socket Workshop (March 8 -11, 2009) in Mesa, AZ.

02/17/2009  The j360 Silicon PathFinder 3D Platform from Javelin Design Automations supports 3D stacked IC design using through silicon vias (TSV). The design tool reportedly extends the Javelin PathFinding methodology and j360 Silicon PathFinder platform to support virtual chip design for co-optimization of system design and 3D interconnect-packaging technologies

02/17/2009  by Fran

02/16/2009  In a bid to expand applications for 3D packaging, NEC has developed a 3D chip-stacked flexible memory to support large-scale high-performance systems-on-chip (SoC).

02/16/2009  By Yann Guillou, ST-Ericsson Wireless and Eric Saugier, STMicroelectronics
3D Integration, through silicon via (TSV), 3D packaging, 3D TSV, 3D system-in-package (SiP), 3D system-on-chip (SoC), and 3D system-on-package (SoP) are some of the hottest topics presented at conferences or read about in popular tech magazines. All of these are definitively trendy terms; no one would argue to the contrary. So it's about time to take a serious look at 3D in its broadest meaning.

02/05/2009  it's just a matter of when. There are three main components to 3D IC technology: through silicon via (TSV) formation; thinning; and bonding. The numerous process flows that exist for 3D integration are all related to the sequence in which these three processes occur.

01/29/2009  Dai Nippon Printing Co. Ltd. (DNP) developed a package leadframe to slim down the semiconductor package mounted on electronic devices. The leadframe enables known good die (KGD) semiconductor packaging with a thickness of 0.15 mm, using precision plating processes.

01/13/2009  Smart Equipment Technology (S.E.T.), a wholly-owned subsidiary of Replisaurus Technologies, announced a collaboration with IMEC to develop die pick-and-place and bonding processes for 3D chip integration using S.E.T.'s flip chip bonder equipment. As part of the collaboration, S.E.T. will join IMEC's Industrial Affiliation Program (IIAP) on 3D integration.

01/07/2009  In response to a call for localized support and increased demand of 3D IC process development in Asia Pacific, EV Group (EVG) and Brewer Science, Inc. have set out to outfit an ultra-thin wafer bonding lab in Taiwan. To this end, the companies announced the installation of an EVG 500 series wafer-bonding system at Brewer Science's Taiwan applications lab in Hsinchu Science Park.

12/05/2008  The 3D interconnection chip carrier from Microcertec S.A.S 3-D combines precision-grinding of ceramics with thin-film metallization and laser micromachining to create a 3D package option for chips and ICs.

12/02/2008  On November 17

12/01/2008  December 1, 2008: Applied Materials Inc. says it is leading a major effort to enable the widespread adoption of through-silicon vias (TSVs) for vertically stacking integrated circuits (ICs) to boost chip performance and functionality, working internally and with other equipment suppliers to develop an integrated, high-performance on-wafer process flow to lower costs, reduce risk, and accelerate time-to-market for customers.

12/01/2008  Sizing up a TSV market beyond the early adopters, Applied Materials is collaborating with material and equipment suppliers (and others) to ensure the full readiness of TSV implementation. AMAT execs update SST on the firm's TSV efforts, including a new TSV process sequence developed with Semitool and a new etch tool.

11/18/2008  By Fran

11/17/2008  By Gail Flower, Editor-in-Chief
This year's IMAPS International Symposium had great international participation, good attendance and excellent presentations from keynoters to the technologically cutting-edge educational papers. It was election day when the IMAPS conference began, and by the second day of the conference, a new president entered the picture. Therefore, the first day proceeded without a rush of attendees as expected, but the second perked up with lively conversation.

11/17/2008  The WDF 12DP is designed to address increased demand for probing ultrathin and diced wafers, and wafer-level testing of chip-scale and wafer-level packaging, stacked, and 3D technologies, as well as KGD testing of ultra-hin wafers, singulated wafers, and strips on a dicing frame.

10/31/2008  By Paul Collander, Poltronics, Inc. At the recent Advanced Packaging Conference at SEMICON Europe in Stuttgart, Germany, (October 7-9, 2008) Fran

10/30/2008  October 30, 2008: SEMATECH and the College of Nanoscale Science and Engineering (CNSE) at the U. at Albany will use TEL's Telius SP UD system in a 300mm 3D R&D center.