Author Archives: psinger

TechInsights (Ottawa, Canada), announced its new Power Semiconductor subscription, a technical intelligence service that provides regular, succinct analysis of emerging power semiconductor products as they enter mass production in high-volume applications. In addition, the company is offering custom analysis services for power semiconductor products.

“The semiconductor industry is developing smaller, more efficient power process technologies, using Silicon Carbide and Gallium Nitride,” said Mike McLean, SVP of Technology at TechInsights. “Our new Power Semiconductor subscription service is ideal for market leaders seeking to design roadmaps based on hard facts about cutting-edge Gallium Nitride, Silicon Carbide, and Silicon devices.”

The Power Semiconductor Subscription service includes:

  • 10 summary reports and hundreds of high-resolution supporting images
  • Analysis coverage including device metrics, package x-rays, die photos, SEM plan-view images and cross-sectional SEM images, cross-sectional TEM images and material analysis
  • TechInsights tri-annual analyst briefing
  • An annual patent landscape summary
  • Annual analyst workshop
  • Real time updates provide access to work in progress as well as exploratory work on more than 30 devices

TechInsights’ primary focus for the 2019 Power Semiconductor subscription is consumer applications of Gallium Nitride technology, specifically where it has the potential to replace super junction MOSFET devices in low form factor applications. Additionally, the company plans to monitor Silicon Carbide technologies as they compete with IGBT, and innovations in the mature Silicon technology that allow it to compete with Gallium Nitride and Silicon Carbide. The analysis will include technology and products from more than 20 major companies driving innovation using these technologies.

OEM Group has launched the P5000:CS automated single wafer cluster tool for the compound semiconductor market.  As the exclusive licensed manufacturer of the Applied Materials P5000, OEM Group’s P5000:CS was designed and developed specifically to handle and process 75mm, 100mm, and 150mm compound semiconductor substrates such as Gallium Arsenide (GaAs), Silicon Carbide (SiC), Sapphire, Germanium (Ge), Indium Phosphide (InP), and Gallium Nitride (GaN).

“Prior to the release of the P5000:CS, customers in the compound semiconductor market had very few options for Etch and CVD cluster tools” said John Almerico, Production Manager Etch and CVD of OEM Group.  “Their choices were limited to boutique custom built, unproven, and expensive systems.  With the P5000:CS, it’s the first time an industry proven, single wafer cluster tool with high volume capability has been made available to the compound semiconductor industry.”

The P5000:CS features a proprietary Bi-Polar Electrostatic Chuck for single wafer processing temperature control best suited for SiC, GaAs, and Sapphire etch applications.  The option for a proprietary Wafer Orienter utilizing special software and sensors specifically tuned to do edge detection on transparent wafers has been added.  An Advanced Spectrometer Endpoint Detection system is built into the chamber to diagnose, analyze, and “fingerprint” any kind of plasma present on the wafer.

In 2016, SEMI reported the total compound semiconductor market was estimated at $24B and expected to almost double at a CAGR of ~13% to ~$44B in 2020.  “With the projected growth in the industry”, said Almerico, “we developed the P5000:CS platform to address the special high volume production needs and support the market at an affordable price”.

About OEM Group, Inc.

OEM Group is a global manufacturer of new and remanufactured semiconductor capital equipment and upgrades focused on innovative and sustaining solutions for emerging markets. Our proven portfolio consists of exclusive intellectual property acquired from leading semiconductor brands, including: P5000, Tegal™ Etch, Sputtered Films® Endeavor™, MRC® Eclipse™, AGHeatpulse®, Varian® Sunset™, Lam® AutoEtch™ and SEMITOOL® Manual Batch, Automated Batch and Single Wafer Equinox™. In addition to the LEGENDS™ lines, OEM offers an Applications Development lab for wet processing and Foundry services for piezoelectric AlN films. For more information, please visit

By Pete Singer, Editor-in-Chief

A new roadmap, the Heterogeneous Integration Technology Roadmap for Semiconductors (HITRS), aims to integrate fast optical communication made possible with photonic devices with the digital crunching capabilities of CMOS.

The roadmap, announced publicly for the first time at The ConFab in June, is sponsored by IEEE Components, Packaging and Manufacturing Technology Society (CPMT), SEMI and the IEEE Electron Devices Society (EDS).

Speaking at The ConFab, Bill Bottoms, chairman and CEO of 3MT Solutions, said there were four significant issues driving change in the electronics industry that in turn drove the need for the new HITRS roadmap: 1) The approaching end of Moore’s Law scaling of CMOS, 2) Migration of data, logic and applications to the Cloud, 3) The rise of the internet of things, and 4) Consumerization of data and data access.

“CMOS scaling is reaching the end of its economic viability and, for several applications, it has already arrived. At the same time, we have migration of data, logic and applications to the cloud. That’s placing enormous pressures on the capacity of the network that can’t be met with what we’re doing today, and we have the rise of the Internet of Things,” he said. The consumerization of data and data access is something that people haven’t focused on at all, he said. “If we are not successful in doing that, the rate of growth and economic viability of our industry is going to be threatened,” Bottoms said.

These four driving forces present requirements that cannot be satisfied through scaling CMOS. “We have to have lower power, lower latency, lower cost with higher performance every time we bring out a new product or it won’t be successful,” Bottoms said. “How do we do that? The only vector that’s available to us today is to bring all of the electronics much closer together and then the distance between those system nodes has to be connected with photonics so that it operates at the speed of light and doesn’t consume much power. The only way to do this is to use heterogeneous integration and to incorporate 3D complex System-in-Package (SiP) architectures.

The HITRS is focused on exactly that, including integrating single-chip and multi­chip packaging (including substrates); integrated photonics, integrated power devices, MEMS, RF and analog mixed signal, and plasmonics. “Plasmonics have the ability to confine photonic energy to a space much smaller than wavelength,” Bottoms said. More information on the HITRS can be found at:

Bottoms said much of the technology exists today at the component level, but the challenge lies in integration. He noted today’s capabilities (Figure 1) include Interconnection (flip-chip and wire bond), antenna, molding, SMT (passives, components, connectors), passives/integrated passive devices, wafer pumping/WLP, photonics layer, embedded technology, die/package stacking and mechanical assembly (laser welding, flex bending).

Building blocks for integrated photonics.

Building blocks for integrated photonics.

“We have a large number of components, all of which have been built, proven, characterized and in no case have we yet integrated them all. We’ve integrated more and more of them, and we expect to accelerate that in the next few years,” he said.

He also said that all the components exist to make very complex photonic integrated circuits, including beam splitters, microbumps, photodetectors, optical modulators, optical buses, laser sources, active wavelength locking devices, ring modulators, waveguides, WDM (wavelength division multiplexers) filters and fiber couplers. “They all exist, they all can be built with processes that are available to us in the CMOS fab, but in no place have they been integrated into a single device. Getting that done in an effective way is one of the objectives of the HITRS roadmap,” Bottoms explained.

He also pointed to the potential of new device types (Figure 2) that are coming (or already here), including carbon nanotube memory, MEMS photonic switches, spin torque devices, plasmons in CNT waveguides, GaAs nanowire lasers (grown on silicon with waveguides embedded), and plasmonic emission sources (that employ quantum dots and plasmons).

New device types are coming.

New device types are coming.

The HITRS committee will meet for a workshop at SEMICON West in July.


January 6, 2016

Semiconductor manufacturing facilities or wafer “fabs” are huge affairs costing billions of dollars. Most of the action takes place in the cleanroom which houses the manufacturing equipment, such as lithography, chemical vapor deposition, etch, ion implant, photoresist track systems, sputtering, annealing tools and many others. Large fabs have upward of 600 different tools, often multiple tools fo the same type to meet overall throughput targets (tens of thousands of wafers per month for large fabs).

In 2015, Samsung announced what is said to be the world’s most expensive semiconductor fabrication plant, at over $14 billion. The new plant will be finished in 2017, according to Samsung, and is reported to almost as big–at 31 million square feet plant–as Samsung’s next two biggest fabs put together at Giheung and Hwaseong South Korea. The new plant is reported to employ about 150,000 people and to produce about $40 billion dollars per year in chip revenue
Wafers are typically transported through the fab with an automated rail system (although hand transportation and loading is not uncommon). Most fabs transport the wafers in a FOUP (front opening unified pod), which is essentially an expensive plastic box.

Fabs require an intricate infrastructure to supply chemicals, materials and gases to the process tool. Air handlers, ionization systems and HEPA filters are used to clean the air in the cleanroom. Support equipment, such as vacuum pumps and gas abatement tools (used to remove process byproducts before the air is released into the atmosphere, for example) are typically housed in a sub-floor beneath the tools.

Fabs also require sophisticated MES (Manufacturing Execution Software) systems to keep track of the “recipes” for the process tools, track lots of wafers through the fab (and manage “hot” lots of wafers that need to be expedited) and keep track of materials.

Another concern is power. A typical wafer fab uses as much energy as 10,000 homes. Energy bills run as high as $25 million annually. New fabs use LEED principles to reduce costs.

Automated Test Equipment

January 6, 2016

Automatic or automated test equipment (ATE) is a system that performs tests on a device, known as the Device Under Test (DUT), using automation to quickly perform measurements and evaluate the test results. An ATE can be a simple computer controlled digital multimeter, or, more often, a complicated system containing dozens of complex test instruments (real or simulated electronic test equipment) capable of automatically testing and diagnosing faults in complex ICs.

The ATE/semiconductor test segment is comprised of six distinct types of testers:
• Analog/Linear Test
• Mixed Signal Test
• RF/Microwave Test
• Digital/Logic Test
• Memory Test
• System-on-Chip (SOC) Test

ATE systems interface with packaged chips through a separate machine called an IC handler. Tested ICs are then “binned” depending on their performance (higher performance devices are sold at a premium). Alternatively, ATE systems can test unpackaged chip directly on the wafer through a wafer prober and probe card designed to touch on the IO/bonding pads of the device. In this way, the cost of packaging bad chips is avoided.

The ATE market is driven by semiconductor chip volumes. As chip volumes steadily increase, the demand for chip testers also grows.

Given the sharp increase in usage of memory devices in end products such as home appliances, cell phones, and automobiles, it’s no surprise that the memory tester sub-segment is the largest in the ATE space.

According to a research report by Radiant Insights, Inc., the global ATE mrket is expected to be valued at $4.48 billion by 2020, as per Increasing design complexity coupled with need for effective testing is expected to drive the global automated test equipment market demand.

Increasing need for optimizing power management in order to ensure longer battery life is likely to favor the growth prospects. However, dependency on semiconductor chips is likely challenge industry participants. Non-memory products were the leading segment, valued at $2,867.5 million in 2013, according to the report. Expansion of consumer electronics, increasing automotive demand and growing number of microcontroller-based applications are factors likely to promote its demand.

Memory products accounted for 21.21% of the overall revenue in 2013, growing at an estimated CAGR of 1.7% from 2014 to 2020. The cyclical variations in growth rates than non-memory semiconductors have resulted in gaining popularity among various applications.

Additional Reading:

Business is good for vendors of test and inspection/metrology equipment


January 6, 2016

The process of creating a pattern on a wafer is known as lithography. Typically, light is shone through a mask onto a photoresist that coats the wafer. After exposure, the photoresist is “developed,” which removes the exposed part of the resist (or the unexposed resist if it is negative resist). A photoresist coat/bake/develop system — often called a “track system” is typically connected directly to the wafer exposure tool or wafer “stepper.”

The exposed wafer is then etched, where the photoresist acts as a barrier to the etching chemicals or reaction ions. The photoresist is then removed by stripping or “ashing.” In complex integrated circuits, a modern CMOS wafer will go through the photolithographic cycle up to 50 times, making lithography one most critical process step.

Increasingly smaller wavelengths of light have been used to create smaller dimensions. Complex mask designs have also evolved, such as optical proximity correction (OPC), to correct for optical effects. Mask-source optimization techniques have also been developed to correct for variations in the source and on the wafer.

A push to extreme ultra-violet (EUV) lithography has been under way for a decade or more, led by ASML Lithography. Alternatives have also been research and developed, including nano-imprint lithography (NIL), which uses stencils and multi e-beam (MEB) lithography, which uses a large bank of individually controlled electron beams to expose the wafer directly (no mask required). More recently, an interesting approach called directed self-assembly (DSA) has been studied, which enables very small dimensions. DSA uses a guide structure on the wafer and polymer-based chemicals to create regular lines with very small dimensions.

Check out our Lithography Topic Center for regular updates.

Additional Reading:

Feed-forward overlay control in lithography processes using CGS

Advanced lithography and electroplating approach to form high-aspect ratio copper pillars

CVD Source Materials

December 17, 2015

Reaction materials for chemical vapor deposition (CVD) and atomic layer deposition (ALD) are typically delivered into the chamber in a gaseous form. CVD polycrystalline silicon, for example, is deposited from trichlorosilane (SiHCl3) or silane (SiH4), using the following reactions:

SiH3Cl → Si + H2 + HCl
SiH4 → Si + 2 H2

This reaction is usually performed in LPCVD systems, with either pure silane feedstock, or a solution of silane with 70–80% nitrogen. Polysilicon may be grown directly with doping, if gases such as phosphine, arsine or diborane are added to the CVD chamber.

Silicon dioxide (usually called simply “oxide” in the semiconductor industry) may be deposited by several different processes. Common source gases include silane and oxygen, dichlorosilane (SiCl2H2) and nitrous oxide (N2O), or tetraethylorthosilicate (TEOS; Si(OC2H5)4). The reactions are as follows:

SiH4 + O2 → SiO2 + 2 H2
SiCl2H2 + 2 N2O → SiO2 + 2 N2 + 2 HCl
Si(OC2H5)4 → SiO2 + byproducts

CVD source materials are typically gases, such as silane and nitrogen, but can also be liquids: There are now a larger variety of liquid sources used in the semiconductor, FPD and PV manufacturing processes.

CVD Sources

The graph above shows the different possible states of matter. There are two ways to get from a liquid to a gaseous state. The first method involves increasing the temperature while holding the pressure steady, as indicated by the arrow with the broken line. This method is commonly used in everyday settings—to boil water and convert it to steam, for example. Heating a liquid takes time, however, which makes rapid vaporization difficult. On the other hand, one can also heat the liquid in advance and then abruptly reduce the pressure, as illustrated by the arrow with the solid line. The pressure in the vaporization section of the injector can be reduced instantaneously, and this makes it possible to vaporize a liquid source instantaneously.

Wafer level packaging (WLP) using fan-out technology is an attractive platform for achieving low-cost low-profile package solutions for smart-phones and tablets, which require cost-effective, high-density interconnects in small form-factor packaging.

It was originally introduced by Infineon in the fall of 2007. Called eWLB, or embedded wafer-level ball grid array technology, it enables all operations to be performed highly parallel at wafer level. In August of 2008, STMicroelectronics, STATS ChipPAC, and Infineon signed an agreement to jointly develop the next-generation eWLB, based on Infineon’s first-generation technology.

Assembled directly on a silicon wafer, the approach is unconstrained by die size, providing the design flexibility to accommodate an unlimited number of interconnects between the package and the application board for maximum connection density, finer line/spacing, improved electrical and thermal performance and small package dimensions to meet the relentless form factor requirements and performance demands of the mobile market.

STATS ChipPAC’s eWLB high volume manufacturing process, for example, today includes automated wafer reconstitution (including wafer-level molding), redistribution using thin film technology, solder ball mount, package singulation and testing. Incoming wafers in both 200mm and 300mm diameters can be supported.

According to a recent report from Yole Développement, the fan-out WLP (FOWLP) market will reach almost $200M in 2015, with 30% CAGR in the coming years. Yole analysts say FOWLP started volume commercialization in 2009/2010 and started promisingly, with an initial push by Intel Mobile. However, it was limited to a narrow range of applications, essentially single die packages for cell phone baseband chips. In 2012 big fabless wireless/mobile players started slowly volume production after qualifying the technology.

Cryogenic Vacuum Pumps

December 16, 2015

Cryopumps are commonly cooled by compressed helium, though they may also use dry ice, liquid nitrogen, or stand-alone versions may include a built-in cryocooler. Baffles are often attached to the cold head to expand the surface area available for condensation, but these also increase the radiative heat uptake of the cryopump. Over time, the surface eventually saturates with condensate and thus the pumping speed gradually drops to zero. It will hold the trapped gases as long as it remains cold, but it will not condense fresh gases from leaks or backstreaming until it is regenerated. Saturation happens very quickly in low vacuums, so cryopumps are usually only used in high or ultrahigh vacuum systems.

The cryopump provides fast, clean pumping of all gases in the 10−3 to 10−9 Torr range. The cryopump operates on the principle that gases can be condensed and held at extremely low vapor pressures, achieving high speeds and throughputs. The cold head consists of a two-stage cold head cylinder (part of the vacuum vessel) and a drive unit displacer assembly. These together produce closed-cycle refrigeration at temperatures that range from 60 to 80K for the first-stage cold station to 10 to 20K for the second-stage cold station, typically.

Regeneration of a cryopump is the process of evaporating the trapped gases. During a regeneration cycle, the cryopump is warmed to room temperature or higher, allowing trapped gases to change from a solid state to a gaseous state and thereby be released from the cryopump through a pressure relief valve into the atmosphere.

Most production equipment utilizing a cryopump have a means to isolate the cryopump from the vacuum chamber so regeneration takes place without exposing the vacuum system to released gasses such as water vapor. Water vapor is the hardest natural element to remove from vacuum chamber walls upon exposure to the atmosphere due to monolayer formation and hydrogen bonding. Adding heat to the dry nitrogen purge-gas will speed the warm-up and reduce the regeneration time.

By Pete Singer, Editor-in-Chief

Austria-based ams AG, formerly known as Austriamicrosystem, announced plans to locate a new 360,000 ft2 fab in upstate New York at the Nano Utica site in Marcy, NY. The fab will be used to manufacture analog devices on 200/300mm wafers. Total buildout at the site, including support buildings and office space, will be close to 600,000ft2.

An artist’s rendering of a semiconductor fab at the Marcy site.

An artist’s rendering of a semiconductor fab at the Marcy site.

This will be the first fab going into the 428 acre Marcy site, which is large enough to accommodate three fabs and an R&D or packaging facility.

Construction of the ams fab is scheduled to begin in spring 2016, with first wafer ramp in the last quarter of 2017.

In what might become the new business model for fabs, the building itself will be publicly owned and leased to ams, which will assume operating costs and most of the costs of the capital equipment. Capital purchases, operating expenses and other investments in the facility over the first 20 years are estimated at more than $2 billion. ams will create and retain more than 700 full time jobs and anticipates the creation of at least 500 additional support jobs from contractors, subcontractors, suppliers, and partners necessary to establish the full ecosystem necessary to enable advanced manufacturing operations.

Fort Schuyler Management (FSMC) will handle the construction, with the goal of turning the fab over to ams in Q2 2017. A key part of N.Y. Governor Andrew Cuomo’s START-UP NY initiative, FSMC is a State University of New York (SUNY Polytechnic Institute) affiliated, private, not-for-profit, 501c(3) corporation that facilitates research and economic development opportunities in support of New York’s emerging nanotechnology and semiconductor clusters.

“If jobs are being created, everything else will take care of itself,” Cuomo said.

Mohawk Valley EDGE President Steve DiMeo said site work has already started. “We’re putting roads in, storm drainage, utilities and we just approved the change order for clearing the land where ams will be located. We’ll be doing some additional site development this fall, and work closely with Fort Schuyler so that they will be in a position to begin construction the early part of next year.”

In a related announcement, GE Global Research said it will expand its New York global operations to the Mohawk Valley, serving as the anchor tenant of the Computer Chip Commercialization Center (QUAD C) on the campus of SUNY Polytechnic Institute’s Colleges of Nanoscale Science and Engineering in Utica. Nearly 500 jobs are expected to be created in the Mohawk Valley in the next five years from SUNY Poly, GE and affiliated corporations and another 350 in the subsequent five years.

These public-private partnerships represent the launch of the next phase of the Governor’s Nano Utica initiative, which now exceeds more than 4,000 projected jobs over the next ten years. Designed to replicate the dramatic success of SUNY Poly’s Nanotech Megaplex in Albany, NANO Utica further cements New York’s international recognition as the preeminent hub for 21st century nanotechnology innovation, education, and economic development.

“This is a transformative moment that will make a difference in peoples’ lives in the Mohawk Valley for generations to come,” said Governor Cuomo. “Over the past few years, we have worked to reverse the negative and invest in Upstate NY – and today we’re taking another huge step forward. With GE and ams joining the Nano Utica initiative, we’re seeing the region’s economy gathering momentum unlike ever before. The Mohawk Valley is beginning an economic revolution around nanotechnology, and I am excited to see the region take off and thrive, both today and in the years ahead.”

Dr. Alain Kaloyeros, President and Chief Executive Officer of SUNY Polytechnic Institute, said, “Today’s announcement by Governor Andrew Cuomo represents a major expansion for Quad-C and the Nano Utica initiative and is a tremendous victory for the Mohawk Valley and the entire State of New York. World renowned partners such as GE Global Research and AMS raise the level of prestige for the entire region and accelerate the development of this international hub for technology and innovation. Governor Cuomo’s pioneering economic development model, coupled with SUNY Poly CNSE’s world class expertise and resources, continues to generate historic investment and job creation throughout the state. We welcome GE and AMS and their leadership teams and look forward to their partnership in the continued growth of Nano Utica.”

ams Chief Operating Officer Dr. Thomas Stockmeier said, “Building a new wafer fab will help us achieve our growth plans and meet the increasing demand for our advanced manufacturing nodes. Our decision to locate the facility in New York was motivated by the highly-skilled workforce, the proximity to esteemed education and research institutions, and the favorable business environment provided by Governor Cuomo and all the public and private partners we are working with on this important project.”

Additionally, ams will collaborate with FSMC and SUNY Poly on a joint development program to support complimentary research, commercialization and workforce training opportunities at SUNY Poly facilities throughout New York State.