Author Archives: psinger

At SEMICON Europa, attendees and exhibitors will delve into the technologies that shape the future of the microtech, nanotech, medtech and cleantech industries. Representing the entire supply chain from materials to electronic systems and services, 35 major European start-ups will participate in the Innovation Village and present their new technologies at SEMICON Europa.  The largest and most important semiconductor event in Europe, SEMICON Europa  will be held 7-9 October in the Grenoble location for the first time. The new three-day Innovation Village program will be the stage for emerging innovators, industry leaders, strategic investors, and venture capitalists to discuss the needs of the industry’s innovation engine. Attendees will gain insights on technology, capital, partnership, and collaboration strategies necessary for mutual success.

Innovation Village consists of a start-up exhibition (7-9 October), Silicon Innovation Forum (7 October) and Innovation Conference (8 October). As part of the Silicon Innovation Forum, all selected start-ups will have the opportunity to “pitch” to investors and SEMICON Europa visitors. The pitch session will be followed by a start-up panel discussion  “Fundraising for the Future Champions of European Electronics,” led by Jean-Pascal Bost of SATT-GIFT with panelists: Jacques Husser (Sigfox), Eric Baissus (Kalray), Serguei Okhonin (ActLight) and Mike Thompson (Hotblock Onboard).

The Innovation Conference, sponsored by Fidal Innovation, will bring together notable names in European innovation to discuss current practices and relevant funding issues facing semiconductor and high-tech start-ups today. Keynote speakers will include Nicolas Leterrier (Schneider Electric) on Innovation Practices and Dan Armbrust (Silicon Catalyst) on Lean Innovation. Christine Vaca (Gate1) will act as the conference chair.

“For the inaugural SEMICON Europa in Grenoble, our team was intent on developing a program that would highlight the strength of the local and the European ecosystems in innovation and new technology,” explains Anne-Marie Dutron, director of the SEMI Grenoble office. “At Innovation Village, visitors will discover the creativity of 35 European start-up companies, presenting their products, partnership and investment opportunities.”

Participating start-ups were chosen by a selection committee which included ten of the most recognizable venture firms in the industry: Applied Ventures LLC, Robert Bosch Venture GmbH, TEL Venture,3M Ventures, CEA Investissement, Samsung Ventures, Air Liquid Electronics, ASTER Capital), VTT Ventures, and  Capital-E.

Start-ups include ActLight (Switzerland), BlinkSight (France), BluWireless Technology (UK), Calao-Systems (France) and Silicon Line (Germany). For more information about Innovation Village, participating start-ups or about the Innovation Conference, please visit the SEMICON Europa website: www.semiconeuropa.org/Segments/InnovationVillage

All events in Innovation Village, including the three-day start-up exhibition, Silicon Innovation Forum and Innovation Conference will be available at no charge for all SEMICON Europa guests and visitors. The event will be co-hosted by SEMI Grenoble and Gate1. The mission of GATE1 is to support the creation of new technology-driven businesses by capitalizing on the proximity of numerous university laboratories and research centers. GATE1 offers programs for technology maturation, business incubation and business acceleration.

Kateeva  announced that it has closed its Series D round with $38 million in financing. The newest participant is Samsung Venture Investment Corporation (SVIC). Existing investors also contributed. They include: Sigma Partners, Spark Capital, Madrone Capital Partners, DBL Investors, New Science Ventures, and VEECO Instruments, Inc.

The company has raised more than $110 million since it was founded in 2008.

Kateeva makes the YIELDjet™ platform — a precision deposition platform that leverages inkjet printing to mass produce flexible and large-size OLED panels. The new funds will be used to support the company’s manufacturing strategy and expand its global sales and support infrastructure. Production systems are currently being built at the company’s facility in Menlo Park, Calif. to fulfill early orders.

The funding news coincides with the 2014 OLEDs World Summit taking place this week in Berkeley, Calif.

“Kateeva is a technology leader and has built a significant business in the OLED space,” said Michael Pachos, Senior Investment Manager at SVIC. “The company has demonstrated both a technical and business vision in driving adoption of OLED displays and lighting, and we look forward to contributing to its progress.”

“We believe that OLEDs on flexible substrates play a major role in the insatiable quest for ultra-durable, high-performance, and unbreakable mobile displays, and Kateeva has proven to hold the keys to a critical industry problem,” said Fahri Diner, Managing Director of Sigma Partners and a member of the Board of Directors of Kateeva. “Moreover, we are very excited about Kateeva’s impressive innovations that are poised to make large-panel OLED televisions finally an affordable reality — perhaps the Holy Grail of the display world. In partnership with SVIC, we’re delighted to offer continued support to Kateeva as they rapidly scale operations to support accelerating demand for OLED manufacturing solutions,” Diner continued.

Kateeva Chief Executive Officer Alain Harrus said: “SVIC’s investment speaks volumes about our technology’s enabling value to world-class OLED producers. It will reinforce our leading position and help serve all our customers better. Also, we appreciate our existing investors for their enduring commitment and trusted guidance. Thanks to their confidence in our technology and execution, mass producing OLEDs will be much smoother for leading display manufacturers.”

By Anand Sundaram, Senior Associate for PwC’s Operations Consulting

Software that controls and powers embedded devices is playing a key role in making possible the highly integrated, multi-functional ‘smart’ devices we take for granted in our daily lives – from the ubiquitous smart phones/tablet to ‘smart’ home appliances and wearable electronics.

F1

Smart Connected Device Unit shipments by Product Category, 2012-2017 (in millions). Source: IDC’s Worldwide Smart Connected Device Tracker Forecast Report, May 2013. Totals may not equal 100% due to rounding.

Despite the wide variety of features and attributes, a few key trends stand out that are common to most  devices:

  • Explosion in device functionality: Many of today’s highly-integrated devices have impressive communication, computing and sensing capabilities, resulting in the convergence of many functions on a single device.
  • Increased focus on customer experience: Today’s embedded devices are not only expected to deliver a rich set of features and performance at an acceptable price point, but are also expected to be aesthetically pleasing and easy-to-use – tangible attributes that directly drive a customer’s perception of value.
  • Increasing speed of innovation: In a dynamic market environment where products are being launched every 12-18 months, companies are trying to keep up with faster time-to-market expectations and driving an increased pace of innovation.

This results in intense competition, constant product category reinvention, and price/cost pressures for OEMs (Original Equipment Manufacturers). However, there is also an impact on the broader value chain, including device makers that design and sell semiconductor chips for these embedded applications. Embedded device OEMs, under tremendous pressure to improve their time-to-market and reduce costs, have begun requiring semiconductor companies to provide not just a chip, but a complete system solution. This is vastly different from the reality of the decades past (figure 2b), where OEMs played the role of system software integrators, requiring System-on-a-Chip (SoC) vendors to provide just the basic, lower-level building blocks.

F2

Embedded Software Model and Work-Split

What does this increased responsibility for embedded software mean for semi device makers?  Should chip makers reluctantly enter this uncharted territory, viewing it as nothing more than a “new normal” in hyper-competitive markets? Is it possible to strategically reposition their overall value proposition to build a long-term sustainable competitive advantage? Does the current operating model enable chip companies to deal with the added complexity of delivering quality embedded software? How efficient is the R&D organization in delivering to the new paradigm? As we try to find answers to these questions, let us examine the opportunities and discuss what companies should do in order to address the unique challenges that lie ahead.

Benefiting from the changing landscape

These trends have the potential to open new opportunities for semiconductor device makers, just by virtue of their position as key enablers of the value chain. Here are some ways in which companies can build a competitive advantage over rivals, if they play their cards right. Many leading companies are slowly recognizing the underlying opportunities:

  • Enhanced product differentiation: Device makers could differentiate themselves by moving to a solution offering that includes a complete library of embedded software modules – feature-rich middleware such as protocol stacks, integrated graphical user interfaces, and integrated security software. Also, they could use embedded software to deliver tremendous flexibility to incorporate evolving technology standards (e.g., communication protocols) on the same silicon device with a minor software update. Thirdly, companies could target the same device to multiple applications by using embedded software to “tune” the chip performance, thus allowing OEM customers to quickly create product variants for minor, incremental effort.
  • Increased platform leverage: Companies could employ advanced architecture exploration as part of the design process to arrive at intelligent “hardware – software” partitioning, to result in a single hardware device that can be customized to the needs of different applications or customers. Creating “common/unified” hardware, and building the differentiating functionality in software increases platform leverage (fewer distinct silicon devices), and hence improves the return on R&D investment. This strategy not only reduces the cost of designing and managing multiple silicon versions, but also simplifies the overall supply chain by reducing operational complexity.
  • New revenue streams: Although there is already a growing perception that the “value add” has increasingly come to reside in the software, much of today’s embedded software is given away for free in order to secure the “design wins”. However, opportunities to monetize it could arise if companies make the right strategic moves to hedge against a future, wherein hardware is a commodity “vehicle” to deliver value-added functionality to the end consumer. Bundled middleware and application software could be sold as packaged software or on a one-time NRE (Non-Recurring Engineering) fee followed licence royalty model for every unit sold. Significant upgrades to functionality could also be software enabled and delivered to customers remotely, for a fee.

How can companies respond?

Irrespective of where companies find themselves on this journey from chip to solution companies, it is worthwhile to take a holistic view of strategy through execution. PwC’s Product Innovation and Development team has identified a few areas of focus for device companies to help position themselves  for success:

Revisit the overall strategy:  Firstly, companies should rethink their overall strategy, focused on:

  • Their role in the evolving ecosystem and the types of embedded software to offer, e.g., system IP, firmware, and development tools, etc.
  • The markets/applications to offer system solutions, supported by customer value proposition and business case
  • An operational assessment to determine capability gaps, and how to address them, e.g., organically, via partnerships, or through M&A

The clamour of M&A activity indicates that chip vendors are acquiring software companies to rapidly gain the required system knowledge and incorporate it into their “complete solution” offerings. PwC’s analysis indicated that  between January 2010 and June 2013, semiconductor firms acquired 16 companies for system software, 3 for application software, and 8 for the software development tools. There were a total of 34 M&A transactions by semiconductor firms during this period (including private placements)

Design a new operating model: Next, companies should redesign their operating model in alignment with their strategy, focused on the following key areas:

F3

  • Agile development methodology: Companies should consider adopting the Agile methodology or its variants to helping them focus on quality, and flexibly respond to ever changing customer requirements effectively. For a detailed look at effective Agile adoption, read PwC’s whitepaper titled “Accelerating embedded software development via agile techniques: The nine strategies that lead to successful embedded software development”
  • Organizational structure: Companies should work to build a collaborative model of development that encompasses all ecosystem partners and OEM customers build teams. Cross-functional teams with broad application and system know-how will allow teams to make intelligent trade-off decisions that best suits the market or application. Teams should be accountable for overall solution, and empowered to drive rapid decision-making
  • Partnership models: Operationalizing the partnership model is essential to drive go-to-market efforts, and is achieved through a collaborative, cross-enterprise level effort that spans R&D, marketing, sales and customer support
  • Software productivity tools: Companies should evaluate and adopt new development tools that can help improve R&D productivity by speeding up the design and testing process. The increased sophistication of hardware-software co-development requires tools such as virtual prototyping, IDEs, and emulators that enable fast and effective testing of complex, deeply embedded hardware-software functionality. Specialized Requirements Management tools can also help effectively manage complex hardware/software dependencies, thereby delivering improved efficiency and quality

Conclusion

As companies embark on this operational transformation, it is important to periodically benchmark performance against leading companies. Metrics should account for effectiveness of R&D investments, development productivity, speed of execution, and quality. The new paradigm demands new solutions.

For more information contact Anand Sundaram at [email protected]

The need for high sigma yield


February 24, 2014

By Dr. Bruce McGaughy, Chief Technology Officer and Senior Vice President of Engineering, ProPlus Design Solutions, Inc.

In the mid-1990s, the former head of General Electric Jack Welch and Six Sigma were all but synonymous. Many a corporation implemented Six Sigma to improve process quality, based on Welch’s outspoken endorsement of the program.

Today, the semiconductor industry is using similar terminology to refer to high sigma yield prediction, a means to statistically determine the impact of process variations on parametric yield for integrated circuits such as SRAM that require extremely low failure rate.

No one needs to be Jack Welch to know why. In fact, it’s a huge challenge for the industry and it has been getting the attention it deserves of late –– the move to state-of-the-art 28nm/20nm planar CMOS and 16nm FinFET technologies present greater challenges to yield than any previous generation.

The key challenge is high sigma yield analysis that covers yield from roughly the 4 to 7+ σ range –– the range where traditional Monte Carlo simulation methods break down due to the requirement of high-sample numbers with associated long run times. For 3 σ designs, Monte Carlo continues to be a viable solution.

Foundries now require SRAM memory verification to 7 σ in 16nm FinFET technology, a technical impossibility without deploying a special high sigma yield prediction tool. The reason memory bit cell yield targets are being set so high is due to large process variations and shrinking design margins at advanced nodes and larger memory sizes. Most commercially available tools are unable to address 7+σ reliably or accurately.

Multiple methods are available to tackle the high sigma challenge, discussed at length in a recent ProPlus whitepaper. The key is an accurate and reliable estimate of yield out to very high sigma values with a reasonable number of simulations.

High Sigma methods that utilize Monte Carlo as the foundation are able to take advantage of its robustness but overcome its inability to scale to high sigma analysis. Designers are further pushing the high sigma boundary running the analysis on larger and larger blocks, such as an SRAM array. The requirement to analyze large designs with tens of thousands of variables creates a compounding effect on the high sigma problem.

This gives a glimpse into the scope of the high sigma challenge. On the one hand, there is a need to validate yield out to 7+ σ ranges. On the other, there is pressure to run high sigma analysis on large designs.

Yes, challenges abound. More than one industry expert is calling for an integrated design for yield (DFY) flow to answer the challenge. That’s because the conventional design flow is outmoded and struggling under the weight of these weighty requirements. An integrated DFY flow, advise the experts, needs accurate statistical device modeling and a powerful SPICE simulator. Most important, the new flow needs yield prediction, analysis and fixing capabilities that can cover requirements from 3 to 7+ σ yield.

Few tool providers today offer all three in an integrated DFY flow. In fact, most electronic design automation (EDA) tool providers in this space offer one product that may or may not be “best in class.” While “best in class” may suggest a company focused on its core competence, it’s a mistake to think that not providing an integrated DFY flow is an acceptable practice in the era of FinFET.

Anyone in charge of developing or managing a complete DFY flow should employ the principals of Six Sigma consistently through all three stages of the whole flow. The checklist should start with an integrated DFY methodology that neatly packages statistical device modeling and a powerful SPICE simulator with yield prediction, analysis and fixing capabilities up to and beyond 7 σ.  A designer should be able to tick off on the checklist the key points of accuracy, productivity improvement, scalability, high s yield, high σ optimization, and cost effectiveness.  That’s the recommendation for EDA teams and designers in the FinFET era. And, one that Jack Welch would endorse.

Long live FinFET


February 3, 2014

By Zhihong Liu, Executive Chairman, ProPlus Design Solutions, Inc., San Jose, Calif.

 

FinFET technology, with its multi-gate architecture for superior scalability, is gaining momentum with foundries, EDA vendors and fabless design companies, a welcome trend that began in 2013 and will continue into 2014.

Enormous effort has been expended already by leading manufactures such as GLOBALFOUNDRIES, Intel, Samsung and TSMC and their EDA partners to support the new technology node that offers so much promise. The move to FinFET portends good things for the semiconductor industry as it enables continuous Moore’s Law scaling down to sub-10nm and delivers higher performance and lower power consumptions. The revolutionary device architecture also brings challenges to designers and EDA companies developing FinFET design tools and methodologies. The achievement of FinFET solution readiness across the design flow is a significant accomplishment, especially considering the PDK itself was migrating in parallel from v0.1 and v0.5 toward v1.0.

The industry-standard BSIM-CMG model, developed by the BSIM group at the University of California at Berkeley, uses complicated surface-potential based equations to model FinFET devices, which also require complex parasitic resistance and capacitance models. As a result, SPICE simulation performance is known to be a few times slower than bulk technology with BSIM4 models. In addition, netlist sizes for FinFET designs are large, especially for post-layout extracted simulations, the norm given the impact of process variations, including layout effects on a design. Lower Vdd, increased parasitic capacitance coupling and noise sensitivity create a need for high accuracy circuit SPICE simulation where convergence of currents and charges is carefully controlled. These issues significantly impact the type of circuit simulation solution that will be viable for FinFETs.

FinFET poses many other design challenges that both EDA vendors and designers have to respond to. For example, “width quantization” puts new requirements on analog and standard cell designers. They can only use quantized widths instead of arbitrary width values in their designs.

The FinFET harvest is just beginning. As production tapeout activity ramps up, more emphasis will be placed on improving the performance of design flows, such as accelerating simulation and better sampling methods for corners or high sigma Monte Carlo analysis. Parametric yield will continue to be a key requirement as design houses attempt to maximize ROI from an existing node or to maximize the investment into a new node. The days of “margining” to safeguard a design are over. At the newer nodes, designers will invest more time figuring out where the yield cliff actually is and making sure their design is robust and will yield in production.

As a result, designers will have to seek out new tools and methodologies to overcome FinFET design challenges. One example is the adoption of giga-scale parallel SPICE simulators to harness circuit simulation challenges in FinFET designs. Traditional SPICE simulators don’t have the capacity and lack sufficient performance to support FinFET designs, while FastSPICE simulators likely will not meet accuracy requirements. Another example is where FinFETs have created increased interest in high sigma analysis of library designs such as SRAMs, standard cells and I/Os. Designers are working hard to fulfill a foundry requirement to verify bitcell designs to 7 sigma. That requirement can only be achieved by proven variation analysis tools that can support large capacity and high sigma yield analysis out to high sigma values.

Yes, FinFET could be the technology to give the semiconductor and EDA industry a major boost. I say long live FinFET.

Read more from ProPlus Design Solutions’ Blog:

Memory design challenges require giga-scale SPICE simulation

DAC panels tackle giga-scale design challenges, semiconductor market in China

SPICEing up circuit design

SEMI ISS: Scaling innovation


February 3, 2014

By Ira Feldman, Feldman Engineering Corp.

Don’t pop the champagne just yet! Although plenty of good news was shared at the 2014 SEMI Industry Strategy Symposium (ISS) there was the sobering outlook of possible limited long-term growth due to technology issues as well as economic projections. Noticeable was the lack of news and updates on key industry developments.

This is the yearly “data rich” or “data overload” (take your pick) conference of semiconductor supply chain executives. The majority of the attendees and presenters are from the SEMI member companies that develop the equipment, materials, processes, and technology used to build, test, and package semiconductors. Keeping the pressure on for advanced technology were the “end customer” attendees and presenters – semiconductor manufacturers.

The official theme was “Pervasive Computing – An Enabler for Future Growth” and the presentations made it clear that pervasive computing will greatly increase the demand for semiconductors. However, as discussed in context of very high volume applications such as the Internet of Things and the recent TSensors Summit, such explosive growth will only occur at a sufficiently low price point for these semiconductors and micro-electromechanical systems (MEMS) based sensors.

A major focus of ISS is economics: both the global trends that drive the semiconductor industry and the cost of new technology. Unlike past years, much of the discussion about new technology centered on economics rather than “will it work.” Past discussions about 450mm wafers, extreme ultra-violet (EUV) photolithography, and 3D transistor structures focused on the soundness of these technologies, not the economics.

The question that is being asked of technologists with increasing frequency is: “When will Moore’s Law end?” The cost reduction necessary to keep pace with Moore’s prediction that the minimum cost per transistor will be achieved when the number of transistors on a semiconductor device doubles every two years has primarily been achieved through shrinking the size of the transistors (“scaling”). Many smart people predicted the end of transistor scaling was upon us, hence the demise of Moore’s Law, only to be proven wrong as scaling continued.

Numerous speakers including Jon Casey (IBM) and Mike Mayberry (Intel) stated that scaling will continue below the 10 nm process node perhaps to 5 or 7 nm. However, the question raised by both the speakers and the audience was at what cost will this scaling be achieved. Rick Wallace (KLA-Tencor) reminded us that the demise of the Concorde supersonic plane was the economics and not the technology. In drawing a parallel to the challenge of continued scaling, Mr. Wallace said, “Moore’s Law is more likely to be killed in the board room than in the laboratory.” Therefore, we really need to look to the product managers and executives as well as the technologists for the answer.

The development on 450mm silicon wafers continues via the G450C consortium and Paul Farrar (G450C) provided a progress update. Their current estimates show 450mm ready for production in the range of late 2017 to mid-2020. Meanwhile Bob Johnson (Gartner) showed projected mid-2018 intercepts for Intel and Taiwan Semiconductor Manufacturing Company (TSMC) capability and first true production fabs in 2019-2020. Many of the equipment companies expressed concerns about their return on investment (ROI) for developing 450 mm equipment especially with a limited market. The weakness of demand can be summed up by Manish Bhatia (SanDisk) who said SanDisk/Toshiba didn’t want to build the last 300 mm fab nor were they in the running to build the first 450 mm fab. It appears as though many customers and suppliers share a “wait and see” attitude even though there are still many years of hard work required to launch 450mm.

No formal update on extreme ultra-violet (EUV) photolithography was presented this year although concerns about throughput and cost were mentioned by several speakers. These concerns are part of the fundamental economics of scaling which will require EUV and/or multi-patterning (multiple passes through the photolithography patterning modules for each layer of the semiconductor device instead of the single pass typical of older process nodes) to achieve smaller dimensions. ASML’s last presentation to ISS was in 2012 shortly before they became the “sole” developer of EUV so I hope there will be a public update later this year. For a while, EUV appeared to be a prerequisite for 450 mm development based upon process node intercept but the G450C plan of record (POR) is 193 nm immersion photolithography. G450C will start “investigating” EUV in the second half of 2016. Is this another code for “wait and see”?

Ivo_Bolsens_Xilinx_SEMI_ISS_2014

Ivo Bolsens (Xilinx) reviewed the challenges and costs in developing next generation application specific integrated circuits (ASICs) and application specific standard product (ASSP). In particular he shared the staggering increase in the cost of the non-recurring engineering (NRE) to develop leading edge semiconductors. (Shown in the chart above.) In less than three years, the estimated NRE cost has jumped from $85 M for a 45 nm design to over $170 M for 28 nm. Included in these NRE estimates are the cost of the design work, masks, embedded software (IP licenses), and yield ramp-up cost. The data presented shows an exponential growth for NRE for each new process node. Rough extrapolation would place 14 nm at $340 M and 7 nm at $680 M respectively. Good news, scaling will continue. Bad news, products may not be able to afford it.

With all this dark and murky news about the future, what was the good news from SEMI ISS? Innovation. The undercurrent of almost every presentation was: since we cannot guarantee that future scaling will provide the savings needed, we need to look at alternative materials, device structures, computation models, system architectures, etc. to continue on the expected cost reduction slope. The list includes a wide range of technology from “More than Moore” (system in packaging, 2.5D, 3D packaging, etc.) to 3D FinFET transistors to carbon nanotubes (CNT) to optoelectronic interconnects, and beyond.

Mr. Wallace in his opening keynote discussed the prerequisites for innovation and shared his concern that some companies have become “too big to innovate”. Even more importantly, if the semiconductor industry wants to remain relevant and attract the best young talent we need to be the “magic behind the gadget.” The Tuesday afternoon sessions closed out with Mark Randall (Adobe Systems) who described his efforts to drive grass-roots innovation by empowering any employee to innovate with no strings attached. Young Sohn (Samsung Electronics) provided his keynote “Innovation in a Connected World” at the banquet describing their work to move from communication devices (smartphones, tablets, etc.) to something that does more to improve lives.

Yes, “innovation” has become an industry buzzword that is often overused. Having seen where these companies say they need to go it is clear many understand it is time to innovate or die. They realize that profitable scaling won’t last forever. Difficult strategic decisions need to be made – marketers and engineers cannot / will not change the direction of their companies by themselves. Enabling innovation and making bold strategic changes requires executive leadership.

Meanwhile, consumers will expect the continuation of Moore’s Law – or at least the end result of continually lowered cost and/or higher performance – without giving a thought to the industry’s inability to continue cost effective scaling or other technical mumbo-jumbo. We still need to continue to make the magic happen!

As always, I look forward to hearing your comments either below or directly. Please don’t hesitate to contact me to discuss your thoughts. For more my thoughts, please see hightechbizdev.com

Ira Feldman ([email protected]) is the Principal Consultant of Feldman Engineering Corp. which guides high technology products and services from concept to commercialization. He follows many “small technologies” from semiconductors to MEMS to nanotechnology engaging on a wide range of projects including product generation, marketing, and business development.

By Zvi Or-Bach, President and CEO of MonolithIC

A recent SEMI report titled SEMI Reports Shift in Semiconductor Capacity and Equipment Spending Trends reveals an important new trend in semiconductors: “spending trends for the semiconductor industry have changed. Before 2009, capacity expansion corresponded closely to fab equipment spending.  Now more money is spent on upgrading existing facilities, while new capacity additions are occurring at a lower pace, to levels previously seen only during an economic or industry-wide slowdown”.

Looking at the semi-equipment booking should be the first step in any attempt to assess future semiconductor trends. While talking is easy, spending billions of dollars is not. Vendors look deeply into their new design bookings and their future production needs before committing new dollars to long lead purchases for their manufacturing future needs. In the past decade it was relatively simple, as soon as a new process node reached production maturity vendors would place new equipment orders knowing that soon enough all new designs and their volume will shift to the new process node. But the SEMI report seems to tell us that we are facing a new reality in the semiconductor industry – a Paradigm Shift.

A while ago VLSI Research Inc. released the following chart with the question: Is Moore’s Law slowing down?

Zvi1Jan27

The chart above indicates a coming change in the industry dynamic, and 2013 might be the year that this turns out to be a Paradigm Shift.

 Just few weeks ago at the SEMI ISS conference, Handel Jones of IBS presented many very illuminating charts and forecasts. The following chart might be the most important of them and it is the revised calculation of per gate cost with scaling.

 Zvi2Jan27

Clearly the chart reveals an unmistakable Paradigm Shift as 28nm is the last node for which dimensional scaling provides a per gate cost reduction. It makes prefect sense for the vendors and their leading edge customers to respond accordingly. Hence it easy to understand why more equipment is being bought to support 28nm and older nodes.

The following table, also from Jones, illustrates this new reality.

 Zvi3Jan27

In the equipment business, more than 50% of demand comes from the memory segment where the dollars per sold wafer are much lower than in logic. It seems that the shift there has already taken place. Quoting Randhir Thakur, Executive Vice President, General Manager, Silicon Systems Group, Applied Materials, Inc -as was recently published in The shift to materials-enabled 3D: ” our foundry/logic and memory customers that manufacture semiconductors are migrating from lithography-enabled 2D transistors and 2D NAND to materials-enabled 3D transistors and 3D NAND”…”Another exciting inflection in 2014 is our memory customers’ transition from planar two-dimensional NAND to vertical three-dimensional NAND. 3D technology holds the promise of terabit-era capacity and lower costs by enabling denser device packing, the most fundamental requirement for memory”. Which fits nicely with the following illustration made by Samsung as part of their 3D-NAND marketing campaign.

Zvi4Jan27

As for the logic segment, the 3D option is yet to happen. But as we wrote in respect to 2013 IEDM – More Momentum Builds for Monolithic 3D ICs.

The following chart from CEA Leti illustrates the interest for monolithic 3D-

 Zvi5Jan27

 It should be noted that monolithic 3D technology for logic is far behind in comparison to memory. Given that the current issues with dimensional scaling are clearly only going to get worse, we should hope that an acceleration of the effort for logic monolithic 3D will take place soon. In his invited paper at IEDM 2013, Geoffrey Yeap, VP of Technology at Qualcomm, articulates why monolithic 3D is the most effective path for the semiconductor future: “Monolithic 3D (M3D) is an emerging integration technology poised to reduce the gap significantly between transistors and interconnect delays to extend the semiconductor roadmap way beyond the 2D scaling trajectory predicted by Moore’s Law.” As illustrated by his Fig. 17 below.

 Zvi6Jan27

So, in conclusion, our industry is now going thru a paradigm shift. Monolithic 3D is shaping up as one of the technologies that would revive and sustain the historically enjoyed growth and improvements well into the future. The 2014 S3S conference scheduled for October 6-9, 2014 at the Westin San Francisco Airport will provide both educational opportunities and cutting edge research in monolithic 3D and other supporting domains. Please mark your calendar for this opportunity to contribute and learn about the new and exciting monolithic 3D technology.

By Dr. Ramesh Ramadoss, Formfactor, San Jose, CA

Micro-Electro-Mechanical Systems (MEMS) are a class of miniature devices and systems fabricated by micromachining processes. MEMS devices have critical dimensions in the range of 100 nm to 1000 µm (or 1 mm). MEMS technology is a precursor to the relatively more popular field of Nanotechnology, which refers to science, engineering and technology below 100 nm down to the atomic scale. Occasionally, MEMS devices with dimensions in the millimeter-range are referred to as meso-scale MEMS devices. Figure 1 shows relevant dimensional scale alongside biological matter.  

 Figure 1. Dimensional scale of MEMS and Nanotechnology. (Adapted from Nguyen et al. [1]).

Figure 1. Dimensional scale of MEMS and Nanotechnology. (Adapted from Nguyen et al. [1]).

Initially, MEMS technology was based on silicon using bulk micromachining and surface micromachining processes. Figure 2 shows an SEM image of a surface micromachining based polysilicon MEMS device, an electrostatic motor, which consists of twelve fixed stator electrodes and a rotor that spins around the pivot at its center. Gradually, other materials such as glass, ceramics and polymers have been adapted for MEMS. Especially, polymers are attractive for biomedical applications due to their bio-compatibility, low cost, and suitability for rapid prototyping. Other micromachining processes employed for fabrication of MEMS include dry plasma etching, electroplating, laser machining, micromilling, micromolding, stereolithography, and inkjet printing.

 

Figure 2. An SEM image of a MEMS electrostatic motor. (Source: https://www.mems-exchange.org/).

Figure 2. An SEM image of a MEMS electrostatic motor. (Source: https://www.mems-exchange.org/).

MEMS devices can actuate or sense on a micro-scale. MEMS devices can function individually or in combination with other devices to generate effects of meso- or macro- scale. Some advantages of MEMS devices include small size, light weight, low power consumption and high functionality compared to conventional devices. Further, MEMS technology offers cost reduction due to batch processing techniques similar to semiconductor Integrated Circuit (IC) manufacturing. Initially, MEMS technology emerged as an offshoot of the semiconductor industry and eventually established itself as a specialized field of study with a significant market share. According to Yole Développement, the MEMS industry market in 2012 was $11 billion, which is a 10 percent growth from the previous year.

MEMS applications

MEMS applications in various functional domains are shown in Figure 3. The term “functional domain” is used to refer to a domain in which the MEMS device performs a function such as sensing or actuation. In the early stages, MEMS proved to be a revolutionary technology in various fields of the physical domain such as Mechanical (e.g., Pressure sensors, Accelerometers, and Gyroscopes), Microfluidics (e.g., Inkjet nozzles), Acoustics (e.g., Microphone), RF MEMS (e.g., Switches and Resonators), and Optical MEMS (e.g., Micromirrors). Gradually, MEMS technology has demonstrated unique solutions and delivered innovative products in chemical, biological and medical domains as well. MEMS have penetrated into consumer electronics, home appliances, automotive industry, aerospace industry, biomedical industry, recreation and sports [2].

Figure 3. MEMS applications in various functional domains.

Figure 3. MEMS applications in various functional domains.

Typically, electronics are used to interface MEMS devices from its functional domain (i.e., Physical, Chemical, or Biological) to the electrical domain for signal transduction and/or recording. It should be pointed out that the term MEMS was originally coined to refer to miniature sensors and actuators operating between electrical and mechanical domains. Gradually, the term MEMS has evolved to encompass a wide variety of other microdevices fabricated by micromachining. For example, a micromachined electrochemical sensor is referred to as a MEMS device even though there is no functional role played by this device in the mechanical domain. Similarly, the term “BioMEMS” is used to refer to the science and technology of microdevices fabricated by micromachining for biological and medical applications. BioMEMS may or may not include any electrical or mechanical functions. BioMEMS application areas include biomedical transducers, microfluidics, medical implants, microsurgical tools, and tissue engineering. As shown in Figure 4, the global BioMEMS market is expected to almost triple in size, from $1.9 billion in 2012 to $6.6 billion in 2018 [3].

Figure 4. BioMEMS market forecast by Yole Développement [3]. (Source: http://www.yole.fr/).

Figure 4. BioMEMS market forecast by Yole Développement [3]. (Source: http://www.yole.fr/).

 BioMEMS applications

 In this section, a few representative BioMEMS applications are presented. A survey of all products available on the market is beyond the scope of this article.

a) MEMS Pressure Sensors The first MEMS devices to be used in the biomedical industry were reusable blood pressure sensors in the 1980s. MEMS pressure sensors have the largest class of applications including disposable blood pressure, intraocular pressure (IOP), intracranial pressure (ICP), intrauterine pressure, and angioplasty. Some manufacturers of MEMS pressure sensors for biomedical applications include CardioMEMS, Freescale semiconductors, GE sensing, Measurement Specialties, Omron, Sensimed AG and Silicon Microstructures.

According to World Health Organization (WHO), Glaucoma is the second leading cause of blindness in the world after cataracts. MEMS implantable pressure sensors are used for continuous IOP monitoring in Glaucoma patients. A normal eye maintains a positive IOP in the range of 10-22 mmHg. Abnormal elevation (> 22 mmHg) and fluctuation of IOP are considered the main risk factors for glaucoma. Glaucoma, often without any pain or significant symptoms, can cause an irreversible and incurable damage to the optic nerve. This initially affects the peripheral vision and possibly leads to blindness without timely lifetime treatment. Therefore, it is critical to accurately monitor IOP and provide prompt treatments at the early stages of glaucoma development. Sensimed’s TriggerfishTM implantable MEMS IOP sensor is shown in Figure 5. It consists of a disposable contact lens with a MEMS strain-gage pressure sensor element, an embedded loop antenna (golden rings), and an ASIC microprocessor (2mmx2mm chip). The MEMS sensor includes a circular active outer ring and passive strain gages to measure corneal curvature changes in response to IOP. The loop antenna in the lens receives power from the external monitoring system and sends information back to the system.

Figure 5. Sensimed’s TriggerfishTM implantable MEMS IOP sensor. (Source: http://www.sensimed.com/).

Figure 5. Sensimed’s TriggerfishTM implantable MEMS IOP sensor. (Source: http://www.sensimed.com/).

b)      MEMS Inertial Sensors MEMS accelerometers are used in defibrillators and pacemakers. Some patients exhibit unusually fast or chaotic heart beats and thus are at a high risk of cardiac arrest or a heart attack. An implantable defibrillator restores a normal heart rhythm by providing electrical shocks to the heart during abnormal conditions. Some peoples’ hearts beat too slowly, and this may be related to the natural aging process or a genetic condition. A pacemaker maintains a proper heart beat by transmitting electrical impulses to the heart. Conventional pacemakers were fixed rate. Modern pacemakers employ MEMS accelerometers and are capable of adjusting heart rate in accordance with the patient’s physical activity. Medtronic is a leading manufacturer of MEMS based defibrillators and pacemakers. Figure 6 shows a MEMS accelerometer-based Medtronic’s SureScanTM pacemaker and implantation of a pacemaker inside the body next to the heart. This pacemaker is designed to be compatible with magnetic resonance imaging (MRI).

Figure 6a.

Figure 6a.

Ramesh F6b

MEMS inertial sensors (accelerometers and gyroscopes) were employed to develop one of the most unique wheelchairs, the iBOTTM Mobility system, shown in Figure 7. A combination of multiple inertial sensors in this system enables the user to operate the wheelchair and lift to a standing height just balancing on two wheels. This allows the wheelchair user to interact with others face-to-face. The iBOTTM system was developed by Dean Kamen in a partnership between DEKA and Johnson and Johnson’s Independence Technology division. Unfortunately, it is no longer available for sale from Independence Technology. Another related example is the Segway PT, a two-wheeled, self-balancing, battery-powered electric vehicle, also invented by Dean Kamen. It is produced by Segway Inc. of New Hampshire, USA.

Figure 7. Independence Technology’s iBOTTM mobility system. (source: http://www.ibotnow.com/).

Figure 7. Independence Technology’s iBOTTM mobility system. (source: http://www.ibotnow.com/).

c)       MEMS Hearing-Aid Transducer A hearing-aid is an electroacoustic device used to receive, amplify and radiate sound into the ear. The goal of a hearing aid is to compensate for the hearing loss and thus make audio communication more intelligible for the user. In the US, hearing aids are considered medical devices and are regulated by the FDA. According to NIH, approximately 17 percent (36 million) of American adults report some degree of hearing loss. There is a strong relationship between age and reported hearing loss. Also, about 2 to 3 out of every 1,000 children in the United States are born deaf or hard-of-hearing.

 According to statistics, 80% of those who could benefit from a hearing-aid chose not to use one. The reasons include reluctance to recognize hearing loss and social stigma associated with common misconceptions about wearing hearing aids. Thus, it is highly desirable to miniaturize hearing-aids without compromising performance. MEMS technology enables reduction of form factor, cost, and power consumption compared to conventional hearing-aid solutions. Figure 8 shows Analog Devices small size (7.3 mm3) MEMS microphone suitable for hearing-aid applications.

Figure 8. Analog Devices MEMS microphone for hearing-aid applications. (Source: http://www.analog.com/).

Figure 8. Analog Devices MEMS microphone for hearing-aid applications. (Source: http://www.analog.com/).

d)      Microfluidics for diagnostics Microfluidics involve movement, mixing and control of small volumes (nanoliters) of fluids. A typical microfluidic system is comprised of needles, channels, valves, pumps, mixers, filters, sensors, reservoirs, and dispensers. Microfluidics enable bedside or at the point-of-care (POC) medical diagnosis. Especially, POC diagnosis is important in developing countries where access to centralized hospitals is limited and expensive. A POC diagnostic microfluidic system uses bodily fluids (saliva, blood, or urine samples) to perform sample preconditioning, sample fractionation, signal amplification, analyte detection, data analysis, and results display. In 1985, Unipath introduced the first POC microfluidic device, ClearBlueTM, for pregnancy test from urine sample and is still available on the market. Recently, a comprehensive review article on the commercialization of microfluidic devices for POC diagnostics was published by Chin et al. [4].

One of the world’s most significant public health challenges, particularly in low- and middle- income countries, remains to be HIV/AIDS. According to WHO, 34 million people are living with HIV, and around 7 million eligible people are waiting for antiretroviral therapy. POC diagnosis is very crucial for the enumeration of absolute numbers of T-helper cells, commonly referred to as a CD4 count, for monitoring the course of immunosuppression caused by HIV and the initiation of antiretroviral therapy. The Alere Pima™ CD4 test system, shown in Figure 9, offers a revolutionary POC solution by providing an absolute CD4 count from either a fingerstick or a venous whole blood sample. The test requires approximately 25 microliters of whole blood sample to be loaded into the cartridge capillary. All test reagents are sealed within the disposable cartridge. On insertion of the cartridge into the analyzer, the test process automatically begins and displays direct CD4 measurement within 20 minutes.

Figure 9. Alere’s PimaTM point-of-care CD4 test system: a) disposable cartridge, and b) analyzer with a slot for cartridge insertion. (Source: http://alere-technologies.com/).

Figure 9. Alere’s PimaTM point-of-care CD4 test system: a) disposable cartridge, and b) analyzer with a slot for cartridge insertion. (Source: http://alere-technologies.com/).

Ramesh F9b

e)      Microfluidics for drug delivery Microfluidics enable advanced drug delivery technologies such as triggered release, timed release and targeted delivery. Some applications include transdermal drug delivery (e.g., microneedle arrays and needle-less jet-based system), implantable drug delivery systems (e.g., drug-eluting stents and insulin pump), and drug delivery vehicles (e.g., micro- and nano– particles).

In the US, Diabetes mellitus has a mortality of 180,000 per year. It can be managed through proper diet and exercise, glucose-lowering oral medications and/or insulin therapy. One of the most notable insulin delivery systems for diabetes therapy, JewelPUMPTM, is shown in Figure 10. This system was developed by Debiotech in collaboration with STMicroelectronics. The MEMS nanopumpTM mounted on a disposable skin patch provides continuous insulin through jet-based infusion delivery. The whole system weighs only 25 grams and holds up to 500 units of insulin and can be used for a 7 day period without any need for refill or replacement. The JewelPUMPTM is directly programmed from a large display remote controller. It can be attached to the body using a disposable skin patch and can be detached when necessary, thereby offering more freedom to the patient.

 

Figure 10b. Attachment of the system to the body using a disposable skin patch (left) JewelPUMPTM (middle) and programmable remote controller (right) (Source: http://www.debiotech.com/).

Figure 10b. Attachment of the system to the body using a disposable skin patch (left) JewelPUMPTM (middle) and programmable remote controller (right) (Source: http://www.debiotech.com/).

f)       Micromachined needles Micromachining enables fabrication of needles smaller than 300 µm, which is the limit of conventional machining methods. Typically, the length of the MEMS-based microneedles is less than 1 mm. Microneedles have been used for drug delivery, bio-signal recording electrodes, blood extraction, fluid sampling, cancer therapy, and microdialysis. Frequently, microneedles are integrated and used in conjunction with microfluidic systems. Solid and hollow microneedles have been fabricated out of silicon, glass, metals, and polymers using micromachining processes. Microneedles have been demonstrated with various body shapes (cylindrical, canonical, pyramid, candle, spike, spear, square, pentagonal, hexagonal, octagonal and rocket shape) and tip shapes (volcano, snake fang, cylindrical, canonical, micro-hypodermis and tapered). Figure 11 shows solid microneedles fabricated by reactive ion etching of silicon [5] and hollow microneedles fabricated by laser machining of a polymer.

Figure 11a. Micromachined needles: silicon based solid needles. (Source: Henry et al. [5]).

Figure 11a. Micromachined needles: silicon based solid needles. (Source: Henry et al. [5]).

Figure 11a. Micromachined needles: polymer based hollow needles. (Source: http://www.lasermicromachining.com/).

Figure 11a. Micromachined needles: polymer based hollow needles. (Source: http://www.lasermicromachining.com/).

g)      Microsurgical tools Surgery is treatment of diseases or other ailments through manual and instrumental methods. In surgery, the majority of trauma to the patient is caused by the surgeon’s incisions to gain access to the surgical site. Minimally invasive surgical (MIS) procedure aims to provide diagnosis, monitoring, or treatment of diseases by performing operations with very small incisions or sometimes through natural orifices. Advantages of MIS over conventional open surgery includes less pain, minimal injury to tissues, minimal scarring, reduced recovery time, shorter hospital visits, faster return to normal activities and often lower cost to the patient. Common MIS procedures include angioplasty, catheterization, endoscopy, laparoscopy, and neurosurgery. MEMS based microsurgical tools have been identified as a key enabling technology for MIS [6]. A pair of silicon MEMS based microtweezers and metal MEMS based biopsy forceps are shown in Figure 12. It should be noted that some of these feasibility demonstrations have yet to be qualified for clinical applications.

Figure 12a. Micromachined surgical tools: a pair of silicon MEMS tweezers. (Source: http://www.memspi.com/).

Figure 12a. Micromachined surgical tools: a pair of silicon MEMS tweezers. (Source: http://www.memspi.com/).

Figure 12b. Micromachined surgical tools: a pair of metal MEMS biopsy forceps. (Source: http://www.microfabrica.com/).

Figure 12b. Micromachined surgical tools: a pair of metal MEMS biopsy forceps. (Source: http://www.microfabrica.com/).

Cardiovascular disease continues to be the leading cause of death in the United States. One of the common fatal cardiovascular conditions is narrowing of blood vessels due to accumulation of plaque that can lead to heart attack, stroke and other serious issues. Angioplasty is a procedure designed to restore normal blood flow through clogged or blocked arteries. A cardiac stent is inserted into a blood vessel via a catheter and then expanded to enlarge the vessel. There are two general types of stents: Metal stents and polymer stents. Metal stents are the conventional type. Two main types of polymer stents are resorbable and nonresorbable. The former type is attractive as it may be absorbed or dissolved inside the body. Figure 13 shows a stent fabricated on a bio-resorbable polymer by laser micromachining. 

Figure 13. Micromachined resorbable polymer stent. (Source: http://resonetics.com/).

Figure 13. Micromachined resorbable polymer stent. (Source: http://resonetics.com/).

Other BioMEMS applications include tissue engineering [7] and microfluidics for cell biology, proteomics, and genomics [8]. A comprehensive coverage of various BioMEMS applications can be found in the recent books [9] and [10].

  In the 21st century, BioMEMS devices are anticipated to revolutionize the biomedical industry similar to that of semiconductor devices to the electronics industry in the last century. As evident from the market trend, there are tremendous opportunities for MEMS in the biomedical industry. However, FDA approval process necessary for certain applications can cause significant delays for new BioMEMS devices entering the market.

 References

1.       N.-T. Nguyen, S. A. M. Shaegh, N. Kashaninejad, and D.-T. Phan, “Design, fabrication and characterization of drug delivery systems based on lab-on-a-chip technology,” Advanced drug delivery reviews (2013).

2.       M. Bourne, A Consumer’s Guide to MEMS & Nanotechnology, Bourne Research LLC, 1st edition, 2007.

3.       BioMEMS 2013: Microsystem Device Market for Healthcare Applications, Yole Developpment, France, Feb. 2013.

4.       C.D. Chin, V. Linder, and S. K. Sia. “Commercialization of microfluidic point-of-care diagnostic devices,” Lab on a Chip 12.12 (2012): 2118-2134.

5.       S. Henry, D. V. Mc Allister, M. G. Allen and M. R. Prausnitz, “Microfabricated Microneedles: A Novel Approach to Transdermal Drug Delivery,” Journal of Pharmaceutical Sciences, 1998, 87, pp. 922-925.

6.       K. Rebello, “Applications of MEMS in Surgery,” Proceedings of the IEEE, vol. 92, no. 1, Jan. 2004, pp. 43-55.

7.       C. M. Puleo,  H. C. Yeh,  T. H. Wang, “Applications of MEMS technologies in tissue engineering,” Tissue Engineering, 13(12), 2007, pp. 2839-2854.

8.       F. A. Gomez, Biological Applications of Microfluidics, Wiley-Interscience, 1st edition, 2008.

9.       A. Folch, Introduction to BioMEMS, CRC Press, 1st edition, 2013.

10.   Shekhar Bhansali (Editor), and Abhay Vasudev (Editor), MEMS for Biomedical Applications, Woodhead Publishing, 1st edition, 2012.

Dr. Ramesh Ramadoss is currently employed as a Senior Manager in the MicroProbe Product Group of FormFactor Inc., San Jose, California. He received his B.E. degree from Thiagarajar College of Engineering, Madurai, India in May 1998 and Ph.D. degree in Electrical Engineering from the University of Colorado at Boulder in May 2003. From June 2003 to Dec. 2007, he was employed as an Assistant Professor in the Department of Electrical and Computer Engineering at Auburn University, Auburn, Alabama. From Jan. 2008 to Mar. 2012, he was employed as a Program Manager, MEMS R&D, FormFactor Inc., Livermore, California. Since April 2012, he has been employed at MicroProbe, San Jose, CA (Acquired by FormFactor Inc.). He is the author or coauthor of 3 book chapters and 53 papers in the MEMS field (Google Scholar Citations: 476, h-index: 14, and i10-index: 17). He has conducted MEMS R&D projects for DARPA, NASA, US Army, AOARD, Sandia National Labs, Motorola Labs, Foster-Miller Inc. and FormFactor Inc.

CEA-Leti, Fraunhofer IPMS-CNT and three European companies — IPDiA, Picosun and SENTECH Instruments — have launched a project to industrialize 3D integrated capacitors with world-record density.

The two-year, EC-funded PICS project is designed to develop a disruptive technology through the development of innovative ALD materials and tools that results in a new world record for integrated capacitor densities (over 500nF/mm2) combined with higher breakdown voltages. It will strengthen the SME partners’ position in several markets, such as automotive, medical and lighting, by offering an even higher integration level and more miniaturization.

The fast development of applications based on smart and miniaturized sensors in aerospace, medical, lighting and automotive domains has increasingly linked requirements of electronic modules to higher integration levels and miniaturization (to increase the functionality combination and complexity within a single package). At the same time, reliability and robustness are required to ensure long operation and placement of the sensors as close as possible to the “hottest” areas for efficient monitoring.

For these applications, passive components are no longer commodities. Capacitors are indeed key components in electronic modules, and high-capacitance density is required to optimize – among other performance requirements – power-supply and high decoupling capabilities. Dramatically improved capacitance density also is required because of the smaller size of the package.

IPDiA has for many years developed an integrated capacitors technology that out performs current technologies (e.g. tantalum capacitors) in terms of stability in temperature, voltage, aging and reliability. Now, a technological solution is needed to achieve higher capacitance densities, reduce power consumption and improve reliability. The key enabling technology chosen to bridge this technological gap is atomic layer deposition (ALD) that allows an impressive quality of dielectric.

The PICS project consortium will address all related technological challenges and set up a cost-effective industrial solution. Picosun will develop ALD tools adapted to IPDiA’s 3D trench capacitors. SENTECH Instruments will provide a new solution to more accurately etch high-K dielectric materials. CEA-Leti and Fraunhofer IPMS-CNT will help the SMEs create innovative technological solutions to improve their competitiveness and gain market share. Finally, IPDiA will manage the industrialization of these processes.

About PICS The PICS project has received funding from the European Union’s Seventh Framework Program managed by REA-Research Executive Agency http://ec.europa.eu/rea (FP7/2007-2013) under grant agreement n° FP7-SME-2013-2-606149.

The PICS Project will last for two years and the consortium consists of three SMEs: IPDiA (France, coordinator), Picosun (Finland) and Sentech Instruments (Germany), and two leading research organizations: Fraunhofer IPMS-CNT (Germany) and CEA-Leti (France). Project objectives are to bring to mass production high density and high voltage capacitors based on ALD and etching development. Further information is available at www.fp7-pics.eu

 

About IPDiA IPDiA is a preferred supplier of high performance, high stability and high reliability silicon passive components to customers in the medical, automotive, communication, computer, industrial, and defense/aerospace markets. The company portfolio includes standard component devices such as silicon capacitors, RF filters, RF baluns, ESD protection devices as well as customized devices. IPDiA headquarters are located in Caen, France. The company operates design centers, sales and marketing offices and a manufacturing facility certified ISO 9001 / 14001 / 18001 / 13485 as well as ISO TS 16949 for the Automotive market. For further information, please visit www.ipdia.com

About Picosun Picosun is the world leading provider of ALD solutions for global industries. Picosun’s pioneering, unmatched expertise in ALD equipment design and manufacturing reaches back to the invention of the technology itself. Today, PICOSUN™ ALD systems are in daily production use in numerous prominent industries around the globe. Picosun is based in Finland, it has its subsidiaries in USA and Singapore, and world-wide sales and support network. For more information, visit www.picosun.com.

 

About SENTECH Instruments SENTECH Instruments GmbH develops, manufactures, and sells worldwide advanced quality instrumentation for Plasma Process Technology, Thin Film Measurement, and Photovoltaics. The medium-sized company founded in 1990 has grown fast over the last decades and has today 60 employees. SENTECH is located in Berlin, capital of Germany, and has moved to its own company building in 2010 in order to expand its production facilities.

SENTECH plasma etchers and deposition systems including ALD support leading-edge applications. They feature high flexibility, reliability, and low cost of ownership. SENTECH’s plasma products are developed and manufactured in-house and thus allow for customer-specific adaptations. More than 300 units have been sold to research facilities and industry for applications in nanotechnology, micro-optics, and optoelectronics. More information: www.sentech.de

About Fraunhofer IPMS-CNT Fraunhofer IPMS-CNT is a German research institute that develops advanced 300 mm semiconductor process solutions for Front-End and Back-End-of Line applications on state-of-the-art process- and analytical equipment. Research is focused on process development enabling 300 mm production, innovative materials and its integration into Systems (SoC/SiP) as well as nanopatterning through electron beam lithography. Fraunhofer is largest application-oriented research organization in Europe with 66 institutes and 22,000 employees. More information:  www.cnt.fraunhofer.de

About CEA-Leti By creating innovation and transferring it to industry, Leti is the bridge between basic research and production of micro- and nanotechnologies that improve the lives of people around the world. Backed by its portfolio of 2,200 patents, Leti partners with large industrials, SMEs and startups to tailor advanced solutions that strengthen their competitive positions. It has launched more than 50 startups. Its 8,000m² of new-generation cleanroom space feature 200mm and 300mm wafer processing of micro and nano solutions for applications ranging from space to smart devices. Leti’s staff of more than 1,700 includes 200 assignees from partner companies. Leti is based in Grenoble, France, and has offices in Silicon Valley, Calif., and Tokyo. Visit www.leti.fr for more information.  

On 16 October 2013, Carlos Lee, Director General of the European Photonics Industry Consortium (EPIC), moderated a discussion with executives from the UK photonics industry. In conjunction with the Photonex UK exhibition, he approached the discussion from an international perspective of how various regions in the world and countries in Europe support their photonics industry. Mr. Lee filed this report:

While governments need to ensure a supportive legal and regulatory framework for companies to blossom, Anke Lohmann, Director of Photonics at UK government agency ESP KTN (Electronics, Sensors, Photonics Knowledge Transfer Network) pledged for industry engagement and collaboration between companies to address specific needs for ESP KTN to focus on. Mark Sims, Professor at the Space Research Centre of the University of Leicester requested on the other hand for the UK Science budget to be increased as soon as possible “by keeping it flat it is being eroded by inflation putting at risk the UK’s capability for medium and long-term growth”. 

The UK, which has historically been strong in manufacturing but then shifted focus to banking decades ago, wants to go back and rebalance the economy to include manufacturing, which it recognizes is imperative to create jobs, create growth, and avoid stagnation. Photonics will certainly play a role as one of the features of our industry is that it comprises a high proportion of small companies, which anticipate a higher recruitment percentage growth than larger companies. The UK claims 1,500 companies in photonics with a direct employment of 70,000 and a production output of £10.5 billion. This is about 20% of Europe’s total and the UK expertise is well balanced, with a distribution based on employment of Optical Systems (20%), Medical (19%), Production (15%) and Defence (10%). The UK has particular expertise in various fields such as Space, Life Science, Defence, Sensing (food, security, gas), and 3D Advanced Manufacturing. A clear sign of the expertise in the UK in these sectors are the many historical acquisitions such as SPI Lasers by Trumpf, CIP Technologies by Huawei, Barr & Stroud by Thales, Microlase Optical by Coherent and many more such examples. John Lincoln, appointed CEO of the UK Photonics Leadership Group (PLG) said that it was a priority to make a connection between photonics and the higher level of the value chain already being supported by the UK. David Gahan, a photonics industry veteran and currently a consultant, asked the UK TSB (Technology Strategy Board) to “provide follow-on funding into the higher levels of TRL 6-7 (Technology Readiness Level) to support demonstrators.” Remaining competitive requires a company to have access to skilled staff. Malcolm Varnham, Vice President Intellectual Property and Co-Founder of SPI Lasers asked for emphasis on the importance of education and training.

The show itself has much improved, after a dip in 2009 following the banking crisis, the UK’s only “photonics” exhibition has grown to 105 exhibitors, a level not seen for many years. Maybe it was due to a general improvement of the photonics market or because the organisers have added a co-located vacuum technologies exhibition, or the application-related sessions to their programme such as nano and bio-imaging and space applications. The event has also developed a strong Vision UK branding which supports its claim to be the primary European event for vision technology in 2013.