Author Archives: psinger

A new Department of Energy grant will fund research to advance an additive manufacturing technique for fabricating three-dimensional (3D) nanoscale structures from a variety of materials. Using high-speed, thermally-energized jets to deliver both precursor materials and inert gas, the research will focus on dramatically accelerating growth, improving the purity and increasing the aspect ratio of the 3D structures.

Known as focused electron beam induced deposition (FEBID), the technique delivers a tightly-focused beam of high energy electrons and an energetic jet of thermally excited precursor gases – both confined to the same spot on a substrate. Secondary electrons generated when the electron beam strikes the substrate cause decomposition of the precursor molecules, forming nanoscale 3D structures whose size, shape and location can be precisely controlled. This gas-jet assisted FEBID technique allows fabrication of high-purity nanoscale structures using a wide range of materials and combination of materials.

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By allowing the rapid atom-by-atom “direct writing” of materials with controlled shape and topology, the work could lead to a nanoscale version of the 3D printing processes now revolutionizing fabrication of structures at the macro scale. The technique could be used to produce nano-electromechanical sensors and actuators, to modify the morphology and composition of nanostructured optical and magnetic materials to yield unique properties, and to engineer high performance interconnect interfaces for graphene and carbon nanotube-based electronic devices.

“This unique nanofabrication approach opens up new opportunities for on-demand growth of structures with high aspect ratios made from high-purity materials,” said Andrei Fedorov, the project’s leader and a professor in the Woodruff School of Mechanical Engineering at the Georgia Institute of Technology. “By providing truly nanoscale control of geometries, it will impact a broad range of applications in nanoelectronics and biosensing.”

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Researchers have demonstrated the feasibility of the technique, and expect the three-year $660,000 grant to help them develop a fundamental understanding of how the process works, accelerate the rate of materials growth and provide improved control over the process. The research will include both theoretical modeling and experimental evaluation. Proof of principle for using thermally-energized gas jets as part of the FEBID technique was reported by Fedorov’s group in the journal Applied Physics Letters in 2011.

“Wherever electrons strike the surface, you can grow the deposit,” explained Fedorov. “That provides a tool for growing complex three-dimensional structures from a variety of materials with resolution at the tens of nanometers. Electron beam induced deposition is much like inkjet printing, except that it uses electrons and precursor molecules in a vacuum chamber.”

Two major challenges lie ahead for using the technique to manufacture 3D nanostructures: increasing the rate of deposition and eliminating the unwanted deposits of carbon that are formed as part of the process. To address these challenges, Fedorov and his team are using energetic jets of inert argon gas to clean substrate surfaces and carefully tune the energy of the desired molecules delivered in another jet to enhance the rate at which the precursor sticks to the substrate.

“If the energy of the jet is sufficiently high, the inert gas molecules striking the surface can knock away the adsorbed hydrocarbon contamination so that there is no parasitic carbon co-deposition,” he said. “We can also tune the properties of the precursor molecules so they stick more effectively to the surface. We have shown that we can increase the rate of growth by an order of magnitude or more while maintaining a high aspect ratio of deposited nanostructures.”

Overall, about two dozen materials have been successfully deposited using FEBID on different substrates, including semiconductors, dielectrics, metals and even plastics. The researchers also plan to create nanostructures containing more than one material, allowing them to create unique properties not available in each individual material. Examples might include new types of ferromagnetic materials and photonic bandgap structures with unique properties.

Fedorov’s group has used FEBID to fabricate low-resistance contacts to carbon nanotubes and graphene, a unique carbon-based material with attractive electronic properties.

Major technical challenges for the project include making tightly focused jets of thermally-energized precursor molecules to provide precise control of the fabrication. In operation, precursor molecules enter the reaction chamber from the micron-scale nozzle at sonic speeds, and accelerate in the vacuum environment to even greater speed, forming a molecular beam that impinges on the substrate. To make structures of the desired morphology, researchers will have to control the spreading of the generated molecular beam and its energy state at the point of contract with the substrate.

“We will be growing structures ranging in size from tens to hundreds of nanometers,” Fedorov noted. “This means we will not only have to confine electrons to very small regions, but we will also need to confine the precursor molecules to these same domains.”

The FEBID technique will likely not be used for high-volume fabrication because the process is difficult to scale up, Fedorov said. Accelerating the deposition rate will allow more rapid fabrication, but the 3D structures will still need to be produced one at a time. A partial solution to the scale-up challenge lies in the use of multiple electron beams and precursor jets operating in parallel.

The new technique will allow researchers to take better advantage of the unique properties of materials at the nanometer scale. Researchers will also have to account for those differences in developing the new manufacturing technique, as the interactions between electrons, precursor materials in the jet and substrate continually change with growth of the deposit.

“This research will open up the potential for some new discoveries in areas we may not be able to predict now,” said Fedorov. “We need to understand the basic physics of what is happening. That basic understanding could lead us to some truly unique applied capabilities, and the possibilities are almost limitless.”

Dr. Bruce McGaughy, CTO and SVP of Engineering at ProPlus Design Solutions, Inc. blogs about the wisdom of Monte Carlo analysis when high sigma methods are perhaps better suited to today’s designs.

Years ago, someone overhead a group of us talking about Monte Carlo analysis and thought we were referring to the gambling center of Monaco and not computational algorithms that have become the gold standard for yield prediction. All of us standing by the company water cooler had a good laugh. That someone was forgiven because he was a recent college graduate with a degree in Finance and a new hire. As a fast learner, he quickly came to understand the benefits of Monte Carlo analysis.

I was recently reminded of this scene as the limitations of Monte Carlo analysis approaches are becoming more acute because of capacity. No circuit designer would mistake Monte Carlo analysis for a roulette wheel, though chip design may seem like a game of chance today. We continue to use the Monte Carlo approach for high-dimension integration and failure analysis even as new approaches emerge.

Emerging they are. For example, high sigma methods with proven techniques are becoming more prevalent for the design of airplanes, bridges, financial models, integrated circuits and more. Moreover, high sigma methods also are used for electronic design for various applications and are proving to be accurate by validation in hardware.

New technologies, such as16nm FinFET, add extra design challenges that require high sigma greater than six and closer to 7 sigma, making Monte Carlo simulation even less desirable.

Let’s explore a real-world scenario using a memory design as an example where process variations at advanced technologies become more severe, leading to a greater impact on SRAM yield.

The repetitive structure circuits of an SRAM design means extremely low cell failure rate is necessary to ensure high chip yield. Traditional Monte Carlo analysis is impractical in this application. In fact, it’s nearly impossible to finish the needed sampling because it typically requires millions or even billions of runs.

Conversely, a high sigma method can cut Monte Carlo analysis sampling by orders of magnitude. A one megabyte SRAM would require the yield of a bitline cell to reach as high as 99.999999% in order to achieve a chip yield of 99%. Monte Carlo analysis would need billions of samples. The high sigma method would need mere thousands of samples to achieve the same accuracy, shortening the statistical simulation time and making it possible for designers to do yield analysis for this kind of application.

High sigma methods are able to identify and filter sensitive parameters, and identify failure regions. Results are shared in various outputs and include sigma convergence data, failure rates, and yield data equivalent to Monte Carlo samples.

Monte Carlo analysis has had a good long run for yield prediction, but for many cases it’s become impractical. Emerging high sigma methods improve designer confidence for yield, power, performance and area, shorten the process development cycle and have the potential to save cost. The ultimate validation, of course, is in hardware and production usage. High sigma methods are gaining extensive silicon validation over volume production.

Let’s not gamble with yield prediction and take a more careful look at high sigma methods.

About Bruce McGaughy

Bruce McGaughy, CTO and Senior VP of Engineering at ProPlus Solutions in San Jose, CA.

Bruce McGaughy, CTO and Senior VP of Engineering at ProPlus Solutions in San Jose, CA.

Dr. Bruce McGaughy is chief technology officer and senior vice president of Engineering of ProPlus Design Solutions, Inc. He was most recently the Chief Architect of Simulation Division and Distinguished Engineer at Cadence Design Systems Inc. Dr. McGaughy previously also served as a R&D VP at BTA Technology Inc. and Celestry Design Technology Inc., and later an Engineering Group Director at Cadence Design Systems Inc. Dr. McGaughy holds a Ph.D. degree in EECS from the University of California at Berkeley.

Nanofluidic channels are useful for many biological and chemical applications, such as DNA sequencing, drug delivery, blood cell sorting and molecular sensing and detection. But in the effort to build a versatile lab-on-a-chip, it has been challenging to develop a wafer-scale nanochannel fabrication process compatible with CMOS technology.

At the upcoming International Electron Devices Meeting (IEDM), to be held December 9-11 in Washington, D.C., IBM researchers will report on a CMOS-compatible 200 mm wafer-scale sub-20nm nanochannel fabrication method that enables stretching, translocation and real-time fluorescence microscopy imaging of single DNA molecules.

Through the use of sacrificial XeF2 etching and various UV and e-beam lithography methods, sub-20-nm patterns in silicon were converted into macro-scale fluidic ports, micro-scale fluidic feed channels, and nano-scale channels for DNA imaging. Gradient nanopillars were located in the channels to stretch DNA molecules prior to imaging them. Fluid wasn’t pumped through the channels, but instead was transported by the force of gravity. The researchers say their techniques lead to highly manufacturable structures and can produce chips for a variety of biological applications.

A schematic of the nanochannel architecture. Grey represents silicon layers, while blue represents SiO2. The silicon layers serve as sacrificial material.

A schematic of the nanochannel architecture. Grey represents silicon layers, while blue represents SiO2. The silicon layers serve as sacrificial material.

The etching sequence of the silicon layers is shown: A) silicon-patterning with sub-20 nm features (note the inset SEM electron microscope photo); B) capping-oxide deposition followed by vent-hole patterning: and C) XeF2 gas-phase etching of silicon patterns embedded in SiO2.

The etching sequence of the silicon layers is shown: A) silicon-patterning with sub-20 nm features (note the inset SEM electron microscope photo); B) capping-oxide deposition followed by vent-hole patterning: and C) XeF2 gas-phase etching of silicon patterns embedded in SiO2.

SEM electron microscope photo of silicon nanochannels.

SEM electron microscope photo of silicon nanochannels.

Optical photos showing A,B) nanochannels with vent holes on 1-2 µm SiO2 capping layer, on top of silicon patterns; and C,D) following gas etching and removal of silicon patterns.

Optical photos showing A,B) nanochannels with vent holes on 1-2 µm SiO2 capping layer, on top of silicon patterns; and C,D) following gas etching and removal of silicon patterns.

Wang (14.1) Fig.12 (450x338)

 

Jordan Valley Semiconductors Ltd., a supplier of X-ray based metrology tools for advanced semiconductor manufacturing lines, received another order for its recently introduced JVX7300LMI scanning X-ray in-line metrology tool for patterned and blanket wafers.  The system has been purchased for advanced process development and production ramp-up for 14nm and 10nm nodes.

The tool provides fully automated advanced metrology for epitaxial materials such as SiGe, Si:C/P and III-V on silicon FinFET structures, as well as high-k and metal gate stacks and other critical layers.

Isaac Mazor, JV CEO, said: “We are pleased to have been selected by key customers to support their FEOL (Front-End-Of-Line) process metrology.  This selection represents the customers’ confidence in Jordan Valley’s ability to provide valuable metrology solutions for their most demanding advanced applications, trusting first principle X-ray based metrology to provide unique process control solutions.”

Mazor added, “Advanced logic devices set new metrology challenges and requirements for key transistor level structure such as FinFET, Ge and III/V materials on silicon, as well as high-k and metal gate stacks used to enhance the transistor performance. Jordan Valley was able to meet the customers’ stringent process requirements in a short period of development time.”

“In choosing the JVX7300LMI platform, the customers acknowledged the significant contribution of the product in shortening the process development cycle, coupled with enabling process performance and extendibility to future technology nodes.” Mazor concluded, “We believe that the JVX7300LMI can be a strong contributor to assure high yield in the current and next generation process nodes.”

The JVX7300LMI is an X-ray metrology system for 14nm and 10nm nodes R&D and production ramp for FEOL applications such as SiGe, Si:C/P, FinFETs, high-k/metal gate and replacement channel materials such as Ge and III-V layers on Si. It is also used for the development and production of the emerging GaN on Si market.

JVX7300LMI


This tool enables scanning HRXRD, XRR and (GI)XRD measurements. HRXRD is capable of measuring epitaxial layer composition, thickness, density, strain and relaxation of single and multi-layer stacks. Additionally, with XRR and (GI)XRD channels, the tool provides information on the thickness, density, phase and crystallinity of ultra-thin layers typically used in the FEOL process. Unlike optical or spectroscopic tools, the HRXRD and XRR are first principle techniques that deliver accurate and precise results without calibration.

InGaAs is a promising channel material for high-performance, ultra low-power n-MOSFETs because of its high electron mobility, but multiple-gate architectures are required to make the most of it, because multiple gates offer better control of electrostatics. In addition, it is difficult to integrate highly crystalline InGaAs with silicon, so having multiple gates offers the opportunity to take advantage of the optimum crystal facet of the material for integration.

Transistors with high mobility channels will likely be required for the 10nm and 7nm device generations, scheduled to go into production in 2016/2016 and 2017/2018, respectively. InGaAs is a good candidate for NFETS, while germanium is the candidate of choice for PFET devices.

At the upcoming International Electron Devices Meeting (IEDM), to be held December 8-11 in Washington, D.C., a research team led by Japan’s AIST will describe how they built triangular InGaAs-on-insulator n-MOSFETs with smooth side surfaces along the <111>B crystal facet and with bottom widths as narrow as 30nm, using a metalorganic vapor phase epitaxy (MOVPE) growth technique. The devices demonstrated a high on-current of 930 µA/µm at a 300nm gate length, showing they have great potential.

 

Triangular transistors produced with MOVPE demonstrate a high on-current of 930 µA/µm at a 30nm gate length.

Triangular transistors produced with MOVPE demonstrate a high on-current of 930 µA/µm at a 30nm gate length.

The National Institute of Advanced Industrial Science and Technology (AIST) is a public research institution largely funded by the Japanese government. About 2300 researchers (about 2050 with tenure: about 80 from abroad) and a few thousands of visiting scientists, post-doctoral fellows, and students from home and abroad are working at AIST.  About 650 permanent administrative personnel and many temporary staff support research works of AIST.

Blog Review October 14 2013


October 14, 2013

At the recent imec International Technology Forum Press Gathering in Leuven, Belgium, imec CEO Luc Van den hove provided an update on blood cell sorting technology that combines semiconductor technology with microfluidics, imaging and high speed data processing to detect tumorous cancer cells. Pete Singer reports.

Pete Singer attended imec’s recent International Technology Forum in Leuven, Belgium. There, An Steegan, senior vice president process technology at imec, said FinFETs will likely become the logic technology of choice for the upcoming generations, with high mobility channels coming into play for the 7 and 5nm generation (2017 and 2019). In DRAM, the MIM capacitor will give way to the SST-MRAM. In NAND flash, 3D SONOS is expected to dominate for several generations; the outlook for RRAM remains cloudy.

At Semicon Europa last week, Paul Farrar, general manager of G450C, provided an update on the consortium’s progress in demonstrating 450mm process capability. He said 25 tools will be installed in the Albany cleanroom by the end of 2013, progress has been made on notchless wafers with a 1.5mm edge exclusion zone, they have seen significant progress in wafer quality, and automation and wafer carriers are working.

Phil Garrou reports on developments in 3D integration from Semicon Taiwan. He notes that at the Embedded Technology Forum, Hu of Unimicron looked at panel level embedded technology.

Kathryn Ta of Applied Materials connects how demand for mobile devices is driving materials innovation. She says that about 90 percent of the performance benefits in the smaller (sub 28nm) process nodes come from materials innovation and device architecture. This number is up significantly from the approximate 15 percent contribution in 2000.

Tony Massimini of Semico says the MEMS market is poised for significant growth thanks to major expansion of applications in smart phone and automotive. In 2013, Semico expects a total MEMS market of $16.8 B but by 2017 it will have expanded to $28.5 B, a 70 percent increase in a mere four years time.

Steffen Schulze and Tim Lin of Mentor Graphics look at different options for reducing mask write time. They note that a number of techniques have been developed by EDA suppliers to control mask write time by reducing shot count— from simple techniques to align fragments in the OPC step, to more complex techniques of simplifying the data for individual writing passes in multi-pass writing.

If you want to see SOI in action, look no further than the Samsung Galaxy S4 LTE. Peregrine Semi’s main antenna switch on BSOS substrates from Soitec enables the smartphone to support 14 frequency bands simultaneously, for a three-fold improvement in download times.

Vivek Bakshi notes that a lot of effort goes into enabling EUV sources for EUVL scanners and mask defect metrology tools to ensure they meet the requirements for production level tools. Challenges include modeling of sources, improvement of conversion efficiency, finding ways to increase source brightness, spectral purity filter development and contamination control. These and other issues are among topics that were proposed by a technical working group for the 2013 Source Workshop in Dublin, Ireland.

NY’s Marcy Nanocenter, the largest remaining shovel-ready, greenfield site in New York State’s Tech Valley near Utica, is another step closer to the goal of attracting major semiconductor manufacturing companies. Governor Andrew M. Cuomo announced that six leading global technology companies will invest $1.5 billion to create ‘Nano Utica,’ the state’s second major hub of nanotechnology research and development.

The public-private partnership, to be spearheaded by the SUNY College of Nanoscale Science and Engineering (SUNY CNSE) and the SUNY Institute of Technology (SUNYIT), will create more than 1,000 new high-tech jobs on the campus of SUNYIT in Marcy, NY.

The consortium of leading global technology companies that will create Nano Utica are led by Advanced Nanotechnology Solutions Incorporated (ANSI), SEMATECH, Atotech, and SEMATECH and CNSE partner companies, including IBM, Lam Research and Tokyo Electron. The consortium will be headquartered at the CNSE-SUNYIT Computer Chip Commercialization Center (Quad-C), and will build on the research and development programs currently being conducted by ANSI, SEMATECH, and their private industry partners at the SUNY CNSE campus in Albany, further cementing New York’s international recognition as the preeminent hub for 21st century nanotechnology innovation, education, and economic development.

“With today’s announcement, New York is replicating the tremendous success of Albany’s College of Nanoscale Science and Engineering right here in Utica and paving the way for more than a billion dollars in private investment and the creation of more than 1,000 new jobs,” Governor Cuomo said. “The new Quad C facility will serve as a cleanroom and research hub for Nano Utica whose members can tap into the training here at SUNYIT and local workforce, putting the Mohawk Valley on the map as an international location for nanotechnology research and development. This partnership demonstrates how the new New York is making targeted investments to transition our state’s economy to the 21st century and take advantage of the strengths of our world class universities and highly trained workforce.”

The computer chip packaging consortium will work inside the Quad C Complex now under construction on the SUNYIT campus, which is due to open in late 2014. As a result of the commitment of the major companies to locate at Nano Utica, the $125 million facility is being expanded to accommodate the new collaboration, with state-of-the-art cleanrooms, laboratories, hands-on education and workforce training facilities, and integrated offices encompassing 253,000 square feet. The cleanroom will be the first-of-its-kind in the nation: a 56,000-square-foot cleanroom stacked on two levels, providing more than five times the space that was originally planned. To support the project, New York State will invest $200 million over ten years for the purchasing new equipment for the Quad C facility; no private company will receive any state funds as part of the initiative.

Research and development to be conducted includes computer chip packaging and lithography development and commercialization. These system-on-a-chip innovations will drive a host of new technologies and products in the consumer and business marketplace, including smart phones, tablets, and laptops; 3D systems for gaming; ultrafast and secure computer servers and IT systems; and sensor technology for emerging health care, clean energy and environmental applications.

As part of the state’s work to promote innovation-driven economic development, the initiative will provide new momentum for development of the adjacent Marcy Nanocenter manufacturing site. CNSE is working with Mohawk Valley EDGE to lead development of the site, which has the capacity to support construction of three 450mm computer chip fabrication facilities.

As part of the initiative, SEMATECH, celebrating its 25th anniversary as an industry leader, will also expand its collaborative research and development activities in partnership with CNSE. Those efforts will target the most cutting-edge areas of nanoelectronics, including advanced lithography, 3D packaging, and metrology technologies that are critical to enabling the smaller, faster, and more powerful computer chips driving nearly every industry.

Fueled by the exploding market for smart phones, tablets and other mobile devices, computer chip packaging has become a critical factor in driving innovation amid the growing reliance on computer chip technologies in nearly every industry. The development of faster, more powerful chips relies not only on shrinking the size of circuits – more than a billion of which are packed on today’s chips – but also on improving packaging technologies, which refer to the conductors that connect the circuits, provide power, and discharge heat to keep them functioning properly.

Hector Ruiz, Chairman of Advanced Nanotechnology Solutions, Inc., said, “My Advanced Nano colleagues and I are working to create breakthrough technology, and we couldn’t find a better place to bring this investment and these jobs than New York. We looked across this country, and around the world, and this is where we found the talent, the mindset, and the leadership to help us revolutionize nanoscale technology, through semiconductors and everything they power.”

Dan Armbrust, president and CEO of SEMATECH, said, “New York State, led by Andrew Cuomo, demonstrates once again the global leadership and long-term commitment necessary to spur innovation and create a complete regional ecosystem that bridges research, development and manufacturing. SEMATECH’s long-standing partnership with NYS and SUNY College of Nanoscale Science and Engineering enables us to provide cutting-edge high-tech capabilities to serve the critical needs of our members. We are excited to continue to be a vital contributor to the growing technology scene in New York.”

Dr. Jaga Jagannathan, Vice President, Semiconductors, Atotech USA, said, “We applaud Governor Andrew Cuomo for his leadership and support, and are delighted to join with CNSE and our industry colleagues as part of this world-class consortium. This collaboration will play a critical role in advancing next-generation semiconductor technologies, and Atotech is pleased to contribute its unique capabilities as part of this groundbreaking effort.”

SUNY Chancellor Nancy L. Zimpher said, “Governor Cuomo has positioned New York and its public university system to lead the world in nanotechnology innovation that is creating jobs and fueling our economy.  This new investment in Utica will help the CNSE-SUNYIT Computer Chip Commercialization Center bring top companies to the Mohawk Valley and bring life-changing products to market.”

CNSE Senior Vice President and CEO Dr. Alain E. Kaloyeros said, “With this announcement, Governor Andrew Cuomo continues to write the pioneering playbook on how business and technology are catalyzed in the innovation-driven economy of the 21st century. Building on the Governor’s new model for publicly-led public-private partnerships, this initiative further strengthens New York’s recognition as the worldwide hub for the nanotechnology industry. Concurrently, it enables leading-edge research and development to serve the needs of industry while firmly establishing the state as a magnet for the attraction of high-tech jobs, companies and unparalleled private investment that will benefit the Mohawk Valley and all New Yorkers.”

Terry Higashi, Chairman, President & CEO of Tokyo Electron Limited, said, As a longtime partner of the College of Nanoscale Science and Engineering, and a true believer in Governor Andrew Cuomo’s vision for growing New York’s nanotechnology sector, we are delighted to hear of this first-of-its-kind consortium that will lead the industry in advanced semiconductor technologies. Working collaboratively with CNSE and our industry partners, we look forward to supporting continued innovation that will benefit our customers and the semiconductor industry.”

Martin Anstice, President and CEO of Lam Research, said, “This consortium is a testament to Governor Andrew Cuomo’s leadership in building a semiconductor industry in New York. The innovations that will be driven by this collaboration, building on our partnership with the College of Nanoscale Science and Engineering, will open up new opportunities for our company and the industry as a whole.”

Mike Splinter, executive chairman of Applied Materials, Inc., said, “Applied Materials applauds New York’s leadership in developing a vibrant high-tech ecosystem and we welcome this latest investment to grow the semiconductor industry here.”

Mohawk Valley EDGE President Steve DiMeo said, “Key watershed moments in the history of the Mohawk Valley were the building of the Erie Canal, the decision in 1951 to transfer personnel from Watson Laboratories in New Jersey to what became known as Rome Air Development Center and today’s announcement by Governor Cuomo on the consortia of companies that will focus on packaging and systems-on-a-chips technologies here at the Quad C.  Today’s announcement follows last month’s exciting announcement by CNSE that it will expand  its G450 PILOT facility with plans to build a 450 MM enabled semiconductor campus here at SUNYIT to help transition R&D activity into advanced manufacturing opportunities and validates a  key part of Governor Cuomo’s strategy to leverage our colleges and universities to make them engines of economic opportunities. What is taking place here at SUNYIT mirrors in many respects the model used in Palo Alto where physical assets at Stanford University were used to build what became known as Silicon Valley.”

By Lara Chamness, senior manager, market analysis, SEMI

Given the industry’s anemic performance during the first part of the year, a number of analysts have recently downgraded their 2013 semiconductor revenue forecasts to low-single digits, while forecasting stronger growth in 2014. SEMI believes that the semiconductor materials market will trend with the device market, resulting in an increase of one percent this year and a seven percent increase in 2014, resulting in a materials market approaching $50 billion in 2014.

Looking at materials trends by region, Japan has traditionally been the largest semiconductor materials consuming region owing to its significant fab base and packaging presence. Over the past four years, manufacturers in the region rapidly adopted a fab-lite strategy or have consolidated many of their fabs and packaging plants. During this same time, companies based in Taiwan invested heavily in advanced packaging and foundry operations.

In the 2009 downturn, the materials market contracted 22 percent in Japan, while falling only 12 percent in Taiwan. Immediately out of the downturn, all regional materials markets enjoyed strong gains and by 2011 the Taiwan market surged ahead Japan, resulting in Taiwan becoming the largest semiconductor materials consuming region in terms of revenue. Rest of World, primarily SE Asia, represents the third largest market for semiconductor materials given the dominance of packaging in the region. For this year and the next, Taiwan will strengthen its lead, with Rest of World’s materials market to exceed Japan’s next year (Figure 1) due to continued strength in its packaging materials market.

Figure 1. Semiconductor materials market forecast by region. Source: SEMI Materials Market Data Subscription, August 2013.

Figure 1. Semiconductor materials market forecast by region. Source: SEMI Materials Market Data Subscription, August 2013.

It is interesting to note that in spite of many Japanese device manufacturers opting for a fab-lite strategy and/or consolidating, Japan still represents one of the largest regional markets for fab materials. This should not be surprising considering that fabs located in Japan currently account for about 22 percent of global IC fab capacity, followed by South Korea with 21 percent, Taiwan with 19 percent and North America with 15 percent (Source: SEMI World Fab Forecast database, August 2013). As a result, the wafer fab materials market roughly mirrors IC fab capacity (Figure 2).

Figure 2. 2013F wafer fabrications materials market by region. Source: SEMI Materials Market Data Subscription, August 2013.

Figure 2. 2013F wafer fabrications materials market by region. Source: SEMI Materials Market Data Subscription, August 2013.

Given current growth expectations for the semiconductor market, SEMI is forecasting that semiconductor materials will increase 1 percent this year and 7 percent in 2014. Taiwan now dominates the semiconductor materials market as the result of its aggressive foundry and advanced packaging presence. Japan still represents a significant portion of the global materials market owing to its historical manufacturing strength but it is expected that Rest of World, primarily SE Asia, will surpass the Japan market next year as the Rest of World region grows at a stronger rate due to continued strength in its packaging materials market.

To learn more about semiconductor materials and key market trends, register to attend the SEMI Strategic Materials Conference, which will be held at the Santa Clara Marriott, in Santa Clara, California on October 16-17. For more information about SEMI, visit www.semi.org.

SPTS Technologies and imec announced a joint partnership to further advance micro- and nanosized components for BioMEMS, using SPTS’ Rapier silicon deep reactive ion etching (Si DRIE) technology.

Micro and nanotechnologies are fast becoming key enablers in medical research, diagnosis and treatment, with rapid developments in areas like DNA sequencing and molecular diagnostics. Imec, as one of the pioneers in the field, is developing the underlying heterogeneous technology and components as the backbone to these life science tools.

One of the most important process techniques in BioMEMS manufacturing is deep silicon etching. It can be used to manufacture devices such as microfluidic channels, polymerase chain reaction (PCR) chambers, mixers and filters. As a leading institute in advanced micro and nanoelectronics research, imec is currently developing lab-on-chip technology for fast SNP (single nucleotide polymorphisms) detection in human DNA and a microsized detection system for circulating tumor cells in the human blood stream. The outcome of this research will be products that deliver a better quality of life for current and future generations.

IMEC_NR_SPTS

“We chose SPTS as a partner after running extensive wafer demonstrations on their tool, challenging them on the demanding structures required by our current projects,” says Deniz Sabuncuoglu Tezcan, who is leading imec’s Novel Components Integration team. “The results convinced us that the Rapier module can help us create the devices we envisage. The demos also showed that the processes will deliver the high throughputs and repeatability necessary for cost-effective volume production.”

At the International Electron Devices Meeting (IEDM) in December, IBM researchers will describe a silicon nanowire (SiNW)-based MOSFET fabrication process that produced gate-all-around (GAA) SiNW devices at sizes compatible with the scaling needs of 10nm CMOS technology. They built a range of GAA SiNW MOSFETs, some of which featured a 30nm SiNW pitch with a gate pitch of 60 nm.

Devices with a 90nm gate pitch demonstrated the highest performance ever reported for a SiNW device at a gate pitch below 100 nm— peak/saturation current of 400/976 µA/µm, respectively, at 1 V. Although this work focused on NFETs, the researchers say the same fabrication techniques can be used to produce PFETs as well, opening the door to a potential ultra-dense, high-performance CMOS technology.

IBM F2

The integration scheme allows for a reduced, more uniform diffusion distance, affording a more abrupt junction.

The integration scheme allows for a reduced, more uniform diffusion distance, affording a more abrupt junction.

A new two-step anneal process shows that the nanowires can be smoothened with no loss of density compared to planar processes.

A new two-step anneal process shows that the nanowires can be smoothened with no loss of density compared to planar processes.

The TEM electron microscope images above show: a) a cross section of a completed device through a gate, illustrating the spacer, epitaxial source/drain and contacts; (b) the cross section of a silicon nanowire (SiNW) decorated with a high-Z film to better show the nanowire’s boundary. The effective SiNW diameter shown is 12.8 nm; (c) a close up of the region of interest indicated in a), showing that the source/drain is epitaxially regrown from the cut face of the nanowire. The lattice planes in the epi region are registered to that of the original SiNW channel (parallel red dashed lines).

The TEM electron microscope images above show: a) a cross section of a completed device through a gate, illustrating the spacer, epitaxial source/drain and contacts; (b) the cross section of a silicon nanowire (SiNW) decorated with a high-Z film to better show the nanowire’s boundary. The effective SiNW diameter shown is 12.8 nm; (c) a close up of the region of interest indicated in a), showing that the source/drain is epitaxially regrown from the cut face of the nanowire. The lattice planes in the epi region are registered to that of the original SiNW channel (parallel red dashed lines).