Author Archives: psinger

An alternative to scaling is to expand vertically, by thinning, stacking and interconnecting ICs, commonly called 3D integration. Chip-to-chip Interconnections are are typically made with through-silicon vias (TSVs), but some TSVs also have major disadvantages, including relatively large dimensions, parasitic capacitances and thermal mismatch issues.

At the upcoming International Electron Devices Meeting (IEDM) in December, researchers from Taiwan’s National Nano Device Laboratories avoided the use of TSVs by fabricating a monolithic sub-50nm 3D chip, which integrates high-speed logic and nonvolatile and SRAM memories. They built it from ultrathin-body MOSFETs isolated by 300-nm-thick interlayer dielectric layers.

To build the device layers, the researchers deposited amorphous silicon and crystallized it with laser pulses. They then used a novel low-temperature chemical mechanical planarization (CMP) technique to thin and planarize the silicon, enabling the fabrication of ultrathin, ultraflat devices. The monolithic 3D architecture demonstrated high performance – 3-ps logic circuits, 1-T 500ns nonvolatile memories and 6T SRAMs with low noise and small footprints, making it potentially suitable for compact, energy-efficient mobile products.

The process flow used to fabricate the 3D IC without TSVs.

The process flow used to fabricate the 3D IC without TSVs.

A TEM electron microscope view of the 3D chip.

A TEM electron microscope view of the 3D chip.

 

At the International Electron Devices Meeting (IEDM) in December, TSMC researchers will unveil a 16nm FinFET process that by many measures is one of the world’s most advanced semiconductor technologies.

 

In size, it is the first integrated technology platform to be announced below the 20 nm node, with key features including a 48-nm fin  pitch and the smallest SRAM ever incorporated into an integrated process—a 128-Mb SRAM measuring 0.07 µm2 per bit. In performance, it demonstrated either a 35% speed gain or a 55% power reduction over TSMC’s existing 28-nm high-k/metal gate planar process, itself a highly advanced technology, and had twice the transistor density.  Short-channel effects were well-controlled, with DIBL <30 mV/V, saturation current of 520/525 µA/µm at 0.75V (NMOS and PMOS, respectively) and off-current of 30 pA/µm. It incorporates seven levels of high-density copper/low k interconnect and high-density planar MIM devices for noise control.

Figure 1 shows that the 16 nm FinFET achieved either a >35% speed gain or >55% power reduction over TSMC’s planar process.

Figure 1 shows that the 16 nm FinFET achieved either a >35% speed gain or >55% power reduction over TSMC’s planar process.

 

Figure 2 shows a cross-section of the device’s 7-level metal copper/low-k architecture.

Figure 2 shows a cross-section of the device’s 7-level metal copper/low-k architecture.

 

3D-IC: Two for one


September 25, 2013

Zvi Or-Bach, President & CEO of MonolithIC 3D Inc. blogs about upcoming events related to 3D ICs.

This coming October there are two IEEE Conferences discussing 3D IC, both are within an easy drive from Silicon Valley.

The first one is the IEEE International Conference on 3D System Integration (3D IC), October 2-4, 2013 in San Francisco, and just following in the second week of October is the S3S Conference on October 7-10 in Monterey. The IEEE S3S Conference was enhanced this year to include the 3D IC track and accordingly got the new name S3S (SOI-3D-Subthreshold). It does indicate the growing importance and interest in 3D IC technology.

This year is special in that both of these conferences will contain presentations on the two aspects of 3D IC technologies. The first one is 3D IC by the use of Through -Silicon-Via which some call -“parallel” 3D and the second one is the monolithic 3D-IC which some call “sequential.”

This is very important progress for the second type of 3D IC technology. I clearly remember back in early 2010 attending another local IEEE 3D IC Conference: 3D Interconnect: Shaping Future Technology. An IBM technologist started his presentation titled “Through Silicon Via (TSV) for 3D integration” with an apology for the redundancy in his presentation title, stating that if it 3D integration it must be TSV!

 Yes, we have made quite a lot of progress since then. This year one of the major semiconductor research organization – CEA Leti – has placed monolithic 3D on its near term road-map, and was followed shortly after by a Samsung announcement of mass production of monolithic 3D non volatile memories – 3D NAND.

We are now learning to accept that 3D IC has two sides, which in fact complement each other. In hoping not to over-simplify- I would say that main function of the TSV type of 3D ICs is to overcome the limitation of PCB interconnect as well being manifest by the well known Hybrid Memory Cube consortium, bridging the gap between DRAM memories being built by the memory vendors and the processors being build by the processor vendors. At the recent VLSI Conference Dr. Jack Sun, CTO of TSMC present the 1000x gap which is been open between  on chip interconnect and the off chip interconnect. This clearly explain why TSMC is putting so much effort on TSV technology – see following figure:

System level interconnect gaps

System level interconnect gaps

On the other hand, monolithic 3D’s function is to enable the continuation of Moore’s Law and to overcome the escalating on-chip interconnect gap. Quoting Robert Gilmore, Qualcomm VP of Engineering, from his invited paper at the recent VLSI conference: “As performance mismatch between devices and interconnects increases, designs have become interconnect limited. Monolithic 3D (M3D) is an emerging integration technology that is poised to reduce the gap significantly between device and interconnect delays to extend the semiconductor roadmap beyond the 2D scaling trajectory predicted by Moore’s Law…” In IITC11 (IEEE Interconnect Conference 2011) Dr. Kim presented a detailed work on the effect of the TSV size for 3D IC of 4 layers vs. 2D. The result showed that for TSV of 0.1µm – which is the case in monolithic 3D – the 3D device wire length (power and performance) were equivalent of scaling by two process nodes! The work also showed that for TSV of 5.0µm – resulted with no improvement at all (today conventional TSV are striving to reach the 5.0µm size) – see the following chart:

Cross comparison of various 2D and 3D technologies. Dashed lines are wirelengths of 2D ICs. #dies: 4.

Cross comparison of various 2D and 3D technologies. Dashed lines are wirelengths of 2D ICs. #dies: 4.

So as monolithic 3D is becoming an important part of the 3D IC space, we are most honored to have a role in these coming IEEE conferences. It will start on October 2nd in SF when we will present a Tutorial that is open for all conference attendees. In this Monolithic 3DIC Tutorial we plan to present more than 10 powerful advantages being opened up by the new dimension for integrated circuits. Some of those are well known and some probably were not presented before. These new capabilities that are about to open up would very important in various market and applications.

In the following S3S conference we are scheduled on October 8, to provide the 3D Plenary Talk for the 3D IC track of the S3S conference. The Plenary Talk will present three independent paths for monolithic 3D using the same materials, fab equipment and well established semiconductor processes for monolithic 3D IC. These three paths could be used independently or be mixed providing multiple options for tailoring differently by different entities.

Clearly 3D IC technologies are growing in importance and this coming October brings golden opportunities to get a ‘two for one’ and catch up and learn the latest and greatest in TSV and monolithic 3D technologies — looking forward to see you there.

SPICEing up circuit design


September 25, 2013

Dr. Zhihong Liu

Dr. Zhihong Liu, Executive Chairman, ProPlus Design Solutions, blogs about the challenges of designing for yield using SPICE models. 

The ubiquitous SPICE circuit simulator, initially released 40 years ago, made a recent list of the top 10 most significant developments in the history of EDA, as it should. Its widespread use and importance among circuit designers cannot be understated.

However, the third-generation of SPICE (Simulation Program with Integrated Circuit Emphasis) simulation is showing its age. Circuit designers are doing giga-scale simulations because of complex designs, increasingly simulated post-layout and the large number of simulations required to design for variation effects.

Giga-scale designs range from post-layout analog circuits, high-speed I/Os, memory and CMOS image sensor arrays to full-chip power ICs, and clock trees and critical path nets. They require a parallel SPICE simulator with high capacity in the order of tens of millions of elements for analog designs and hundreds of million elements for memory designs. A SPICE simulator needs to deliver high performance with pure SPICE accuracy and offer support for the latest process technologies such as FinFETs.

Three dimensional FinFETs bring additional challenges to device modeling and circuit simulations. Modeling and simulation tools must be able to handle increased layout dependencies in device characteristics and more complex parasitics, including internal parasitics and interactions between the device and surrounding components.

Current SPICE simulators can offer few of these must haves. Traditional SPICE simulators lack capacity even with parallelization capabilities. FastSPICE simulators deliver capacity at the cost of accuracy and are losing steam as an increasing number of designs require post-layout verification that weakens circuit hierarchy. The FastSPICE table model approach and approximated matrix solutions can offer unreliable results and poor usability for complicated giga-scale designs with multiple operating modes and supply voltages.

The key is to maintain simulation accuracy as traditional SPICE simulators do, and simultaneously, be able to handle large circuit simulation capacity that typically only FastSPICE simulators can do with reasonable simulation time. In today’s bleeding-edge designs, designers often can’t settle for performance or capacity by sacrificing accuracy as FastSPICE simulators can.

EDA vendors are aware of these trends and the increasingly urgent market needs. Almost all existing SPICE and FastSPICE simulators have been working hard to utilize parallel technologies on multicore and/or multi-CPU computing environments to improve simulation performance. However, patched-on parallelization offers short-term improvement, and can’t fully meet the need for simulation accuracy, performance and memory consumption for giga-scale circuit designs.

New simulation technology is essential for deep-nanometer technology designs where process variations impact circuit yield and performance. In addition to capacity challenges related to increasing circuit size, designers need to run large numbers of repeated simulations to tackle the impact of process variations. Process-Voltage-Temperature (PVT) analysis and statistical Monte Carlo analysis create another challenge dimension for giga-scale simulations.

In a circuit designer’s ideal world, the next-generation SPICE circuit simulator would be highly accurate with full SPICE analysis features and support for industry-standard inputs and outputs. It would be much, much faster than traditional SPICE simulators and able to handle all circuit types. The ability to simulate giga-scale circuits and challenging post-layout designs is mandatory. Building parallelization in a SPICE simulator from the ground up instead of patched-on solutions is the key to handling giga-scale simulations with good performance and memory consumption, while still offering SPICE accuracy. Most aging circuit simulators will soon show their limitations.

Ideally, the new SPICE simulator also will have native capabilities to handle process variations from 3-sigma to high-sigma Monte Carlo simulations, where hundreds or even thousands of simulations are needed. Circuit designers have begun to search for Design-for-Yield (DFY) solutions and not just cobbled-together point tools. A total DFY solution starts with a high-capacity, high-performance SPICE simulator as its engine. A simulator designed for DFY with built-in statistical simulation capabilities can provide incomparable simulation performance when compared to ad-hoc variation analysis with external circuit simulators.

And, of course, the SPICE simulation engine should be tightly integrated with statistical transistor model extraction and yield prediction/improvement software. Those components make a total DFY solution, and enable the efficiency and consistency of yield-analysis results.

Giga-scale simulation isn’t the future, it’s here today and needs viable solutions to meet the challenges it has created. SPICE simulators have served the circuit design industry for 40 years, and it’s time for the next generation, essential for deep nanometer technology designs.