MCA’s BrightSpots 3D IC Forum came to a close on Friday, July 24. Out of 3 topic areas covering technology
progress, supply chain issues, and standards development, the discussions around technology progress were clearly the most active, both from a panelist and attendee perspective. What follows is a summary of each discussion. Where topics overlapped, and discussions were brief, the summaries have been
combined into one.
TECHNOLOGY PROGRESS AND LIMITATIONS
What is 3D IC’s position along the technology curve?
3D IC is progressing along the adoption and technology curve. All panelists agreed that it has moved
from the first phase of research into the early phases of commercialization, with pilot lines coming
online at manufacturing sites, and SEMATECH’s 3D interconnect program ramping up to take processes
beyond feasibility and qualify them as manufacturing processes. While skeptics remain, early adopters
such as Tezzaron Semiconductor will pave the way for volume production.
What problems does 3D solve in comparison to traditional scaling?
3D IC integration offers myriad solutions to problems over traditional scaling. According to Bob Patti of
Tezzaron Semiconductor, 3D IC with TSV interconnect offers increased speed and density for higher
performance at lower power and cost. He predicts that over the next decade or two 3D will take the
limelight from CMOS. “The exploitation of 3D has barely started,” he says. “The opportunities go far
beyond just connecting together the bond pads.”
However, because 3D requires new processes and design paradigms, it scares people. The industry has
20+ years of shrinking CMOS success, but it is becoming more difficult to achieve. Most people now see
3D as an option and the question is more of when is 3D going to be easier and/or cheaper. The key
challenge according to Michael Fritze of DARPA is getting folks to start thinking about the novel
architectures that would be capable of exploiting 3D IC benefits.
Once processes have been narrowed to a “manageable few”, with roadmaps and standards in place,
Sitaram Arkalgud of SEMATECH says 3D IC integration permits the cost-effective combination of
dissimilar materials, technologies and signals. He points out that when it comes to thermal dissipation,
lower power consumption of 3D stacks will result in less heat generated, and additionally the 3D
configurations lend themselves to new and innovative methods of dissipating what heat exists.
If nine-die stacks can be done with wire bonding, why go to TSV?
If required speed, performance and density can be achieved by interconnecting bond pads with wire
bond, then it’s the most cost effective way. For flash memory with low I/O count, there’s no motivation
to move to TSV stacking. However with DRAM, there is an “immediate need” for TSVs. CMOS
repartitioning requires it. Again, it all comes down to performance improvements and cost.
Along these same lines, other alternative technologies such as Vertical Circuits’ vertical interconnect
pillar process and 3D Plus’ wirefree die-on-die may offer similar advantages to flash memory, but again
when it comes to repartitioning, TSV is the only viable solution, according to our panelists.
What new capabilities are required of EDA tools to support 3D IC design?
Ric Borges reports work at Synopsys is ramping to provide tools in time for market adoption of 3D IC
integration. Design teams are establishing requirements and priorities as a step toward developing
roadmaps. He says 3D tools will be built on existing platforms.
In the meantime, start-ups like R3 Logic, MicroMagic and Javelin Design Automation have introduced
layout editors, pathfinding tools, etc. for designing 3D ICs, thereby fulfilling a critical role by providing
tools with which companies can determine the value of 3D IC technologies in different applications. It’s
a widely held understanding that these start-up companies have the flexibility to work with a new
technology before the market demand is there. If they succeed and the market develops, the larger
companies are likely to acquire them.
Additionally, Borges says Synopsys is addressing the need for simulation tools for some key areas of 3D
IC process development such as simulating the stresses generating in and around the TSV, detailed
modeling of deep trench etching and seed liner deposition inside the TSV, and design-oriented concern
of computing the TSV parasitic capacitance and resistance.
How should 3D ICs be tested, and what difficulties does this present?
With circuit-level 3D, device layer testing isn’t possible due to the number of interconnects per die
numbering in the millions. What Bob Patti recommends is a self-test and repair approach. He says
designers should be ready for a paradigm shift where future yield relies on how repairable and fault
tolerant your design is, rather than KGD. On the other hand, I/O level 3D interconnect will benefit from
work being done by probe testing companies developing contact-free probe technologies. There are
reportedly 2 or 3 groups working on this.
SUPPLY CHAIN ISSUES
Who will handle post-fab processes for 3D IC stacking?
While fabs are the most likely to handle TSV fabrication, there’s still question as to whether OSATS or a
third party will handle post-TSV processes including wafer backside processing, thinning, stacking and
bonding.
What business aspects need to be considered for volume production?
While companies with strong financial positions, experience, and track records are likely to be the most
suited to take on 3D integration, few exist (Toshiba and ST Micro come to mind) that have absorbed the
risk of investment thus far. Yole D
