Category Archives: 3D Integration

July 14, 2008 – Wireless fabless developer Qualcomm is the first fabless IC company to participate in European R&D consortium IMEC’s industrial affiliation program on 3D integration, the firms say. Their joint research will strive to understand and develop ways to use 3D technologies, mainly 3D wafer-level packaging and 3D stacked ICs, in future wireless products.

With the addition of Qualcomm to its 3D program, “we have all the major supply chain players working together,” said IMEC CEO Luc Van den hove, in a statement. “We are confident that strong industry collaboration among foundries, IDMs, packaging and assembly companies, and equipment suppliers at IMEC will push the development of innovative 3D products forward.”

Incorporating 3D designs into its wireless products will create “superior features and performance in our products,” added Jim Clifford, SVP/GM of Qualcomm CDMA Technologies, noting in particular a desire to leverage IMEC’s R&D expertise to accelerate 3D implementation in its product designs.

Other partners in IMEC’s 3D integration program include: Amkor, Infineon, Intel, Micron, NEC, NXP, Panasonic, Qimonda, Samsung, ST Microelectronics, Texas Instruments, and TSMC.

(July 8, 2008) ST FLORIAN, AUSTRIA &#151 EV Group(EVG)announced the order and successful installation of its 300-mm bonding, alignment, and photoresist fully automatic processing tools at ST Microelectronics'(ST) 300-mm through-silicon-via (TSV) pilot line in Crolles, France. The company says the tools will be used in the manufacture of CMOS imaging sensors (CIS) Using TSV technology.

Industry experts anticipate that the first products to feature TSV technology are reportedly expected to hit the market in 2008 and will include flash memory and image sensors, similar to what ST is developing with the help of EVG’s 300-mm tools.

“ST is committed to accelerating the manufacturing of 3D TSV-based devices into high volume.” Says Gareth Bignell, program manager, 300-mm equipment selection, STMicroelectronics. “As such, we’re turning to trusted suppliers, like EVG, who can help us maintain our competitive edge by minimizing manufacturing risks, while increasing the speed of implementation and time to market.”

EVG has been actively involved in bringing this TSV technology to market commercialization. Key to this effort, the company is a founding member of the EMC-3D international consortium, which is chartered with developing the 3D market infrastructure by demonstrating a cost-effective, manufacturable, stackable TSV interconnection technology.

“We believe TSV technology holds tremendous potential and we are poised and committed to being a key player in this space,” said Paul Lindner, EVG’s executive technology director, citing this milestone order from ST as a testament to EVG’s ability to meet the chipmaker’s performance, uniformity and repeatability demands.

According to Lindner, a number of factors contributed to the company’s recent win with ST over the competition such as its NanoSpray photoresist coating processing capabilities for steep topographies, along with its IQ Aligner’s lithography backside alignment capabilities. EVG reports that the ST order also included its EVG150 Coater and EVG150 Developer.

EVG was named a finalist in this year’s Advanced Packaging Awards for its NanoSpray coating process.

by Debra Vogler, Senior Technical Editor, Solid State Technology

July 8, 2008 – In a pre-SEMICON West interview with SST, Ludo Deferm, IMEC’s VP of business development, described how R&D consortia will have to change the way they accommodate the inclusion of fabless and fab-lite companies in their R&D business model, as fewer companies are able to afford the move from 32nm manufacturing to 22nm, and beyond.

Scaling will still continue for those manufacturers that make complex systems at high volumes, e.g., microprocessors and memories, noted Deferm. “But those who make complex systems at small volumes will probably stick with 32nm, or use foundries who can provide 22nm for the more critical blocks,” he said. Fewer IDMs will manufacture at 22nm and 16nm, which means more work for foundries — and that has implications for materials and equipment suppliers, he noted, as well as for R&D centers.

For IMEC, the further turn toward the fabless/fab-lite/foundry model means it must further adapt its R&D agreements, to a model that is more compatible with foundries, observed Deferm. Meanwhile, fabless and fab-lite companies will also have to understand the complications and limitations of scaling technology, and many will likely partner with other companies that are able to scale past 32nm.

Deferm observed that it will take some time for the different companies to understand the different goals of the various parties that sign onto these expanded R&D programs. “We have to serve even more companies than we have in the past,” he said. Although IMEC has been working with foundries, those projects have primarily been focused on licensing and services, not so much R&D. Deferm sees the same kind of R&D model extension applying to IP providers. — D.V.

3D freedom, choices, risks drive IMEC’s design tool program

by Debra Vogler, Senior Technical Editor, Solid State Technology

Recognizing the lack of design tools that account for design in three dimensions, rather than just two, IMEC has established a 3D integration program to tackle the need. Ludo Deferm, VP of business development at IMEC, talked with SST in a pre-SEMICON West briefing about the necessity for its research partners to understand the impact of 3D technology and the added value of design.

Not only will there be new design rules, 3D technology provides opportunities for improving designs, such as the way power is handled, he said. “But these opportunities provide more flexibility for the designer, which also means there are more opportunities to choose the wrong path,” noted Deferm. “You have to know how to extend the EDA tools and the design methodologies with 3D.” IMEC’s design program will provide high-level simulation capabilities to ensure its partners understand the limitations of 3D design. — D.V.

It’s About Time


July 1, 2008

What do you do when work doesn’t leave a moment to spare? You take a break to gain a new perspective. So in early June, my daughter and I ventured to Cancun for the sole purpose of finding a bit of escape. Perhaps the sunshine, snorkeling, hiking, and history of this part of Mexico would offer the perfect place to refuel. Little did we know that the hurricane season had begun.

After a four-hour bus ride, we arrived at Chichen Itza to see the ancient pyramids in the jungle rain. It was amazing. When you see the carvings in stone and masks of Mayans, the serious eyes, slope from high forehead to nose without much of an indentation, and then look at those selling hand-carved masks along the pathways, it’s often the same face. The pyramid itself is a calendar piece with mathematical proportions of 365 steps, arranged for the sun to shine at angles as a sundial in shadows. There were 50,000 Mayans living in the Yucatan at one time. Their organization and knowledge for their time period is remarkable.

What’s happening in our industry can be disconcerting. SEMI has predicted that world fabs are forecasted to hit bottom in 2008, the return to strong profitability and growth in 2009. In many companies a downsizing trend has begun. Many of the SATS providers and OEMs have begun to rethink strategies for pursuing market-share expansion while concentrating more on competitive positioning and financial performance.

Some positive results are in evidence too. Rather than lose a competitive edge or miss out on the positive benefits of new technology, many packaging companies are forming consortia. For the first time in history, the overall capacity of volume fabs producing 300-mm wafers has surpassed those producing 200-mm wafers. That should result in lower cost flip chips and packages. Professors at U.S. colleges talk about the cooperative industry/university projects that continue to spark innovative ideas.

There’s no doubt that all things change over time. From a pyramid-size clock, we’re down to a wrist watch or Blackberry. And in business, time is money; a factor in measuring productivity, delivery time, and new product introduction time. In 3D packaging, the fourth dimension

Riding on recent advances in nano-fabrication technology, thin-film thermoelectric coolers (TF-TEC) have been developed with active material as thin as 10-20

June Names in the News


June 30, 2008

(June 30, 2008) It was a month for names in the news as acquisitions and evolving business strategies inspired executive appointments and reorganization; industry organizations added members and directors, and books got published. Company announcements came in from JP Sercel Associates, TRUMPF, Dage Precision Industries, ECD, Jordan Valley, Rogers Corp., Formfactor, Unisem Group, Mentor Graphics, and Alchimer.

******

J. P. Sercel Associates (JPSA) announces the opening of a customer service and support office in Malaysia to focus on the combined territories of Malaysia, China, and Singapore, and provide service, installations, and training, and will stock spare parts for customers of JPSA’s laser workstations for wafer processing and micromachining.

Chuan Ki (C.K.) Foo, a direct JPSA employee based in Penang will run the center. Foo holds a Diploma in Electronic and Mechanical Engineering Technology from the Silicon Institute of Technology, Penang, Malaysia. He previously served as Senior Field Service Engineer for the Malaysia installation of Besi Die Handling, Laurier & Datacon divisions.

******

James Rogowski was appointed managing director of TRUMPF Canada shortly after the company acquired the remaining shares of Advanced Fabricating Machinery, which serves the Canadian market as a sales and spare parts facility for TRUMPF products. Rogowski will reportedly manage day-to-day operations and all sales and service activity in Canada. Rogowski is a 10 year verteran of TRUMPF, serving in various positions, most recently as product manager of 2D laser machines and automation.

*******
The High Density Packaging User Group International, Inc. (HDP), a global non-profit cooperative research and development organization for the Electronics industry, announces that Huawei Technologies, Inc. has joined the organization as an Executive Member. Huawei will participate in HDP User Group’s technical programs, and will also have a seat on the Board of Directors. HDP is dedicated to “reducing the costs and risks for the Telecommunications and Computer industries when using advanced electronic packaging and assembly”. This international industry led group organizes and conducts R&D programs to address the technical issues facing the industry, including design, printed circuit board manufacturing, electronics assembly, and environmental compliance.

******

Dage Precision Industries reports that Hal Hendrickson, general manager, and national sales manager for the Americas was elected to the Surface Mount Technology Association’s (SMTA) Board of Directors. Hendrickson has been an active member of SMTA since 1991 and has been actively involved in the electronics industry since 1974. His goal in serving on the SMTA Board of Directors is reportedly to help the association achieve its full potential and success as a training and networking organization as well as to expand into new areas of global involvement.

*******

ECD of Milwaukie, OR, has selected Kroschewski Industrial Electronics (KIE) GmbH as the distributor of ECD’s full line of thermal profiling products in Germany and Austria. After the company announced it had become a full-line distributor at SMT/Hybrid/Packaging in Nuremberg, KIE GmbH is led by Jascha Kroschewski, who holds a Dipl.-Betriebswirt Geschaftsfuhrung degree. Previously with Peter Jordon GmbH for thirty-five years, Mr. Kroschewski is well known in the industry, and brings a wealth of experience to serve ECD’s customers across a wide range of applications.

*******

Metrology solution provider, Jordan Valley Semiconductor, Ltd., has tapped Meir Mimon as worldwide VP of sales and marketing. Mimon will lead Jordan Valley’s aggressive growth strategy, with a focus on enhancing worldwide customer support operations and increasing Jordan Valley’s market share in the thin film and materials characterization metrology market segments. The announcement follows Jordan Valley’s recent acquisition of Bede, effective April 14th, 2008. Bede supplies HRXRD (High Resolution XRD) metrology for the semiconductor and compound industries. Mimon joined Jordan Valley in January 2008 as the VP of Business Development, responsible for the Bede acquisition project ended in Apr 2008 when JV acquired the assets, IP’s and technology of Bede, UK. Previously, he served as the corporate sales director for KLA-Tencor’s metrology group and overlay division based in San Jose, CA.

******

Rogers Corporation recently appointed Michael D. Bessette, V.P. to lead its Advanced Circuit Materials Division (ACMD) in Chandler, Arizona. A 33-year veteran of Rogers, He comes to the ACMD from Rogers’ Durel Division, also located in Chandler. Previously, Bessette worked at Rogers’ R&D department in Connecticut, where he was responsible for new product development and business commercialization, and also in Japan, where he headed up Rogers’ joint venture with INOAC Corporation, which manufactures Rogers’ elastomer materials.
Robert Wachob, President and CEO of Rogers Corporation, says this appointment comes at a critical time as the company strives to accelerate growth in that division. Rogers ‘ ACM Division manufactures high performance laminates and thin dielectric circuit materials for use in high frequency applications in a variety of global industries, including wireless base station, defense/aerospace, automotive, high speed digital, and advanced chip packaging.

******

Formfactor’s board of directors appointed Mario Ruscev, currently president, as its next CEO. Ruscev, 51, will succeed Igor Khandros, 53, FormFactor’s founder, who will become executive chairman of the FormFactor board of directors. Khandros will succeed Jim Prestridge, 76, its current chairman, who will remain on the FormFactor board of directors and become its lead independent director. The changes will become effective at the beginning of the company’s fiscal third quarter of 2008. Speaking on behalf of the BOD, Prestridge ascertained that the Khandros and Ruscev are the right team to lead the company through its next stage of growth.

******

Earlier this month, Unisem Group announced the resignation of Bruno Guilmart, executive director and group CEO in order to pursue other interests. His resignation was accepted by the board of directors and took effect June 4 2008. C.H. Ang, group COO, will be taking over all of Guilmart’s responsibilities and will be leading Unisem moving forward. Unisem reportedly does not anticipate any additional changes to the group’s organizational structure, nor does the company anticipate disruptions its daily operations.

*******

Alchimer, the nanometric films for through-silicon via (TSV) metallisation company, has appointed Lenix as its representative in Korea. This exclusive agreement means Lenix is sole agent for Alchimer’s products in Korea. As such, the company’s formulations and process IP for its electrochemical deposition process will reportedly be available from Lenix. Lenix is owned and run by semiconductor industry veteran Sang-Sok Lee, president and CEO. Lee created Lenix earlier this year to focus on advanced 3D packaging and TSV technology. The company is also provides carrier tape as the final packing media of packaged ICs.

*******

Mentor Graphics Corporation announced the publication of a book written by Charles Pfeil, engineering director of Mentor’s Systems Design Division, entitled BGA Breakouts and Routing, Effective Design Methods for Very Large BGA. This publication reportedly explores the impact of dense ball-grid array (BGA) packages with high pin-count on PCB (printed circuit board) design, and provides solutions for inherent design challenges.

“Using a BGA is the most common method today for packaging a high pin-count or very dense application specific integrated circuits (ASIC) and field programmable gate arrays (FPGA). BGAs have been proved to be a reliable, cost-effective package while at the same time providing flexibility to address miniaturization and functional requirements,” said Pfeil. “However, as BGA density and pin count continue to increase, the designer’s ability to effectively design with the devices has not kept pace. Fortunately, significant advancements in PCB fabrication technology have enabled further miniaturization in the manufacturing process.”

These improvements, along with new software and design methods specifically for BGAs provide a means to successfully design using these devices.

June 18, 2008 — NEXX Systems, a provider of process equipment for advanced wafer-level packaging applications, will participate in IMEC’s Industrial Affiliation Program (IIAP) on 3D integration. IMEC is an independent non-profit research center in nanoelectronics and nanotechnology focusing on the next generations of chips and systems, and on the enabling technologies for ambient intelligence.

As a member of this program, NEXX Systems will install a Stratus S300-FX electrodeposition system at IMEC’s facility in Leuven, Belgium for joint research and development of the metallization of through silicon vias (TSVs) and micro-bumping. The TSVs and micro-bumps are fabricated with electrodeposition technology and play a key role in 3D integration.

“We are delighted to continue our partnership with NEXX Systems and are confident that the Stratus will give our partners leading-edge electrodeposition technology for 3D integration,” says Eric Beyne, program director of the Advanced Packaging and Interconnect Center at IMEC.

“3D integration is an exciting new technology that addresses the ever-increasing demands for smaller, more complex, electronic devices,” says Richard Post, NEXX’s CEO. “Our partnership with IMEC will enhance continuing efforts to develop robust, low cost electroplating solutions that will enable future products for consumer electronics as well as automotive, medical, and office networking applications.”

eG ViaCoat is the latest in Alchimer’s eGTM series of electrochemical coating processes, for the metallization of high aspect ratio through-silicon vias (TSVs) used in advanced 3D packaging applications. It reportedly produces conformal, thin, uniform, and adherent copper seed layers, even on resistive barriers. It is said to enables significant reductions in cost of ownership (CoO) compared to dry vacuum processes.

eG ViaCoat is based on Alchimer’s proprietary electrografting (eG) technology, an electrochemical process based on specific organic precursors enabling the initiation and growth of nanometric films on conductive or semiconducting surfaces. eG ViaCoat is suitable for all applications requiring Cu metallization of TSVs: high-density vias for 3D-ICs such as stacking of memories, medium and low-density vias for image sensors, heterogeneous components integration and system-in-package (SiP) applications.

eG ViaCoat demonstrates conformal sidewall and bottom coverage, even when deposited on discontinuous surfaces such as highly ‘scalloped’ TSV etch profiles. It is compatible with standard barrier materials, including, but not limited to, PVD, CVD and ALD deposited Ta, TaN, Ti, TiN, WN, Ru and bi-layers. Alchimer S.A. Massey, France www.alchimer.com

By Julia Goldstein, contributing editor
(May 22, 2008) San Jose, CA &#151 The “3D Integration North American Tour” came to San Jose on May 15 after stops in Durham, NC and Dallas, TX. The event, hosted by SUSS MicroTec, Surface Technology Systems (STS) and NEXX Systems outlined the current state of the art in through silicon vias (TSVs) and related technology. An overview by consultant Phil Garrou, Ph.D. of MCNC describing various process steps involved in 3D TSV technology led naturally into detailed presentations on processes and materials.

(May 22, 2008) SINGAPORE &#151 STAT ChipPAC hosted its inaugural Supplier Day, honoring eleven materials and equipment suppliers for outstanding contribution as key suppliers. The awards ceremony, held on May 13 in Singapore, recognized supplier achievements in 3 categories: outstanding overall performance, outstanding service, and special site outstanding service.

by Ed Korczynski, senior technical editor, Solid State Technology

Masaaki Kinugawa, GM of Toshiba’s Oita operations, discussed the tough challenges faced by fabs developing advanced processes today. Both process technologies and device technologies continue to increase in complexity, and costs rise proportionally. Alliances to share costs, such as the IBM-centric one for bulk CMOS to which Toshiba belongs, are essential to continue IC shrinks to the 32nm node.

While the core bulk CMOS process is common, each of the partners in the alliance develops different optional processes and technologies to serve each of their targeted SoC markets. For example, Toshiba has invested in FeRAM and MRAM embedded memory with logic, MEMS, and through-silicon vias (TSV) for die stacking as power differentiators. Other optional technologies could include eDRAM, RF-CMOS, and sensors.

Even with careful management of process and technology development through the use of partners and alliances, owning a profitable fab is still getting to be very difficult. In the past, one process node in an IDM fab could be used over 10 or more years to manufacture a series of profitable products such as first SoCs then image sensors and finally MCUs. As the industry moves to 32nm and beyond, the sharply escalating costs of both IC product development and fab equipment may combine to slow down the historic chip cost reduction trendline.

The total cost to develop a chip product — including all EDA functions as well as maskmaking — has been nearly doubling each node from 90nm to 65nm to 45nm. Moving on to 32nm is projected to raise costs only ~50% over 45nm, but the absolute numbers are now making design-teams pause to consider their choice of manufacturing node. Kinugawa predicted that neither Japanese fabless nor customers nor IDM-internal designers are prepared to jump to the next node — such that a “several year gap” will appear between the availability of 32nm node fab capacity and substantial demand!

Only products with very high projected volume can enjoy the benefit of early access to advanced processes. With fab setup costs soaring, even well established IDMs need strategic fabless customers to take up some of the capacity. Toshiba expects that the majority of the initial volume for its 32nm node and beyond fab technology will come from fabless companies, before the established product migration from SoC to MCU finally begins. With a lot of new device materials and novel device structures, any fabless company interested in 32nm node chips will have to work intimately with its foundry. As a major IDM, Toshiba is ready to provide anything from traditional IC foundry work to full ASIC turnkey service including design help starting at the gate-level netlist, Kinugawa said. The company also claims to have 1000 engineers “for IDM foundry service.”

In some cases, a large IDM like Toshiba will also be differentiated from pure-play foundries by special capabilities, such as MEMS, sensors, and 3D techniques based on TSVs, for example.

For 3D packaging, Toshiba has taken aggressive steps to develop cost-effective die-stacking technology. The current offering is 60μm pitch micro-bumps which can be combined with die-thinning, flip-chipping, and wire-bonding to stack three layers of silicon. By 2010, the plan is to have 60μm thin silicon chips with TSV stackable on a silicon interposer for system LSI with lower power consumption and higher performance. Toshiba claims to have developed models such that stacked dice can be simulated as one chip for thermal analysis, power integrity, IR drop, noise, and ESD.

Whether automotive customers who need long-term commitments or consumer electronics customers who need advanced processes, Japanese customers are said to prefer Japanese fabs run by Japanese companies, Kinugawa noted. High quality and quick delivery are mentioned as decision factors, and the IDM may sometimes be able to establish bi-directional business for mutual benefit. The IDM foundry model is based on choosing a small number of key customers, and then servicing them with technology capability from design through test, assembly, and packaging. — E.K.