Category Archives: 3D Integration

If the overflow of registered attendees standing in the hallway, craning their necks to hear what was being said inside the room was any indication, than the primary technology draw at this year’s IMAPS International Device Packaging Symposium was anything to do with 3D packaging technologies; and through silicon via (TSV) processes were clearly stars of the show. Even though the rest of the program featured sessions on the latest in MEMS, biomedical, flip chip, and wafer level and chip scale packaging &#151 all critical and current areas for advanced packaging &#151 the rooms dedicated to those sessions had plenty of seating available.

The AVIA 355-23-250 from Coherent, Inc. delivers over 8 watts of 355-nm output at repetition rates of 250 kHz and higher. The combination of high average power and high pulse repetition rate translates directly into high process throughput with minimal silicon microcracking, reportedly achieving high-speed IC die singulation with high yields.

by Bob Haavind, Editorial Director, Solid State Technology

March 11, 2008 – Progress toward 13.5nm extreme ultraviolet (EUV) lithography was covered by Gregory Denbeaux, assistant professor of nanoengineering, U. of Albany. Two types of sources, discharge produced plasma (DPP) and laser produced plasma (LPP) both currently work at low efficiency and generate large amounts of heat, and both require some type of debris mitigation. Power is still far below that needed for full production. EUV must be done in a very large vacuum chamber because the x-rays emitted by the target can’t penetrate air molecules. Current resists do not have sufficient sensitivity for the few photons that reach the wafer surface, so at 5 mJ/cm2 they currently operate close to the shot noise limit, Denbeaux said. Potentially there will be high line-edge roughness (LER) if the tools can not generate higher doses.

Defects could ruin the high reflectivity mirrors made of 80 alternating molybdenum/silicon layers, but so far SEMATECH has been able to stay on its target for defect reduction (see figure 1). Hydrocarbons contaminate the mirrors as well as the reflective mask and the optics, but keeping them out of the chamber is difficult because of outgassing from the resists. Some cleaning will be needed for hydrocarbon contamination, but oxygen or ozone are not good candidates because of potential oxidation. Atomic hydrogen cleaning is preferred instead, but this has not yet been well tested. Also, Denbeaux explained, there is no good way yet to monitor contamination on each mirror surface.

While much more power is desired, there is concern about heating as a result. Intense plasmas could distort mirrors and the collectors, and perhaps melt and fuse some of the molybdenum/silicon layers. To prevent this, he said, there needs to be better cooling behind the mask.

In spite of all the problems, Denbeaux said, EUV technology does work, although very far from a commercially acceptable level. He showed very good lines and spaces at 32nm and even below (see figs. 2, 3), and pointed out that AMD had successfully used EUV for the first metal layer of its Typhoon chip, as announced at the recent SPIE Advanced Lithography conference (see figure 4). Because of the need for double exposure/patterning at future nodes for 193nm tools, it turns out that if EUV targets can be reached in the next few years, it will provide a more cost-effective solution to advanced lithography — even though the tools might cost a cool $65 million each! — B.H.

Click here for more presentations from the SEMI breakfast: Gordon Starkey, a senior engineer in technical operations for IBM, explained how silicon-on-insulator (SOI) has made a transition from a niche to mainstream technology. And Sitaram Arkalgud, head of SEMATECH’s 3D interconnect program in Albany, discussed the expected evolution of through-silicon vias (TSVs) and 3D chip stacks for future electronics.

by Bob Haavind, Editorial Director, Solid State Technology

March 11, 2008 – Shrinking devices on an IC to increase density has been the industry’s primary means for following Moore’s Law for decades, but another route to higher density is going to 3D, pointed out Sitaram R. Arkalgud, director of SEMATECH’s 3D interconnect program. Already the industry is in Phase I of a trend toward 3D with packaging innovations, such as system-in-package (SiP) and package-on-package (PoP) approaches. But wire bonds on pads at the edges have been used for connections between chips. This requires long signal paths, slowing performance.

Much shorter signal paths could be provided by through-silicon vias (TSVs) that could be placed anywhere on each chip. This approach is already being used by Samsung with up to eight stacked die NAND flash or DRAM memory packages using TSVs — which is what Arkalgud called Phase II of the 3D transition. Instead of doing vias one at a time with a laser drill, they are done hundreds at a time using reactive-ion etching (RIE), and then copper plated. A big question about TSVs, according to Arkalgud, is the cost of the processing needed for etching the vias and plating through multi-layers of chips or wafers. Via widths might range from 1μm-50μm, with aspect ratios up to 10:1, which will be very hard to plate through. If copper-to-copper bonding is used, this can take several hours.

In Phase 3 of the 3D transition, there might be face-to-face bonding of chips which could make TSVs optional, Arkalgud explained, noting that Intel is taking this approach for an 80-core processor. If TSVs are used, they can be via-first, or backside via last approaches.

As TSV technology advances and becomes cost-effective (see figure 1), the industry can move to Phase 4 — multi-chip stacking and aggressive via pitch and diameter targets. Processes, including bonding and thinning, will become more “assembly-like,” he added. Cooling of the device stacks will be a problem, but a number of solutions are being explored, including using one layer as a cooling layer, adding microfluidic channels to carry off heat, or adding extra vias to enhance heat flow. Better modeling will be needed to determine the effectiveness of these various approaches.

One problem facing the industry, according to Arkalgud, is that many of these processes will overlap work done at a high-performance wafer fab and an assembly house, which might even be on different continents and operate with different cultures. Standards will be needed to allow convenient mix-and-match of various types of devices in either die-to-wafer or wafer-to-wafer stacks.

There are pros and cons to each of these approaches, Arkalgud explained (see figure 2). For wafer-to-wafer stacking to work, all die will have to be the same size and very high yield will be required to make sure all the die in a stack are good. If the chipmaker wants a heterogeneous stack, with flash, SRAM, DRAM, and microprocessors plus other devices, die sizes will be different and even wafer sizes may vary. This mix-and-match approach can be done with die-to-wafer stacking. He pointed out that while cost will be a deciding factor on whether the TSV approach is used, it rates as excellent for all other critical factors, such as performance, power, functionality, and time-to-market. The SiP approach would have lower performance, and the 2D, SoC approach would take a much longer time-to-market, for example.

The 3D approach also might be an enabler for combining other technologies with ICs, such as optoelectronics, MEMS, biosensors, and others.

Despite the benefits of 3D, Arkalgud explained that 3D technology can only advance through a wide collaborative effort across many parts of the industry. There are many different possible integration approaches and bonding methods, and there is no benchmarking methodology for comparing tool performance, for example. Also, there are gaps in design and testing methodologies. Many options must be narrowed to a few most attractive approaches for critical mass to develop and a necessary infrastructure to develop.

SEMATECH sees the need for a 3D roadmap, and is working with the International Technology Roadmap for Semiconductors to develop specifications for when certain levels of precision will have to be reached. — B.H.

Click here for more presentations from the SEMI breakfast: Gordon Starkey, a senior engineer in technical operations for IBM, explained how silicon-on-insulator (SOI) has made a transition from a niche to mainstream technology. And Gregory Denbeaux, assistant professor of nanotechnology at the U. of Albany, gave an overview of progress needed in EUV to make it suitable for high volume manufacturing.

by Bob Haavind, Editorial Director, Solid State Technology

March 11, 2008 – Until the mid-1990s, SOI was considered too costly except for a few specialized niche applications, according to Starkey. Then, because of some advantages of the technology, IBM decided to go to SOI wafers for high-end servers, one of its key products. A number of factors drove the decision, he said, including better quality, narrowing of cost differences between SOI and bulk wafers, and the move to innovation rather than scaling to drive performance.

As IBM moved to 130nm, it added desktop PC processors and some printer controllers to the devices made on SOI wafers. Then, at 90nm, IBM won the competition to make SOI-based processors for all three major game consoles (Nintendo’s Wii, Sony’s Playstation, and Microsoft’s X-Box).

As the industry moves to 65nm and then 45nm, digital cameras may go to SOI, especially for portable miniaturized video devices, such as for high-definition or streaming video signals — rich-media applications for which SOI is particularly well-suited, Starkey said. In the future, handsets may go to SOI chips as well. At 45nm, he explained that all ASIC (application-specific IC) devices made by IBM will be on SOI.

As features have shrunk, more and more complexity has been required to make devices on bulk silicon, Starkey noted, so SOI processing has become less complex in comparison, while the price difference has narrowed. In bulk, large shallow trench isolation gets narrower at the top, making processing difficult, whereas SOI devices automatically have isolation that avoids latchup. Isolation is particularly important for analog circuits, he pointed out. Sometimes analog circuit islands are surrounded by an SOI layer, reducing self-heating.

The lower junction capacitance of SOI means that devices dissipate less active power — so for the same leakage, an SOI device can achieve about a 30% performance advantage over bulk devices, Starkey said. It is also possible to turn the performance advantage into circuits about 25% smaller using 20% less power, he said. At the same performance level, leakage can be 4×-8× less with SOI. In some applications, it is also possible to lower the supply voltage to achieve a power improvement. The lower power means less cooling is required, which can lower packaging costs.

On-chip DRAM (eDRAM) cell size can be reduced with SOI, making faster and less costly embedded memory. In fact, according to Starkey, eDRAM is being considered for SRAM replacement, because SRAM’s require a larger 6-device cell.

An additional advantage of SOI, he explained, making it especially attractive to the military, is less susceptibility to soft errors.

There also is an advantage for high frequency applications, Starkey said. Current-mode logic (CML) used for high frequency circuits is inherently leaky, so if conventional CMOS circuits using SOI can be used instead, there will be far less leakage.

Starkey said that IBM does not see the advantage of SOI diminishing as the shrink continues, as some have suggested. Instead he sees increasing problems with bulk transistors because of a well proximity effect. A resist edge comes closer to the device with each succeeding generation, he explained, and scattering off this edge is a growing problem. — B.H.

Click here for more presentations from the SEMI breakfast: Sitaram Arkalgud, head of SEMATECH’s 3D interconnect program in Albany, discussed the expected evolution of through-silicon vias (TSVs) and 3D chip stacks for future electronics. Gregory Denbeaux, assistant professor of nanotechnology at the U. of Albany, gave an overview of progress needed in EUV to make it suitable for high volume manufacturing.

This intuitive cost-of-ownership (CoO) tool model is specifically designed to evaluate the cost of a given through-silicon-via (TSV) process flow. It has been developed using Excel so as to be widely exploitable and upgradable. This CoO tool will enable evaluation of the cost/wafer level for manufacturing TSVs using user inputs or pre-defined parameters. This cost analysis tool is dedicated to 3D IC manufacturing for defining and tuning fab parameters such as: number of wafers/year processed, global process yield, number of working days/year, operator cost/year, and engineer cost/year. The tool will provide precise descriptions on cleanroom (CR) class, CR maintenance cost ($/m

3D Packaging Processes


March 3, 2008

(March 5, 2008) — This article is the third in a series on 3D packaging technology, and summarizes information presented during a January 2008 webcast hosted by Advanced Packaging magazine. Participants were: Fred Roozeboom, Research Fellow, NXP Semiconductors and professor at TU Eindhoven; Kai Zoschke, Research Engineer for Fraunhofer IZM; and Thorsten Matthias, Director of Technology North America, EV Group.

By Paul A. Magill, Nextreme Thermal Solutions, Inc.

Tracking the future of TSV


February 21, 2008

by Ed Korczynski, Senior Technical Editor, Solid State Technology

Through-silicon vias (TSV) can be used to connect 3D multi-chip module stacks with improved performance and reduced timing delays. A new report by analysts at TechSearch International, [PDF file] Through Silicon Via Technology: The Ultimate Market for 3D Interconnect provides a forecast for millions of silicon wafers to be made with TSV in the year 2014. For the next few years, however, it is likely that image-sensors and memory chip stacks will be the major high-volume applications, building on the estimated less than 50,000 wafers to be fabbed with TSV this year according to TechSearch President Jan Vardaman.

The industry is now moving past the feasibility (R&D) phase for TSV technology and into the commercialization phase, where economic realities will determine which technologies are adopted. Low-cost fine via hole formation and highly reliable via filling technologies have been demonstrated; process equipment and materials are available. Global research organizations are looking at applications for TSVs including image sensors, flash, DRAM, microprocessors, FPGAs, and power amplifiers.

There is no question that 3D TSV will be adopted, but the timing for mass production depends on how the cost of the new technology compares with that of existing technologies. In particular, as confirmed by Vardaman, if there are only 2 silicon layers to be assembled it is generally more cost-effective today to use flip-chip with wire-bonders. Another 1 or 2 chip layers can be easily added to the bottom side of an interposer, still without the need for TSV.

…Click here to read the full text…

(February 13, 2008) Austin, TX — A new study reports that 3D through-silicon vias (TSV) will eventually be adopted, but the timing for mass production depends on how the cost of the new technology compares with that of existing technologies. Design, thermal, and test issues remain a barrier to TSV adoption in some applications, though progress is being made.

This article, the first in a series of three on 3D packaging technology, summarizes information presented during a November 2007 webcast produced by Advanced Packaging magazine. Participants were Jean-Christophe “J.C.” Eloy, founder and GM of Yole D