Category Archives: 3D Integration

Keeping it Cool

Back in 2008 we addressed 3D cooling activities [see PFTLE 43, "Keeping it cool in the dog days of summer"] looking a the activities at IBM Zurich, GaTech, and CALCE (U Md) as the groups especially active in this area.

Since then we have looked further at the liquid cooling activities of Bakir at GaTech [see IFTLE 83, "Orange County IEEE CPMT 3DIC Workshop"] and Brunschwiler at IBM Zurich [see "IBM to use water cooling for future 3D IC processors"] and the fact that one of the drivers for 2.5D is that it offers better thermal performance that current 3D stack solutions [ see IFTLE 97, "DATE in Dresden, Synopsys 3D EDA solution"]. For the most part, though, IFTLE has taken the position that thermal would not be the roadblock for 3DIC and that initial products would be ones where the thermal solution was not driving the technology.

Now that we are quickly approaching full commercial production of a number of products, it’s probably a good time to focus more on proposed thermal solutions for the future. To update yourself on where things stand, I suggest Herman Oprins’ article "Modeling and experimental characterization of hot spot dissipation in 3D stacks." He concludes that thermal management issues in these 3D stacks are one of the main challenges for 3D integration since the use of polymer adhesives with low thermal conductivity, the presence of interconnection structures, back end of line (BEOL), redistribution layers (RDL), and through-Si vias (TSVs) increases the complexity of the conductive heat transfer paths in a 3D stack.

Oprins concludes that hot spot power dissipation results in significantly higher temperatures in 3D stacked chips compared to the same power dissipation in single 2D chips. This temperature increase is mainly due to the reduced thermal spreading in the thinned dies on the one hand, and to the use of adhesives with low thermal conductivity for the vertical integration of the chips on the other hand. To limit the temperature increase in 3D-ICs, "too thin chips should be avoided" because the thinner the silicon substrate, the higher the thermal spreading resistance is in the case of hot spots. Simulations show that a minimum die thickness of 50

October 16, 2012 – SEMI has extended the call for papers for the 2013 China Semiconductor Technology International Conference (CSTIC) to October 22. Paper abstract guidelines are listed here, and SEMI says there remain "just a few openings" for proposed talks on semiconductor technology and manufacturing. Original and overview papers from integrated device manufacturers (IDMs), equipment/materials suppliers, and academic and research institutes are welcomed.

The CSTIC (March 17-18 in Shanghai), held in conjunction with SEMICON China (March 19-21), is the largest annual semiconductor technology conference for the industry in China. (Last year’s CSTIC featured 100 technical lectures, 300 speakers, and nearly 1000 attendees.) Confirmed plenary speakers for CSTIC 2013 are RPI prof and Nobel Laureate Ivar Giaever, and "father of SOI technology" Ghavam Shahidi, IBM Fellow and director of Silicon Technology at IBM.

The CSTIC program offers 10 symposia covering all aspects of semiconductor technology and manufacturing, including a just-announced new track covering "circuit design, system integration and applications." Other tracks include: device engineering and technology; lithography and patterning; dry & wet etch and cleaning; thin-film technology; CMP, wafer substrate polishing and post-polish cleaning; materials and process integration for device and interconnection; packaging and assembly; metrology, reliability and testing; emerging semiconductor technologies; and advances in MEMS and sensor technologies.

SEMI and ECS are the organizers along with China’s High-Tech Expert Committee (CHTEC) with co-sponsors IEEE, MRS, and the China Electronics Materials Industry Association.

October 16, 2012 – The Global Semiconductor Alliance (GSA) says it has formed a Technology Steering Committee to help address key business and technology areas of interest to its members, and "encourage the advancement and adoption of leading technology and practices."

The committee will meet quarterly to "provide general oversight and guidance to the GSA’s working groups, committees, and research and events, as it pertains to key technological trends and their implications on the technology ecosystem," according to the GSA. The committee also will be charged with keeping the GSA’s focus aligned with key technologies and practices having the most positive impact on its members. Topics range from the technologically specific such as 3D IC packaging (for which the GSA has had a working group since 2009) to broader themes such as taxation and education.

The steering committee is chaired by Open Silicon top exec Naveed Sherwani, and seats representatives from two dozen companies spanning the fabless, foundry, and equipment supplier sectors: Altera, Applied Materials, ASE, Amkor, Cadence, CSR, eSilicon, GlobalFoundries, IBM, IDT, Intersil, LSI, Microsemi, Open-Silicon, PMC-Sierra, Rambus, SanDisk, Silicon Labs, SMIC, Spreadtrum, SuVolta, Synopsys, and TSMC.

The Technology Steering Committee is expected to help companies across the semiconductor ecosystem "address business and technology concerns specifically, where they intersect and their implications in this industry," stated Jodi Shelton, co-founder and president of GSA. "The committee will support, encourage and promote entrepreneurship, as well as accelerate industry adoption of emerging technologies and practices that are most significant to GSA members and their constituents."

The first TSC meeting was held Aug 8 at Open Silicon in Milpitas, CA, site of all the quarterly meetings. The next one is scheduled for Nov. 7.

Update 10/16: Jodi Shelton summed up the reason and timing for the formation of this steering committee: "The participants within the Technology Steering Committee are all senior technical executives with tremendous visibility and insight into the trends of the industry. We simply want to leverage this visibility and insight." Forming a steering committee to oversee the GSA’s working groups helps "bring in fresh perspectives from a different angle" and keep momentum moving forward, she explained.

Takeaways from that inaugural TSC meeting were to decide on key areas of focus, key individual technology & broader topics toward which the TSC will be "steering" the GSA’s efforts:

– 2.5-3D. Technical readiness (e.g. EDA, equipment, I/O standards, etc.); supply chain optimization (e.g. foundries want complete ownership to guarantee yields, but others may want to add their own disintegrated portion of expertise); and collaborative innovation (who will create and own IPs/standards, profit and loss sharing).

– Beyond Moore. Roadmap challenges for 450mm wafer manufacturing (what the ecosystem needs to do to support this); technologies beyond CMOS and NAND; trends on cost and power; the effect of silicon convergence (integrating large systems, EDA challenges, what is the FPGA component, etc.); the roles of FinFETs and 3D wafers; how Beyond Moore can be effected with a limited number of players in fab development, and how this will effect fab development costs; will this drive further industry consolidation or opportunities for micro fabs; managing package equivalence and system costs, reference designs, software, support, etc.

– IP. How can a limited number of vendors enable more shuttle and support, process, non-essential IP; make finding the right IP easier — if it exists; packaging and transferring quality; verifying IP, making it portable and usable.

– More than Moore/Innovation in Legacy Nodes. What’s the solution for low-cost, heterogeneous integration for MEMS, simple analog blocks, and other drivers that may not necessarily scale to Moore’s Law? (e.g. 2D-2.5D-3D, which may or may not include TSVs) And how can the GSA’s working groups determine ways to improve efficiencies and innovations at the ≥90nm nodes, and leverage existing technology to support emerging markets?

October 12, 2012 – The advent of leading-edge semiconductor packaging technologies dictates efficient use of capital, and only the top-tier companies will have the financial wherewithal to develop required expertise and capacity. That means consolidation needs to happen in the semiconductor assembly and test services (SATS), according to a recent report from Gartner.

IDMs started moving packaging plants into the Asia-Pacific region in the 1980s, and by the early 1990s outsourced packaging had bloomed, and gained speed with the emergence of the fabless/foundry model, explains Gartner analyst Jim Walker in a recent report ("Competitive Pressures Will Bring Consolidation to the SATS Market"). Over the past 10 years outsourcing has accelerated with proliferation of customized, application-specific packaging demand, and today the market has quintupled since 1997 to $25B, with nearly all the 130 SATS companies still in the greater Asia-Pacific region (including Japan).

Right now the SATS market is on a 8% CAGR trajectory from 2011-2016, but growth on an annual basis is slowing, Walker notes. The top five SATS companies currently comprise 50% of the market and will expand to nearly 60% by 2012 — that’s five out of more than 130 suppliers. The top 20 SATS companies comprise more than three-fourths of the market.

Top 10 SATS companies in 2011, sales as a percentage of total market. (Source: Gartner)

Consolidation is not only inevitable, it is sorely needed. Several factors will push these firms together:

  • Slower growth, due to market saturation. Crossing the 50% outsourcing saturation mark in 2011 implies that the total market available for packaging services from IDM, OEM, and fabless companies is shrinking, and will be more tied to industry unit growth and new business sectors.

  • Increasing competition at leading-edge technology nodes, and in niche markets. The process node migration continues (28nm, 20nm, 14nm, eventually 10nm and below), as does increased demand for mobile devices, which together necessitate more packaging technology and capacity for capabilities including WLP, flip-chip, through-silicon via (TSV), and redistribution layers. Those who can stomach the capital requirements for these, will stay on top — and those who cannot will find themselves on the losing end.

    Similarly, as the outsourcing sector aligns to industry unit growth, SATS companies focusing on specific markets (e.g. memory) are more exposed to narrow, commodity-like and price-sensitive market forces. Such companies need to expand on their own into other markets, or consolidate with bigger and broader SATS companies. See recent expansion/divestment news from PTI, Power ASE, SPIL, and ChipMOS. (In fact this trend could spell the end of memory-specific packaging and test services market, Walker notes.)

  • Continued efforts by IDMs and OEMs to outsource backend processes. Technology investments and capacity additions are a hard sell when utilization rates are low (or aren’t at full strength). The proliferation of packaging options (Gartner cites >2000 unique packages) is forcing OEMs/IDMs to rethink sharing capital investments, deciding to leave it to the outsourced "experts."

  • Increasing importance of a China market strategy. Most top 10 SATS companies have at least one Chinese manufacturing facility, initially taking advantage of cost savings and incentives. But now, recognizing China’s swelling appetite for electronics components and systems, SATS firms want and need those domestic capabilities to satisfy demand. ASE, for example, has led the way in defining a strategy that straddles operations in both Taiwan and China, including $1.2B to build up operations in Shanghai and Pudong.

Continued emergence and development of wafer-based packaging process technologies requires both wafer fabrication and semiconductor packaging manufacturing equipment, processes, and expertise — meaning foundries can do some of them too, such as wafer bumping and underbump metallization. Similarly, 3D package stacking, embedded components, and system-in-package (SiP) devices require both processes and technologies for packaging and printed circuit board assembly — and technologies such as system-on-package will further blur these roles. SATS firms should expect to see increased competition from the foundry market, Walker notes. They also need to expand their services to include test capabilities, package design, and module offerings. And perhaps most importantly, they need to get virtual or vertical — develop an acquisition plan or partnerships/joint ventures with foundries, EMS/ODM firms, and/or materials and equipment companies, he advises.

October 10, 2012 – Nanium says it has shipped its 200 millionth embedded wafer-level ball grid array technology (eWLB) component, a milestone reached in less than two years. The achievement represents a 10% year-over-year productivity increase, and reflects full conversion to the company’s eWLB overmold technology that allows both thinner and more robust packages, according to the company.

The shipment milestone "demonstrates that eWLB technology is a robust low-cost solution delivering both high reliability and high yields for manufacturing advanced electronic products with high I/O density in a small form-factor," stated Armando Tavares, president of NANIUM

Four of the leading micro- and nanoelectronics regions in Europe are joining forces to form a cluster alliance called “Silicon Europe.” The four groups, Silicon Saxony (Dresden/Germany), DSP Valley (Belgium), Minalogic (Grenoble/France) and Point One (Eindhoven/Netherlands), will be cooperating in research, development and business expertise.

Together they represent about 800 research institutes and companies, which account for more than 150,000 jobs; among the companies are global market leaders such as Philips, NXP, Globalfoundries, Infineon, STMicroelectronics, Schneider Electric und Thales.

This is a three year effort, as shown in the diagram. “We want to set up a joint action plan that is organized between the four clusters,” said Frank Bösenberg, in charge of administration of Silicon Europe, speaking at a press conference in Dresden. “Not only this, in the third year, we also want to start implementing this action plan. It’s not only about creating paper, but doing some action. In addition to this, we want to involve if possible additional European players.”


 “Global competition is tough and investments into European microelectronics are declining”, says Jean Chabbal, Chief Representative and CEO at the French Cluster Minalogic (Grenoble/France). In 2007 only 10% of all worldwide investments into microelectronics, around 28 billion Euro, went to Europe, while about 48% went to Asia. Since 2000 Europe’s market share in the semiconductor industry has dropped from 21 to 16 percent, yet the European microelectronics sector still employs 135,000 people directly along with another 105,000 in its supplier industries. “Europe is home to a number of the world’s best known, and most active regions in the micro- and nanoelectronics industry and the semiconductor industry, more specifically. These clusters, established over many years, with strong consolidated structures from industry, research and local governments, serve all application fields of micro- and nanoelectronics and have access to the most advanced research and key competencies – the European micro- and nanoelectronics sector must take advantage of this leading position and further expand upon it. This is the only way for Europe to maintain its role as a world-renowned leader in technology research and development”, continues Jean Chabbal.

Silicon Saxony (Dresden) is a unique conglomeration of companies with know-how in micro- and nanoelectronics, photovoltaic, organic and printed electronics, energy efficient systems, communications technology and sensor networks. More than 300 cluster partners employ 48,000 people. 

At the cluster Minalogic (Grenoble) 204 cluster partners with more than 39,000 employees develop modern micro- and nanoelectronics and integrated system-on-chip technologies. Their work applies to the sectors energy efficiency, connectivity and mobility, health systems and traditional industries. 

Point-One (Eindhoven) connects 170 cluster partners, who jointly develop solutions for mechatronics, integrated systems, photonics and micro-and nanoelectronics. Their solutions apply to lighting systems, to semiconductor and photovoltaic production and also the mobility, logistics and security branches. 

The 75 partners of the technology cluster DSP Valley (Leuven) are focusing on the development of hardware and integrated software technology for digital signal processing and system-on-chip solutions. 

Silicon Europe calls for a European ICT-Summit

 “Our activities and plans will not end at national borders as they did before – Silicon Europe stands for the common interest of the European microelectronics industry”, explains Peter Simkens, Managing Director at the Belgian Cluster DSP Valley. “However, to be successful in the long run, Silicon Europe and European microelectronics need active political support. We are appealing to all national governments to increase the synchronization of their economic and innovation policy with the European Commission and its guidelines. In order to realize this we are calling for a European micro- and nanoelectronics summit, which – similar to the German IT summit – shall bring together leading actors and decision makers from the European Commission, the national governments and all relevant branch organizations and associations. The European economy needs to expand on its strengths now, if it wants to remain competitive in the global market for the long run.”

Transnational Cluster Alliance as a new impetus

“Silicon Europe stands for a new quality of an European industry policy”, says Thomas Reppe, General Manager of the German Cluster Silicon Saxony. “In close cooperation with regional development agencies and institutes we transfer the cluster concept of Saxony’s Research Cluster for Energy Efficiency ‘Cool Silicon’ – the strong cooperation across organizational and institutional borders – onto a transnational level. Through this new and strong cluster alliance we are securing not only Europe’s current know-how in production of KET relevant technologies, but we are also working together on a strategic technology roadmap, which can serve the European Commission as a template and development guide for future programs.”

Silicon Europe offers a platform for active exchange among the clusters and their nearly 800 members, including internationally leading corporations; more than 75 percent of all partners are small and medium sized businesses. By performing a detailed analysis of each of the four cluster’s main research topics and by synchronizing their activities, previously unused synergies are being utilized.

Europe 2020

By intensifying transnational cooperation of regional research-oriented competence clusters, Silicon Europe will make a substantial contribution to “Europe 2020”, the EU growth strategy for the coming decade. The program’s focus is the advancement of research and development as a basis for a modern and strengthened European society. “With their activities, the European Commission aims at a digital and resource-efficient development – for both of these core goals micro- and nanoelectronics are a decisive factor”, says Eelco van der Eijk, contact person for the high-tech industry at the Dutch Ministry of Economic Affairs.  One of the key words for these activities is ‘smart specialization’ – the EU’s control mechanism to tailor and efficiently distribute development funds in the European technology regions.

Michael Kretschmer, Vice-Chairman of the CDU Parliamentary Group at the German Bundestag, member of the German Bundestag and member of the Committee on Education, Research and Technology Assessment explains his support for the initiative: “The Europe-Cluster of the micro- and nanoelectronics sites is a very important signal for both German and European politics. Together and across national borders we have to ensure that this key technology still has a home in Europe in the future. In the past, European clusters seldomly worked together – luckily, this is going to change now. I appreciate the Silicon Europe initiative and wish for it to find numerous supporters and advocates also in the German Bundestag and the German government. The high-tech nation Germany can simply not forego these technologies that by enabling innovations in various industries create jobs and prosperity”.

 

 

October 2, 2012 – Sand 9, a Cambridge, MA-based developer of precision microelectromechanical systems (MEMS) timing technology for wireless and wired applications, is partnering with GlobalFoundries for high-volume manufacturing of its technology, which incorporates silicon-on-insulator (SOI) and through-silicon vias (TSV).

"Partnering with GlobalFoundries allows Sand 9 to meet heightened market demand for the highest-volume mobile applications, including handsets, tablets and other consumer electronics," stated Vince Graziani, CEO of Sand 9. "Our collaboration will ensure a stable, reliable supply chain for all of our customers in mobile as well as in wireline communications infrastructure, cellular base station, and test and measurement markets."

The deal also highlights GlobalFoundries’ MEMS design and manufacturing capabilities, pointed out Raj Kumar, SVP for the foundry’s 200mm business unit & GM of its Fab 7 facility in Singapore (formerly Chartered Semiconductor). "For Sand 9, we have established a very cost-effective and novel MEMS process technology platform integrated with polysilicon through-silicon vias (TSVs) for wafer-level packaging," he noted.

Also read:
– MEMS timing firm Sand 9 lands $3M investment from mobile gear giant Ericsson
– Intel Capital leads Sand 9 funding round, joins board

Examining a Sand 9-provided white paper (circa 2010) reveals more details about its "temperature-compensated crystal oscillator" (TCMO) technology. A silicon-based MEMS resonator is suspended and acoustically decoupled from a silicon substrate using a "special engineered substrate" (an SOI wafer), with a predefined cavity hidden in the handle silicon layer. Through-silicon vias are formed inside that SOI substrate, then the backside routing is prepared for final solder bumping. DRIE etch through the device silicon layer releases the resonator structure — having the buried cavity enables this release to be done "very fast and clean" using dry etching, the company explains, since no sacrificial layer or wet etching chemistry means one less time-consuming material removal process and it also eliminates stiction effects. The CMOS IC wafer and MEMS wafer are then bonded to create interconnects and hermetic seal around the MEMS resonator, followed by deposition of underbump metallization and solder bumps. Electrical and thermal interconnects are made during the bonding process; the TSVs are directly routed through to the IC, not the MEMS resonator.

MEMS oscillators accounted for less than 1% of the $6.3B timing devices market $6.3B in 2011, according to Semico Research, but the firm projects a sparkling ~86% compound annual growth rate (CAGR) for both MEMS oscillator sales and unit shipments over the next five years (2011-2016), mostly thanks to demand from smartphones.

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October 1, 2012 – Tezzaron Semiconductor is taking over SVTC Technologies’ wafer fab in Austin, TX, amid reports that the semiconductor/MEMS development organization is cutting back activities in Austin and in California — and perhaps shutting its doors entirely.

In a statement, the Naperville, IL-based 3D IC technology firm acknowledges that days ago SVTC "announced to customers and employees that the [Austin] plant would be closed and liquidated by month’s end." This confirms local reports that SVTC had filed notice with the State of Texas about imminent and permanent layoffs of more than a hundred workers at the former SEMATECH ATDF facility. One report further suggested that SVTC might consolidate its operations in Austin.

More bad news for SVTC may be afoot. Last week local reports surfaced that the group has filed similar notification to authorities in California. That report includes a copy of the actual filing with the Economic Development Department, which lists another 106 layoffs — among them the positions of CEO and CFO, and dozens of directors and managers.

Tezzaron processes some of its wafers at the SVTC Austin fab, and intends to expand the fab’s capabilities to support some of its specialized 3D steps that are currently done elsewhere, a Tezzaron official told SST. While the firm says it will continue to support all other processes and services currently offered at the site, its "main strategy is not changing; our focus is still 3D," the official explained. "This acquisition allows us to consolidate much of our processing in one US location while continuing the fab’s current business model."

SVTC Technologies — née Cypress Semiconductor’s Silicon Valley Technology Center — was spun off in early 2007 with VC/private equity backing, and later that year combined with SEMATECH’s ATDF in Austin, TX.

"This is the only facility of its kind on the continent. It supports product innovations for semiconductors, life sciences, clean energy, aerospace, and defense," stated J.T. Ayers, Tezzaron’s CEO. "When we became aware it might be shut down, we knew we had to work quickly to retain this highly valuable group of people and capabilities."

No terms of the Austin deal were offered, though Tezzaron says it should close within two weeks, during which time the fab will continue normal operations. The Austin fab will become a subsidiary of Tezzaron and be led by David Anderson, SVTC VP and former SEMATECH/ATDF director.

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The first working 3D NAND flash memory at sub-40nm feature sizes will be described by Macronix researchers at this year’s International Electron Devices Meeting (IEDM). They used vertical gates having horizontal channels to create a new architectural layout that dramatically decreases feature sizes in the wordline direction and improves manufacturability. The new architecture also enables the use of a novel “staircase” bitline contact formation method to minimize fabrication steps and cost. The result is an eight-layer device with a wordline feature size of 37.5nm, bitline feature size of 75 nm, 64 cells per string and a core array efficiency of 63%. The researchers say the technology not only is lower cost than conventional sub-20nm 2D NAND, it can provide 1 Tb of memory if further scaled to 25nm feature sizes. At that size the Macronix device would comprise only 32 layers, compared to 3D stackable NANDs with vertical channels that would need almost 100 layers to reach the same memory density.

A previously proposed 3D vertical gate NAND architecture.

An overview of the proposed architectural layout that is said to be an improvement.

 

A cross-sectional views of the new device.

 

TEM electron microscope views of the staircase bitline contacts.