Category Archives: Device Architecture

Future technologies based on the principles of quantum mechanics could revolutionize information technology. But to realize the devices of tomorrow, today’s physicists must develop precise and reliable platforms to trap and manipulate quantum-mechanical particles.

In a paper published Feb. 25 in the journal Nature, a team of physicists from the University of Washington, the University of Hong Kong, the Oak Ridge National Laboratory and the University of Tennessee, report that they have developed a new system to trap individual excitons. These are bound pairs of electrons and their associated positive charges, known as holes, which can be produced when semiconductors absorb light. Excitons are promising candidates for developing new quantum technologies that could revolutionize the computation and communications fields.

The team, led by Xiaodong Xu, the UW’s Boeing Distinguished Professor of both physics and materials science and engineering, worked with two single-layered 2D semiconductors, molybdenum diselenide and tungsten diselenide, which have similar honeycomb-like arrangements of atoms in a single plane. When the researchers placed these 2D materials together, a small twist between the two layers created a “superlattice” structure known as a moiré pattern — a periodic geometric pattern when viewed from above. The researchers found that, at temperatures just a few degrees above absolute zero, this moiré pattern created a nanoscale-level textured landscape, similar to the dimples on the surface of a golf ball, which can trap excitons in place like eggs in an egg carton. Their system could form the basis of a novel experimental platform for monitoring excitons with precision and potentially developing new quantum technologies, said Xu, who is also a faculty researcher with the UW’s Clean Energy Institute.

Excitons are exciting candidates for communication and computer technologies because they interact with photons — single packets, or quanta, of light — in ways that change both exciton and photon properties. An exciton can be produced when a semiconductor absorbs a photon. The exciton also can later transform back into a photon. But when an exciton is first produced, it can inherit some specific properties from the individual photon, such as spin. These properties can then be manipulated by researchers, such as changing the spin direction with a magnetic field. When the exciton again becomes a photon, the photon retains information about how the exciton properties changed over its short life — typically, about a hundred nanoseconds for these excitons — in the semiconductor.

In order to utilize individual excitons’ “information-recording” properties in any technological application, researchers need a system to trap single excitons. The moiré pattern achieves this requirement. Without it, the tiny excitons, which are thought to be less than 2 nanometers in diameter, could diffuse anywhere in the sample — making it impossible to track individual excitons and the information they possess. While scientists had previously developed complex and sensitive approaches to trap several excitons close to one another, the moiré pattern developed by the UW-led team is essentially a naturally formed 2D array that can trap hundreds of excitons, if not more, with each acting as a quantum dot, a first in quantum physics.

A unique and groundbreaking feature of this system is that the properties of these traps, and thus the excitons, can be controlled by a twist. When the researchers changed the rotation angle between the two different 2D semiconductors, they observed different optical properties in excitons. For example, excitons in samples with twist angles of zero and 60 degrees displayed strikingly different magnetic moments, as well as different helicities of polarized light emission. After examining multiple samples, the researchers were able to identify these twist angle variations as “fingerprints” of excitons trapped in a moiré pattern.

In the future, the researchers hope to systematically study the effects of small twist angle variations, which can finely tune the spacing between the exciton traps — the egg carton dimples. Scientists could set the moiré pattern wavelength large enough to probe excitons in isolation or small enough that excitons are placed closely together and could “talk” to one another. This first-of-its-kind level of precision may let scientists probe the quantum-mechanical properties of excitons as they interact, which could foster the development of groundbreaking technologies, said Xu.

“In principle, these moiré potentials could function as arrays of homogenous quantum dots,” said Xu. “This artificial quantum platform is a very exciting system for exerting precision control over excitons — with engineered interaction effects and possible topological properties, which could lead to new types of devices based on the new physics.”

“The future is very rosy,” Xu added.

Sigma Labs, Inc., a provider of quality assurance software under the PrintRite3D® brand, was named a member of the Manufacturing Technology Centre (MTC) located at Ansty Park, Coventry, UK. Membership of the MTC enables Sigma Labs to share and provide expertise and solutions for a number of the Centre’s projects and also network with the Centre’s existing members, including some of the UK’s leading aerospace companies.

The MTC was established as part of the UK government’s national manufacturing strategy with the aim of bridging the gap between academic discoveries and real-time industry innovation. It houses some of the most advanced manufacturing equipment in the world, providing integrated manufacturing system solutions for customers across sectors that include automotive, aerospace, rail, construction/civil engineering, oil & gas and defense.

John Rice, CEO of Sigma Labs, said, “The MTC manufacturing research center model uses public and private funding to bring academia and industry together, to pursue challenging, industrially relevant development projects. As a member of the MTC, Sigma Labs will extend its industry footprint further into the exciting research and commercialization in additive manufacturing today. With Europe at the forefront of many innovative and major developments in the metal AM industry, we believe this agreement, our second major research alliance with a European center of excellence, holds great promise for us and the future of AM. We look forward to interacting with the other member companies in the MTC, and particularly to collaborating with researchers at the National Centre for Additive Manufacturing to demonstrate the capabilities and potential of the PrintRite3D® INSPECT®technology.”

MTC technology director Ken Young said, “I am delighted to welcome Sigma Labs to the MTC community. Quality assurance in additive manufacturing is a critical topic that requires significant attention. Gaining insights into the part quality during the additive manufacturing build process reduces effort for post-build inspection and ultimately provides the foundation for closed loop process control for improved robustness. Sigma Labs’ advanced capabilities on this topic will provide expertise for a number of the MTC’s projects and network with our membership base, focusing on qualification and certification of the additive manufacturing process.”

Sigma Labs will install its PrintRite3D® INSPECT® In-Process Quality Monitoring and Control technology at the MTC’s National Centre for Additive Manufacturing and participate in various member-sponsored programs with a focus on qualification and certification of the additive manufacturing process.

PrintRite3D® INSPECT®, which comprises software for in-process inspection of metallurgical properties, uses sensor data and establishes in-process metrics for each product’s design specifications and metal. It provides manufacturing engineers with information in real time that can permit them to avert a part that is beginning to display discontinuities from going on to become a rejected part. INSPECT® also generates quality reports based on rigorous statistical analysis of manufacturing process data and allows for interrogation of suspect part data that can be used for process improvement and optimization.

The Electronic System Design Alliance, a SEMI Strategic Association Partner, today opened nominations for member company executives to serve on the ESD Alliance Governing Council for the next two-year term.

Elections, normally on a two-year cycle, were postponed in 2018 as the ESD Alliance became a SEMI Strategic Alliance Partner. During this cycle, up to nine members will be elected to a two-year term.

Current Governing Council members are:

  • Simon Segars, chief executive officer (CEO) of Arm Holdings
  • Lip-Bu Tan, president and CEO from Cadence Design Systems
  • Dean Drako, IC Manage’s president and CEO
  • Wally Rhines, CEO emeritus at Mentor, a Siemens Business
  • John Kibarian, president and CEO from PDF Solutions
  • Grant Pierce, CEO of Sonics
  • Aart de Geus, Synopsys’ chairman and co-CEO
  • Bob Smith, executive director of the ESD Alliance

Executives from member companies can nominate themselves or be nominated by someone from within a member company. Forms are available on the ESD Alliance website. Candidate statements will be posted on the website as they are received, with elections in mid-April. Results will be announced in May.

The Governing Council’s charter is to provide input and steer the direction of the organization. The ESD Alliance’s board of directors became the Governing Council when the ESD Alliance transitioned into SEMI as a SEMI Strategic Association Partner.

“Participating on the Governing Council offers executives a chance to help shape our industry, especially as the ESD Alliance’s global footprint expands and we increase our initiatives with the launch of ES Design West,” remarks Smith. “It’s a satisfying experience and we encourage executives from the electronic system and semiconductor design ecosystem to get involved.”

The Inaugural ES Design West

The ESD Alliance will host ES Design West co-located with SEMICON West 2019 at San Francisco’s Moscone Center, July 9-11. Dedicated to promoting the commercial successes of the Design and Design Automation Ecosystem™, ES Design West is the only event in North America that links the electronic system and semiconductor design community with the electronic product manufacturing and supply chain. For more information, visit the ES Design West 2019 website.

About the Electronic System Design Alliance

The Electronic System Design (ESD) Alliance, a SEMI Strategic Association Partner representing members in the electronic system and semiconductor design ecosystem, is a community that addresses technical, marketing, economic and legislative issues affecting the entire industry. It acts as the central voice to communicate and promote the value of the semiconductor design ecosystem as a vital component of the global electronics industry.

Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that Toshiba Memory Corporation has successfully used the Cadence® CMP Process Optimizer, a model calibration and prediction tool that accurately simulates multi-layer thickness and topography variability for the entire layer stack, to accelerate the delivery of its advanced 3D flash memory devices. With the Cadence solution in place, Toshiba Memory Corporation achieved 95.7 percent accuracy to silicon.

After conducting a thorough competitive evaluation, Toshiba Memory Corporation adopted the Cadence CMP Process Optimizer for its unparalleled feature set that addresses diverse layout topologies of array-based memory designs. The Cadence CMP Process Optimizer is based on a model-based approach versus a traditional, rules-based approach, which enabled Toshiba Memory Corporation to better predict complex, cumulative and long-range effects of chemical mechanical polishing (CMP) effects and CMP yield-limiting hotspots. Also, the Cadence CMP Process Optimizer allowed Toshiba Memory Corporation to perform simulations for the entire design stacks—both the transistor and routing layers—leading to improved accuracy. Toshiba Memory Corporation generated high-precision CMP models with the Cadence CMP Process Optimizer’s innovative capabilities. For more information on the Cadence CMP Process Optimizer, please visit www.cadence.com/go/ccpo.

“Advanced process technologies bring added complexities to the design process, and as a result, CMP effects have become more and more critical for us, particularly for our leading 3D flash memory solutions,” said Susumu Yoshikawa, technology executive, Memory Technology at Toshiba Memory Corporation. “We’ve been particularly impressed by the Cadence CMP Process Optimizer’s unparalleled capabilities, which enabled highly accurate modeling and analysis that we expect to improve product yield and accelerate the delivery of our flash devices.”

The Cadence CMP Process Optimizer offers feature-scale topography prediction and advanced reverse etch-back for accurate modeling and is part of the broader Cadence digital and signoff portfolio. From synthesis through implementation and signoff, the Cadence integrated full-flow digital and signoff tools provide a fast path to design closure and better predictability. The digital and signoff full-flow supports the company’s overall System Design Enablement strategy, which enables system and semiconductor companies to create complete, differentiated end products more efficiently.

Soitec (Euronext Paris), a designer and manufacturer of innovative semiconductor materials, today announced it is the first materials supplier to join the China Mobile 5G Innovation Center (“Center”), an international alliance chartered to develop 5G communication solutions for China, the world’s largest wireless communications market with 925M mobile subscribers. Both silicon and non-silicon engineered substrates, in which Soitec is the global leader, are essential in bringing to mass deployment 5G mobile communications for applications including self-driving cars, industrial connectivity and virtual reality.

Founded by China Mobile, the world’s largest operator, the Center aims to accelerate the development of 5G by establishing a cross-industry ecosystem, setting up open labs to create new products and applications, and fostering new business and market opportunities. As the first materials supplier to join the Center, Soitec brings its long-standing worldwide partnerships with R&D Centers, fabless semiconductor companies and foundries.

With ongoing investments and advances in capabilities, assets and SOI technology, Soitec’s RF portfolio is 5G-ready and designed to support deployment of 5G solutions across different regions. Soitec’s portfolio features cost-effective SOI and compound material substrates spanning advanced and established technology nodes optimized to balance performance, power efficiency and integration, in less space. Soitec will further support China Mobile through access to Soitec’s engineered substrate development ecosystem.

“As China Mobile works to bring 5G to market, Soitec’s participation in the China Mobile 5G Innovation Center is focused on accelerating the creation and delivery of market-leading 5G material solutions,” said Thomas Piliszczuk, Executive Vice President of Global Strategy for Soitec. “This is a unique opportunity for Soitec to engage with the world’s largest mobile operator and its ecosystem partners. Engineered substrates give foundries, fabless semiconductor companies and IDMs (integrated device manufacturers) the means to improve performance, power, area and cost (PPAC) while also enabling new applications.”

Soitec engineered substrates have been critical in deployment of 4G communication. RF-SOI material is used in 100 percent of smart phones manufactured today and its surface is growing with each new product generation. Also, FD-SOI brings unique RF performance, making it an ideal solution for many applications including mmWave communications such as 5G transceivers as well as enabling full RF and ultra-low-power computing integration for IoT.

SEMI, the global industry association serving the electronics manufacturing supply chain, today announced SEMI Works, a comprehensive program to attract, develop and retain the talent critical to the worldwide electronics industry’s continued innovation and growth. The holistic program is designed to improve the industry’s image and provide educational programs for all age groups across the education continuum.

“SEMI has made workforce development and talent advocacy a top priority and dedicated significant resources and expertise to tackle the issue,” said Ajit Manocha, SEMI president and CEO. “As the global industry association anchoring the $2 trillion global electronics industry and representing the end-to-end semiconductor supply chain, SEMI is uniquely positioned to address this problem. We look forward to forming partnerships in leading the way on behalf of our members to build the workforce of the future.”

SEMI Works leverages the SEMI association’s proven track record developing and delivering education and workforce development initiatives as well as its rich history of building public-private partnerships. Under the program, SEMI will establish scalable and sustainable education programs extending from grade-schoolers to adults, offering experiential learning and training programs linked to the skill sets the industry needs most.

“Attracting, training and retaining talent is a major priority for our industry, and we applaud SEMI for taking a lead in workforce development,” said Dan Durn, senior vice president and CFO of Applied Materials, Inc. “SEMI is in a great position to mobilize the right resources and drive the success of this important initiative.”

Leading SEMI Works is Mike Russo, vice president of Global Industry Advocacy at SEMI. Russo brings to bear his more than two decades of talent development experience working with the public and private sectors.

“The global electronics industry’s shortage of high-skilled workers will only become more severe as technology advances,” Russo said. “We need a highly skilled workforce throughout the supply chain to develop new technologies and bring these advances to market. SEMI Works™ will be anchored by both detailed competency models continually updated to support the industry’s rapidly evolving workforce needs and certified education and training aligned to these competencies. This systematic approach will enable us to develop the talent vital to the industry’s prosperity.”

With SEMI Works, SEMI is building on its growing suite of workforce initiatives and involving a consortium of member companies along with its strategic alliances. The program will expand to include public and private sector partners. Organizations interested in contributing to SEMI Works should visit the SEMI Works webpage for program manager contact details.

GOWIN Semiconductor Corp., an innovator of programmable logic devices, announces the release of GOWIN’s new EDA tool, YunYuan 1.9. With the release of this new toolchain, GOWIN will enable enhanced features and performance capabilities on their current and future FPGA product families.

EDA toolchains are becoming increasingly complex as FPGA applications are integrating more functions for the cloud and endpoint markets. To enable this complexity change, the new toolchain will include Gowin Synthesis, an enhanced front end logic synthesis tool designed and developed by the GOWIN EDA software team. It’s a significant milestone for GOWIN as the total toolchain is now completely designed in-house, allowing for quick quality improvements as well as product updates for customers time to market requirements. While GOWIN’s FPGA’s will be more optimized for IP, performance, and utilization using the new Yun Yuan 1.9 toolchain, the toolchain will additionally support the current Synopsys Synplify Pro synthesis tool already integrated.

“The development of the new synthesis tool is a major step for GOWIN,” said Alan Liu, Director of Software Development, GOWIN Semiconductor. “We can now make tool adjustments in real-time, enhancing the user experience.”

GOWIN EDA (YunYuan®) is an easy-to-use integrated design environment, providing design engineers with a one-stop solution. The complete GUI based environment covers FPGA design entry, code synthesis, place & route, bitstream generation, download, and online debugging of GOWIN FPGA’s on customer’s boards. The new toolchain also incorporates the following updated IP blocks:

Communication:

  • CAN2.0 & CAN-FD IP
  • High-Speed MIPI Interface (1:8 & 1:16 Gear Box)
  • Ethernet 10/100/1000Mhz MAC Controller & Interface to MII/RMII/GMII

Memory Controller:

  • pSRAM Controller IP

Microprocessor:

  • Configurable RISC-V (5-Stage-Pipeline) CPU & System IP

DSP:

  • FIR
  • NLMS Filter
  • FDAF – Frequency Domain Adaptive Filter
  • Cross-Correlation

North America-based manufacturers of semiconductor equipment posted $1.89 billion in billings worldwide in January 2019 (three-month average basis), according to the January Equipment Market Data Subscription (EMDS) Billings Report published today by SEMI. The billings figure is 10.5 percent lower than the final December 2018 level of $2.10 billion, and is 20.8 percent lower than the January 2018 billings level of $2.37 billion.

“January billings of North American equipment manufacturers declined 10 percent when compared to the prior month,” said Ajit Manocha, president and CEO of SEMI. “Weakening smartphone demand and high inventory levels are eroding capital equipment investments, especially by memory suppliers.”

The SEMI Billings report uses three-month moving averages of worldwide billings for North American-based semiconductor equipment manufacturers. Billings figures are in millions of U.S. dollars.
Billings
(3-mo. avg.)
Year-Over-Year
August 2018
$2,236.8
2.5%
September 2018
$2,078.6
1.2%
October 2018
$2,029.2
0.5%
November 2018
$1,943.6
-5.3%
December 2018 (final)
$2,104.0
-10.5%
January 2019 (prelim)
$1,896.4
-20.8%

Source: SEMI (www.semi.org), February 2019

SEMI publishes a monthly North American Billings report and issues the Worldwide Semiconductor Equipment Market Statistics (WWSEMS) report in collaboration with the Semiconductor Equipment Association of Japan (SEAJ). The WWSEMS report currently reports billings by 24 equipment segments and by seven end market regions. SEMI also has a long history of tracking semiconductor industry fab investments in detail on a company-by-company and fab-by-fab basis in its World Fab Forecast and SEMI FabView databases. These powerful tools provide access to spending forecasts, capacity ramp, technology transitions, and other information for over 1,000 fabs worldwide. For an overview of available SEMI market data, please visit www.semi.org/en/MarketInfo.

The advancement of the IC industry hinges on the ability of IC manufacturers to continue offering more performance and functionality for the money.  As mainstream CMOS processes reach their theoretical, practical, and economic limits, lowering the cost of ICs (on a per-function or per-performance basis) is more critical and challenging than ever. The 500-page, 2019 edition of IC Insights’ McClean Report—A Complete Analysis and Forecast of the Integrated Circuit Industry (released in January 2019) shows that there is more variety than ever among the logic-oriented process technologies that companies offer.  Figure 1 lists several of the leading advanced logic technologies that companies are presently using. Derivative versions of each process generation between major nodes have become regular occurrences.

Figure 1

Intel — Its ninth-generation processors unveiled in late 2018 have the code-name “Coffee Lake-S” or, sometimes called “Coffee Lake Refresh.” Intel says these processors are a new generation of products, but they seem to be more of an enhancement of the eighth-generation products.  Details are scarce, but these processors appear to be manufactured on an enhanced version of the 14nm++ process, or what might be considered a 14nm+++ process.

Mass production using its 10nm process will ramp in 2019 with the new “Sunny Cove” family of processors that it unveiled in December 2018.  It appears that the Sunny Cove architecture has essentially taken the place of the 10nm Cannon Lake architecture that was supposed to be released in 2019.  In 2020, a 10nm+ derivative process is expected to go into mass production.

TSMC — TSMC’s 10nm finFET process entered volume production in late 2016 but it has moved quickly from 10nm to 7nm.  TSMC believes the 7nm generation will be a long-lived node like 28nm and 16nm.

TSMC’s 5nm process is under development and scheduled to enter risk production in the first half of 2019, with volume production coming in 2020.  The process will use EUV, but it will not be the first of TSMC’s processes to take advantage of EUV technology.  The first will be an improved version of the company’s 7nm technology.  The N7+ process will employ EUV only on critical layers (four layers), while the N5 process will use EUV extensively (up to 14 layers).  N7+ is scheduled to enter volume production in the second quarter of 2019.

Samsung — In early 2018, Samsung started mass production of a second-generation 10nm process called 10LPP (low power plus). Later in 2018, Samsung introduced a third-generation 10nm process called 10LPU (low power ultimate) that provided another performance increase.  Samsung uses triple patterning lithography at 10nm.  Unlike TSMC, Samsung believes its 10nm family of processes (including 8nm derivatives) will have a long lifecycle.

Samsung’s 7nm technology went into risk production in October 2018.  The company skipped offering a 7nm process with immersion lithography and decided instead to move directly to a EUV-based 7nm process.  The company is using EUV for 8-10 layers at 7nm.

GlobalFoundries — GF views and markets its 22nm FD-SOI process as being complementary to its 14nm finFET technology.  The company says the 22FDX platform delivers performance very close to that of finFET, but with manufacturing costs the same as 28nm technology.

In August 2018, GlobalFoundries made a major shift in strategy by announcing it would halt 7nm development because of the enormous expense in ramping production at that technology node and because there were too few foundry customers planning to use the next-generation process.  As a result, the company shifted its R&D efforts to further enhance its 14nm and 12nm finFET processes and its fully depleted SOI technologies.

For five decades, there have been amazing improvements in the productivity and performance of integrated circuit technology.  While the industry has surmounted many obstacles put in front of it, it seems the barriers keep getting bigger.  Despite this, IC designers and manufacturers are developing solutions that seem more revolutionary than evolutionary to increase chip functionality.

A team of Cambridge researchers have found a way to control the sea of nuclei in semiconductor quantum dots so they can operate as a quantum memory device.

Quantum dots are crystals made up of thousands of atoms, and each of these atoms interacts magnetically with the trapped electron. If left alone to its own devices, this interaction of the electron with the nuclear spins, limits the usefulness of the electron as a quantum bit – a qubit.

Led by Professor Mete Atatüre, a Fellow at St John’s College, University of Cambridge, the research group, located at the Cavendish Laboratory, exploit the laws of quantum physics and optics to investigate computing, sensing or communication applications.

Atatüre said: “Quantum dots offer an ideal interface, as mediated by light, to a system where the dynamics of individual interacting spins could be controlled and exploited. Because the nuclei randomly ‘steal’ information from the electron they have traditionally been an annoyance, but we have shown we can harness them as a resource.”

The Cambridge team found a way to exploit the interaction between the electron and the thousands of nuclei using lasers to ‘cool’ the nuclei to less than 1 milliKelvin, or a thousandth of a degree above the absolute zero temperature. They then showed they can control and manipulate the thousands of nuclei as if they form a single body in unison, like a second qubit. This proves the nuclei in the quantum dot can exchange information with the electron qubit and can be used to store quantum information as a memory device. The findings have been published in Science today.

Quantum computing aims to harness fundamental concepts of quantum physics, such as entanglement and superposition principle, to outperform current approaches to computing and could revolutionise technology, business and research. Just like classical computers, quantum computers need a processor, memory, and a bus to transport the information backwards and forwards. The processor is a qubit which can be an electron trapped in a quantum dot, the bus is a single photon that these quantum dots generate and are ideal for exchanging information. But the missing link for quantum dots is quantum memory.

Atatüre said: “Instead of talking to individual nuclear spins, we worked on accessing collective spin waves by lasers. This is like a stadium where you don’t need to worry about who raises their hands in the Mexican wave going round, as long as there is one collective wave because they all dance in unison.

“We then went on to show that these spin waves have quantum coherence. This was the missing piece of the jigsaw and we now have everything needed to build a dedicated quantum memory for every qubit.”

In quantum technologies, the photon, the qubit and the memory need to interact with each other in a controlled way. This is mostly realised by interfacing different physical systems to form a single hybrid unit which can be inefficient. The researchers have been able to show that in quantum dots, the memory element is automatically there with every single qubit.

Dr Dorian Gangloff, one of the first authors of the paper and a Fellow at St John’s, said the discovery will renew interest in these types of semiconductor quantum dots. Dr Gangloff explained: “This is a Holy Grail breakthrough for quantum dot research – both for quantum memory and fundamental research; we now have the tools to study dynamics of complex systems in the spirit of quantum simulation.”

The long term opportunities of this work could be seen in the field of quantum computing. Last month, IBM launched the world’s first commercial quantum computer, and the Chief Executive of Microsoft has said quantum computing has the potential to ‘radically reshape the world’.

Gangloff said: “The impact of the qubit could be half a century away but the power of disruptive technology is that it is hard to conceive of the problems we might open up – you can try to think of it as known unknowns but at some point you get into new territory. We don’t yet know the kind of problems it will help to solve which is very exciting.”