Category Archives: Device Architecture

UltraSoC, the provider of embedded analytics for the RISC-V ecosystem, today announced full support within its embedded analytics architecture for Western Digital’s RISC-V SweRV Core™ and associated OmniXtend™ cache-coherent interconnect. The two companies have worked together to create a debug and on-chip analytics ecosystem that will support the requirements of both Western Digital’s internal development teams, and third parties choosing to adopt the SweRV Core for their own applications.

“Western Digital has proven to be a powerful driving force within the RISC-V ecosystem, with a visionary approach encompassing processors that are closely tailored to their target applications,” said Rupert Baines, UltraSoC CEO. “The SweRV concept is a compelling one, and we’re extremely proud to have been selected to support it at an early stage of its evolution.”

SweRV is an open source RISC-V core intended to accelerate development of open, purpose-built compute architectures for Big Data and Fast Data environments. Western Digital has taken an active role in helping to advance the RISC-V ecosystem, allowing it to create processors that are purpose-built for data-centric applications. Every storage product the company ships contains some kind of processor, and the company has committed to transitioning one billion of these cores to the RISC-V architecture.

UltraSoC launched the industry’s first – and still only – commercial RISC-V processor trace solution in June 2017, and is committed to supporting both standards-based and proprietary debug and analytics approaches. Trace functionality is a key tool for system developers, allowing the behavior of a program to be viewed in detail. UltraSoC’s embedded analytics technology is uniquely capable of supporting very powerful multicore system-on-chip (SoC) implementations, and enables seamless development and debug of systems containing multiple different types of processor: known as heterogeneous systems.

Western Digital’s RISC-V SweRV Core is based on a two-way superscalar design, with a 32-bit, nine-stage pipeline core that allows several instructions to be loaded at once and execute simultaneously. It is a compact, in-order core and is expected to run at around 5 CoreMarks/Mhz. Its power-efficient design offers clock speeds of up to 1.8Ghz on a 28nm CMOS process technology. Open sourcing the core is expected to drive development of new data-centric applications such as Internet of Things (IoT), secure processing, industrial controls and more.

pSemi Corporation today announced that its parent company and executive leadership has approved the recommendation of Chairman and Chief Executive Officer Jim Cable for an evolution of the company’s senior leadership structure.  Under the new structure, the company’s current VP of Product Marketing, Sumit Tomar, will succeed Jim as CEO, effective July 1, 2019.  Jim will continue as Chairman and Chief Technology Officer.  In addition, Jim will remain as global semiconductor R&D director for the parent company Murata Manufacturing.

“I am very proud of what we have accomplished here at pSemi Corporation.  In our over 30 years of innovation, we have consistently pushed the envelope of technology.  Now it is time to ensure we can continue to compete just as strongly in the future.  To that end, I have selected an internal candidate to succeed me as CEO,” says Jim Cable.  “I have watched Sumit in action, he knows our company and I am 100 percent committed to a successful transition for him and the company. We did an extensive external search and decided that the right choice was already here.”

Tomar is a 20-year industry veteran with a proven track record of bringing successful products to the market.  An expert in the RF ecosystem, Tomar has a solid understanding of RF products and has driven product execution from inception to production for hundreds of market-shaping products. From 2012 to 2016, Tomar served as the general manager of Qorvo’s wireless infrastructure business unit. In addition, he worked in RF product management at Texas Instruments, Sierra Monolithics and Skyworks. His product marketing experience spans 4/5G smartphone and radio access networks, automotive semiconductors, 802.11ax access points, SDN/NFV for data centers, and machine learning and artificial intelligence for mobile edge networks. In 2016, he co-founded C-RAN Inc., a startup that is developing a 5G RF system prototype. Tomar holds a Master of Science in electrical engineering and completed the StanfordExecutive Management Program. He joined pSemi Corporation in August of 2017 as the Vice President of Product Marketing.  “Sumit has been instrumental in managing our relationship with Murata to ensure that we support our parent company while continuing to innovate new products in the RF space,” continues Cable.

“Murata believes that successful succession planning requires careful consideration and attention to ensure a strong talent pipeline,” says Norio Nakajima, senior executive vice president and board member for Murata Manufacturing. “Jim’s selection of Sumit is an ideal example of outstanding succession planning.  I have had the pleasure of watching Sumit in action and I am convinced he is the right person to succeed Jim.”

Rice University integrated circuit (IC) designers are at Silicon Valley’s premier chip-design conference to unveil technology that is 10 times more reliable than current methods of producing unclonable digital fingerprints for Internet of Things (IoT) devices.

Rice’s Kaiyuan Yang and Dai Li will present their physically unclonable function (PUF) technology today at the 2019 International Solid-State Circuits Conference (ISSCC), a prestigious scientific conference known informally as the “Chip Olympics.” PUF uses a microchip’s physical imperfections to produce unique security keys that can be used to authenticate devices linked to the Internet of Things.

Considering that some experts expect Earth to pass the threshold of 1 trillion internet-connected sensors within five years, there is growing pressure to improve the security of IoT devices.

Yang and Li’s PUF provides a leap in reliability by generating two unique fingerprints for each PUF. This “zero-overhead” method uses the same PUF components to make both keys and does not require extra area and latency because of an innovative design feature that also allows their PUF to be about 15 times more energy efficient than previously published versions.

“Basically each PUF unit can work in two modes,” said Yang, assistant professor of electrical and computer engineering. “In the first mode, it creates one fingerprint, and in the other mode it gives a second fingerprint. Each one is a unique identifier, and dual keys are much better for reliability. On the off chance the device fails in the first mode, it can use the second key. The probability that it will fail in both modes is extremely small.”

As a means of authentication, PUF fingerprints have several of the same advantages as human fingerprints, he said.

“First, they are unique,” Yang said. “You don’t have to worry about two people having the same fingerprint. Second, they are bonded to the individual. You cannot change your fingerprint or copy it to someone else’s finger. And finally, a fingerprint is unclonable. There’s no way to create a new person who has the same fingerprint as someone else.”

PUF-derived encryption keys are also unique, bonded and unclonable. To understand why, it helps to understand that each transistor on a computer chip is incredibly small. More than a billion of them can be crammed onto a chip half the size of a credit card. But for all their precision, microchips are not perfect. The difference between transistors can amount to a few more atoms in one or a few less in another, but those miniscule differences are enough to produce the electronic fingerprints used to make PUF keys.

For a 128-bit key, a PUF device would send request signals to an array of PUF cells comprising several hundred transistors, allocating a one or zero to each bit based on the responses from the PUF cells. Unlike a numeric key that’s stored in a traditional digital format, PUF keys are actively created each time they’re requested, and different keys can be used by activating a different set of transistors.

Adopting PUF would allow chipmakers to inexpensively and securely generate secret keys for encryption as a standard feature on next-generation computer chips for IoT devices like “smart home” thermostats, security cameras and lightbulbs.

Encrypted lightbulbs? If that sounds like overkill, consider that unsecured IoT devices are what three young computer savants assembled by the hundreds of thousands to mount the October 2016 distributed denial-of-service attack that crippled the internet on the East Coast for most of a day.

“The general concept for IoT is to connect physical objects to the internet in order to integrate the physical and cyber worlds,” Yang said. “In most consumer IoT today, the concept isn’t fully realized because many of the devices are powered and almost all use existing IC feature sets that were developed for the mobile market.”

In contrast, the devices coming out of research labs like Yang’s are designed for IoT from the ground up. Measuring just a few millimeters in size, the latest IoT prototypes can pack a processor, flash memory, wireless transmitter, antenna, one or more sensors, batteries and more into an area the size of a grain of rice.

PUF is not a new idea for IoT security, but Yang and Li’s version of PUF is unique in terms of reliability, energy efficiency and the amount of area it would take to implement on a chip. For starters, Yang said the performance gains were measured in tests at military-grade temperatures ranging from 125 degrees Celsius to minus 55 degrees Celsius and when supply voltage dropped by up to 50 percent.

“If even one transistor behaves abnormally under varying environmental conditions, the device will produce the wrong key, and it will look like an inauthentic device,” Yang said. “For that reason, reliability, or stability, is the most important measure for PUF.”

Energy efficiency also is important for IoT, where devices can be expected to run for a decade on a single battery charge. In Yang and Li’s PUF, keys are created using a static voltage rather than by actively powering up the transistor. It’s counterintuitive that the static approach would be more energy efficient because it’s the equivalent of leaving the lights on 24/7 rather than flicking the switch to get a quick glance of the room.

“Normally, people have sleep mode activated, and when they want to create a key, they activate the transistor, switch it once and then put it to sleep again,” Yang said. “In our design, the PUF module is always on, but it takes very little power, even less than a conventional system in sleep mode.”

On-chip area — the amount of space and expense manufacturers would have to allocate to put the PUF device on a production chip — is the third metric where they outperform previously reported work. Their design occupied 2.37 square micrometers to generate one bit on prototypes produced using 65-nanometer complementary metal-oxide-semiconductor (CMOS) technology.

The research was funded by Rice University.

Researchers at CEA-Leti and Stanford University have developed the world’s first circuit integrating multiple-bit non-volatile memory (NVM) technology called Resistive RAM (RRAM) with silicon computing units, as well as new memory resiliency features that provide 2.3-times the capacity of existing RRAM. Target applications include energy-efficient, smart-sensor nodes to support artificial intelligence on the Internet of Things, or “edge AI”.

The proof-of-concept chip has been validated for a wide variety of applications (machine learning, control, security). Designed by a Stanford team led by Professors Subhasish Mitra and H.-S. Philip Wong and realized in CEA-Leti’s cleanroom in Grenoble, France, the chip monolithically integrates two heterogeneous technologies: 18 kilobytes (KB) of on-chip RRAM on top of commercial 130nm silicon CMOS with a 16-bit general-purpose microcontroller core with 8KB of SRAM.

The new chip delivers 10-times better energy efficiency (at similar speed) versus standard embedded FLASH, thanks to its low operation energy, as well as ultra-fast and energy-efficient transitions from on mode to off mode and vice versa. To save energy, smart-sensor nodes must turn themselves off. Non-volatility, which enables memories to retain data when power is off, is thus becoming an essential on-chip memory characteristic for edge nodes. The design of 2.3 bits/cell RRAM enables higher memory density (NVM dense integration) yielding better application results: 2.3x better neural network inference accuracy, for example, compared to a 1-bit/cell equivalent memory.

The technology was presented on Feb. 19, at the International Solid-State Circuits Conference (ISSCC) 2019 in San Francisco in a paper titled, “A 43pJ/Cycle Non-Volatile Microcontroller with 4.7μs Shutdown/Wake-up Integrating 2.3-bit/Cell Resistive RAM and Resilience Techniques”.

But NVM technologies (RRAM and others) suffer from write failures. Such write failures have catastrophic impact at the application level and significantly diminish the usefulness of NVM such as RRAM. The CEA-Leti and Stanford team created a new technique called ENDURER that overcomes this major challenge. This gives the chip a 10-year functional lifetime when continuously running inference with the Modified National Institute of Standards and Technology (MNIST) database, for example.

“The Stanford/CEA-Leti team demonstrated a complete chip that stores multiple bits per on-chip RRAM cell. Stored information is correctly processed when compared with previous demonstrations using standalone RRAM or a few cells in a RAM array,” said Thomas Ernst, Leti’s chief scientist for silicon components and technologies. “This multi-bit storage improves the accuracy of neural network inference, a vital component of AI.”

Mitra said the chip demonstrates several industry firsts for RRAM technology. These include new algorithms that achieve multiple bits-per-cell RRAM at the full memory level, new techniques that exploit RRAM features as well as application characteristics to demonstrate the effectiveness of multiple bits-per-cell RRAM at the computing system level, and new resilience techniques that achieve a useful lifetime for RRAM-based computing systems.

“This is only possible with a unique team with end-to-end expertise across technology, circuits, architecture, and applications,” he said. “The Stanford SystemX Alliance and the Carnot Chair of Excellence in NanoSystems at CEA-Leti enabled such a unique collaboration.”

GLOBALFOUNDRIES today announced that the company’s mobile-optimized 8SW RF SOI technology platform has delivered more than a billion dollars of client design win revenue since its launch in September 2017. With yields and performance exceeding client expectations, 8SW is enabling designers to develop solutions that offer extremely fast downloads, higher quality connections and reliable data connectivity for today’s 4G/LTE Advanced operating frequencies and future sub-6 GHz 5G mobile and wireless communication applications.

As the industry’s first 300mm RF SOI foundry solution, 8SW delivers significant performance, integration and area advantages, with best-in-class low-noise amplifier (LNA) and switch performance which all together improve integration solutions in the front-end module (FEM). The optimized RF FEM platform is tailored to accommodate aggressive LTE and sub-6 GHz standards for FEM applications, including 5G IoT, mobile device and wireless communications.

“At Qorvo, we continuously expand upon our industry-leading RF portfolio to support all pre-5G and 5G architectures, as such we require the best available technologies to enable us to deliver top-notch solutions with the broadest range of connectivity in sub-6 GHz and mmWave 5G,” said Todd Gillenwater, Qorvo CTO. “GF’s 8SW technology delivers a mix of performance, integration and area advantages in FEM switches and LNAs, giving us a great platform for our world-class products.”

“As new high-speed standards, including 4G LTE and 5G, continue to grow in complexity, innovation in RF Front End radio design must continue to deliver performance commensurate with growing network, data and application demands,” said Bami Bastani, senior vice president of business units at GF. “GF continuously builds on our extensive RF SOI capabilities that are providing our clients a competitive market advantage with first time design success, optimal performance, and the shortest time to market.”

According to Mobile Experts, the mobile RF front-end market is estimated to reach $22 billion in 2022, with a CAGR of 8.3 percent. With more than 40 billion RF SOI chips shipped thru 2018, GF is uniquely positioned to deliver an expanding RF portfolio for a broad range of high-growth applications such as automotive, 5G connectivity and the Internet of Things (IoT).

“Radio complexity promises to increase for both sub-6 GHz and mmWave, driving tight integration of multiple RF functions,” said Joe Madden, Principal Analyst at Mobile Experts. “The market needs RF solutions with high efficiency and linearity performance, but also using scalable processes on large wafers. GF has established an RF SOI process that will enable longer-term market expansion.”

GF combines legacy RF expertise and the industry’s most differentiated RF technology platform spanning advanced and established technology nodes, to help clients develop 5G connectivity solutions for next-generation products.

GF will present its 5G-ready RF solutions with industry experts at MWC Barcelona on February 25 at the NEXTech Labs Theater, in the Fira Gran Via Convention Center, in Barcelona Spain. For more information, go to globalfoundries.com.

Soitec (Euronext Paris), a designer and manufacturer of innovative semiconductor materials, and Shanghai Simgui Technology Co., Ltd. (Simgui), a Chinese silicon-based semiconductor materials company, jointly announced today an enhanced partnership and an increase in annual production capacity of 200mm silicon-on-insulator (SOI) wafers from 180,000 to 360,000 at Simgui’s manufacturing facility in Shanghai, China, to better serve the growing global market for RF-SOI in mobile and Power-SOI products.

Since signing their original licensing and technology transfer agreement in May 2014, the companies have achieved high quality standards with Simgui mastering Soitec’s Smart Cut(TM) proprietary process to deliver world-class RF-SOI and Power-SOI products. Simgui’s strategic partnership with Soitec allows them to use the same tools and processes to deliver the same products meeting the same specifications.

This ramp up in production is a direct result of the close collaboration and customer focus of both partners to deliver high quality SOI products at high volume. To further advance this mission,  Simgui and Soitec have redefined their original financial agreement and specific roles regarding the 200 mm wafers produced by Simgui. Simgui will focus on SOI wafer manufacturing and Soitec will manage worldwide product resale. To meet increasing worldwide demand for 200mm SOI in response to the growing market for RF-SOI used in mobile front-end modules (FEM) and for Power-SOI used in automotive and consumer electronics, Simgui has invested in their Shanghai fabrication line to offer customers this increased production capacity. The fab is production ready, having been qualified by multiple key customers inside and outside China.

“We are very pleased to continue our long-standing history and manufacturing partnership with Simgui to secure 200 mm capacity for our customers in markets where RF-SOI is today a standard for RF FEM for 4G & 5G and Power-SOI shows strong growth,” said Dr. Bernard Aspar, Soitec’s Executive Vice President, Communications and Power Business Unit. “Soitec and Simgui are committed to serve this industry with the right level of capacity and product quality.”

“Through our industrial collaboration with Soitec, Simgui has proven the robustness and high-volume scalability of Soitec’s Smart Cut technology and we are pleased to announce this new step in our relationship and increase in production capacity to serve our existing and future customers,” said Dr. Jeffrey Wang, Simgui’s Chief Executive Officer. “China has design, wafer manufacturing and good momentum in the IC industry. We are committed to our strategic partnership with Soitec to keep advancing SOI as China’s key differentiator.”

A ride on the business cycle


February 19, 2019

By Walt Custer

Global growth slows in fourth quarter

World electronic industry growth moderated (or contracted) in many sectors in late 2018.  Compare Chart 1 (3Q’18 vs.3Q’17) to Chart 2 (4Q’18 vs.4Q’17). The length and color of the bars tell the story. The semiconductor industry felt more of a fourth-quarter slowdown than the end markets.  Semiconductor-related products are typically much more volatile than the electronic equipment markets they serve.

In the third quarter of 2018 SEMI equipment shipments were up 10.6 percent and semiconductors grew 15.2 percent compared to the same quarter in 2017. By comparison, in 4Q’18 SEMI capital equipment shipments declined 1.6 percent and semiconductor shipments rose only 0.6 percent. For the month of December 2018 alone the results were even more sobering – SEMI equipment down 8.9 percent and semiconductors down 9.1 percent.

Such are the business cycles in the global electronics industry!

Electronic equipment, semiconductors and SEMI equipment – Historical growth comparisons

Chart 3 compares the quarterly growth of “end market” equipment to semiconductors and SEMI capital equipment for 2013 through 2018. Notice the much higher volatility of SEMI equipment in the peaks and troughs of the business cycle.

Leading indicators

Predicting the future performance of our very volatile electronics business cycle is an important challenge. Taiwan wafer fab sales and Purchasing Manager Indices are two useful tools.

Wafer foundries

Chart 4 compares the composite monthly sales of 14 Taiwan-listed wafer fabs to global semiconductor sales. The foundry composite predicts a further decline in chip sales short term.  Taiwan-listed companies report their monthly revenues about 10 days after month-close, so they can be a very timely indicator of industry performance.

Chart 5 compares the 3/12 growth of these wafer foundries to global semiconductor and SEMI equipment shipments. The data point to further slowing ahead.

This leading indicator methodology can be useful in forecasting individual company sales. For details contact [email protected].

Walt Custer of Custer Consulting Group is an analyst focused on the global electronics industry.

Source: SEMI Blog

UltraSoC today announced a significant extension of its embedded analytics architecture, allowing designers and innovators to incorporate powerful data-driven features into their products. Developers in the automotive, storage and high performance computing industries can now integrate even more sophisticated hardware-based security, safety and performance tuning capabilities within their products, as well as reaping substantial time-to-market and cost benefits of using UltraSoC in the system on chip (SoC) development cycle.

The new features allow SoC designers to build on-chip monitoring and analytics systems with up to 65,000 elements, allowing seamless support for systems with many thousands of processors. Future iterations will allow even higher numbers of processors for Exascale systems. In addition to this dramatically improved scaling capability, new System Memory Buffer (SMB) IP allows the embedded analytics infrastructure to handle the high volumes of data generated by multicore systems, and to cope with “bursty” real-world traffic.

The new UltraSoC architecture is capable of monitoring effectively unlimited numbers of the internal building blocks that make up the most complex SoC products – and to analyze the impact on system-level behavior of the interactions between them. Such heterogeneous multicore chips are becoming increasingly common, particularly in enabling the artificial intelligence and machine learning technologies required in leading edge applications such as driverless cars.

Dave Ditzel, Founder and CEO of Esperanto, commented: “Esperanto’s mission is to enable the most energy-efficient high-performance computing systems for artificial intelligence, machine learning and other emerging applications. That requires us to put over a thousand RISC-V processors and AI/ML accelerators on a single chip; UltraSoC’s ability to match that level of scaling with monitoring, analytics and debug capabilities is a vital enabler for our business.”

UltraSoC CEO, Rupert Baines, said: “Our solutions are unique in the market in their ability to deal with multiple heterogeneous processors, standard and proprietary bus structures and even custom logic. This dramatic extension of our architecture takes us even further ahead of traditional solutions – both in the debug and development arena, and in allowing our customers to incorporate in-life monitoring capabilities to ensure security, functional safety and real-world performance optimization.”

UltraSoC’s system-level monitoring and analytics capabilities extend beyond the chip’s core processing components to all parts of the system – which may include thousands of IP blocks and subsystems, buses, interconnects and software. The new features within the UltraSoC architecture allow chip designers to deploy tens of thousands of monitoring and analytics modules within a single infrastructure. By providing an integrated, coherent analysis of the behavior of the system, UltraSoC significantly reduces the development burden for next-generation machine learning and artificial intelligence applications, as well as allowing the implementation of innovative product features such as hardware-based security and functional safety.

Extension of the UltraSoC architecture to encompass effectively unlimited monitoring capabilities helps developers to address the problems of systemic complexity which are among the most pressing issues faced by the electronics industry today. In addition to the sheer size of modern SoCs, machine learning and artificial intelligence algorithms are often inherently non-deterministic: because they devise their own ways of solving problems by ‘learning’, it is impossible for the system’s original designer to predict how they will behave in the final application. In-life monitoring of the chip’s behavior is therefore the only way of getting a true picture of what is going on inside the chip, and the wider system.

The complex interactions between multiple hardware blocks, firmware and software within SoCs have already made real-time in-life monitoring an indispensable tool for SoC designers. Changes in design approaches are also making system-wide monitoring more necessary than ever. Agile software development and ad hoc programming practices inherently require high-granularity visibility of the real system. Similarly, system hardware and software may not be ‘architected’ in the traditional sense: again, engineers need clear visibility of the run-time behavior of their systems.

eSilicon, a provider of FinFET ASICs, market-specific IP platforms and advanced 2.5D packaging solutions, announced today the achievement of multiple milestones related to the company’s growth in the tier one FinFET ASIC market, serving high-bandwidth networking, high-performance computing, AI and 5G infrastructure.

Critical requirements to serve these markets include leading-edge, high-performance, differentiating semiconductor IP that is validated in advanced process nodes, a track record of successful design and fabrication of complex, FinFET-class ASICs and expertise in the design and manufacture of 2.5D package assemblies, including the integration of HBM memory stacks.

In the fall of last year, eSilicon announced availability of its neuASIC™ IP platform for AI ASIC design. The innovative IP platform includes an HBM2 PHY and AI mega/giga cells, including a convolution engine and accelerator builder software, all verified in 7nm technology. In that same time frame, the company announced that its 56G long-reach 7nm DSP SerDes was available for licensing.

In January, 2019, eSilicon announced a new high-performance test system to facilitate customer validation of its SerDes IP. At the recent DesignConshow, eSilicon demonstrated the new test system and its SerDes driving a five-meter copper cable at 56Gbps with very low error rates. Several customer engagements are underway with this SerDes IP, and customer feedback is validating its best-in-class capabilities. Also in January, eSilicon announced the formation of a technical advisory board for its AI initiatives staffed by three prominent technologists from academia and industry.

The company is in active production bring-up with two FinFET designs, including 2.5D technology utilizing its HBM2 PHY. All performance parameters are being met and both designs are on track to achieve full-scale production this year. One of the designs represents the largest ASIC eSilicon has ever built. It is believed to be the largest chip the foundry has ever produced as well.

“Our customers demand best-in-class IP, advanced ASIC and packaging expertise and the resources and technical depth to facilitate production bring-up of the final device,” said Hugh Durdan, vice president of strategy and products at eSilicon. “I am pleased to say we are delivering on all fronts. Recently, a tier one customer reported that they were usually quite critical of all IP. They went on to say they could find nothing to criticize after detailed evaluation of our SerDes.”

eSilicon will be presenting “A Sub-250mW 1-to-56Gb/s Continuous-Range PAM-4 42.5dB IL ADC/DAC-Based Transceiver in 7nm FinFET” at ISSCC in San Francisco on February 18. The company will be demonstrating its SerDes live at ISSCC that day as well. You can also find eSilicon at OFC in San Diego from March 5-7 (booth #5416), where the company will present two high-speed SerDes demonstrations and a demonstration if its HBM2 PHY.

During IBM THINK 2019, IBM’s annual conference focused on technology and business, Samsung SDS announced it is continuing its collaboration with IBM in support of advancing Hyperledger Fabric, an open source cross-industry blockchain technology, with recent code contributions, research and a new white paper.

As a contributor to Hyperledger Fabric, Samsung SDS is working to improve fabric capabilities and actively contributing its new “Accelerator” code to the open source community. The new code is expected to significantly improve Hyperledger Fabric performance for specific use cases.

Samsung SDS is also making a new white paper available, “Accelerating Throughput in Permissioned Blockchain Networks,” co-written by IBM. The paper validates the applicability of Accelerator to Hyperledger Fabric, provides a roadmap and also illustrates performance improvement in terms of transactions per second. A copy of the white paper and the Innovation Sandbox environment is now available for external developers to test. (https://github.com/nexledger/accelerator)

While this technical initiative is being rigorously validated from the open source Hyperledger community, Samsung SDS will prepare to become IBM’s key go-to-market reseller partner of IBM Blockchain Platform in Korea.

Ted Kim, Vice President, Blockchain Team from Samsung SDS America has been named to the IBM Blockchain Board of Advisors. Additionally, during the IBM Think Conference in San Francisco, Kiwoon Sung, Head of Blockchain Research Lab, Samsung SDS, will discuss the company’s blockchain innovation efforts at a session entitled, “New Blockchain Solutions emerging from the IBM Blockchain ecosystem.”

Hyperledger is an open source collaborative effort created to advance cross-industry blockchain technologies. It is a global collaboration including leaders in finance, banking, Internet of Things, supply chains, manufacturing and Technology. The Linux Foundation hosts Hyperledger under the foundation. To learn more, visit: https://www.hyperledger.org/.