Category Archives: Materials and Equipment

by Bob Haavind, Editorial Director, Solid State Technology

Over 1600 technologists gathered in Washington, DC, to explore a wide range of innovative ideas at the 2007 International Electron Devices Meeting (IEDM). Boosting performance as the shrink heads below 45nm was the goal of many new CMOS-based schemes. There were 237 papers from all over the globe, about a third of the 695 submitted.

While current mainstream CMOS approaches, using strain engineering and metal/high-k dielectric gates, were covered extensively, there were also a wide range of further out alternatives, suggesting that darts had been tossed at periodic table charts all over the world.

Germanium and silicon germanium (SiGe) were predominant, but there were may other devices incorporating III-V compounds, metal source and drain, and even hints of future circuitry based on carbon rather than Si or Ge. Carbon-based nanoelectronic technology using graphene even won a catchy new name: “pionics.”

A very promising demonstration of how compound semiconductor devices might be integrated onto a silicon substrate was presented by a group from Intel and IQE (Bethlehem, PA). An enhancement-mode quantum well (QW) transistor using indium-gallium-arsenide InGaAs was heterogeneously integrated onto silicon using a composite buffer only 1.3μm thick. The QFET is very promising for high-speed, low-power logic due to high electron mobility and low leakage. This seamless integration of a high-performance QFET suggests that logic blocks of such devices could be coupled with mainstream SiCMOS platforms for future microprocessors, the authors concluded. The quantum well device with an 80nm gate length had a +0.11V threshold voltage with an ION/IOFF ratio of 2150 with a 0.5V gate voltage swing. Sub-threshold slope and drain induced barrier loading (DIBL) were better for enhancement-mode than depletion-mode devices, they reported.

A sub-50nm compound semiconductor high-electron-mobility transistor (HEMT) also set a new speed record, achieving an extrapolated Fmax of over 1THz, as reported by a group from Northrop Grumman Space Technology and the Jet Propulsion Labs (JPL). The extrapolation was based on the successful demo of a 3-stage low-noise millimeter IC amplifier working at 340GHz with over 15dB gain. The authors believe they can achieve 600-700GHz amplifiers with next-generation designs, pushing the limits for military and telecom systems as well as radio astronomy. The InGaAs/InAlAs/InP HEMT incorporates a T-shaped gate as small as 35nm formed using e-beam lithography.

Another record, an ultrahigh blocking voltage of 8300V which could be useful for high-power systems such as hybrid vehicles, was achieved for an AlGaN/GaN heterogeneous transistor (HFET) on sapphire with thick poly-AIN passivation by a group from Matsushita/Panasonic. Via holes were drilled thru the etch-resistant sapphire by a high-powered laser. The device achieves a specific on-state resistance of 186-Ω.cm2 with an Imax of 150mA/mm.

A room-temperature electrically pumped Ge semiconductor laser, potentially useful for light generation for an IC, was developed by a group from National Taiwan U. They used a simple metal-insulator semiconductor (MIS) structure, with a thin (~2nm) tunneling insulator to allow carrier tunneling between an electrode and the semiconductor. A pair of cleaved (111) planes perpendicular to the plane of junction forms a Fabry-Perot cavity. The device is 48μm wide with a 1-2mm cavity length. The authors suggest that the Ge laser could be integrated onto silicon by epi or wafer bonding, and an even better laser may be feasible by taking advantage of the SiGe junction.

Pionics, or graphene nanoelectronics, was the topic of an overflowing session. Walt deHeer of Georgia Institute of Tech. said he was surprised his paper was accepted due to the early phase of this work on deposited hexagonal carbon like that of carbon nanotubes (CNT). The major difference is that CNTs grow in an uncontrolled tangle while the deposited graphene forms thin films on a SiC wafer. In-plane sigma bonds in the carbon form the strongest bonds known but groups of atoms form p-electron orbitals in what is called pibands, hence the name “pionics.” The piband mass is zero, so carrier velocities are independent of energy. In addition to charge and spin, they are characterized by chirality. Successive layers in the hexagonal motif are rotated about 2.5°, so there is little interlayer coupling.

Similar to CNTs, metallic or semiconducting graphene ribbons can be created with the bandgap inversely proportionally to the ribbon width due to quantum confinement. The graphene layers can be patterned using microelectronics techniques to form both transistors and interconnects. Graphene mobilities of 104cm2/Vs have been demonstrated, promising higher speeds and lower power than is possible with silicon, deHeer said.

Obtaining bandgaps suitable for room-temperature operation would require nanopatterning beyond present capabilities, however, so a chemical modification method for bandgap control would more expedient at present, he explained.

The excitement about pionics at IEDM is shared by DARPA, according to a source at the session, and a major development program is planned for this emerging technology.

Another graphene paper from the U. of Florida in the US, and U. of Pisa in Italy, did a performance comparison of two types of graphene nanoribbon devices: schottky barrier and MOSFETs. The MOSFET has superior parameters and would be less impacted by potential defects, so this type of device would be preferable.

The JJ Ebers award fittingly went to Stephen J. Pearton, a Tasmanian with a dry wit, who was a pioneer in developing processes for compound semiconductors when at Bell Labs. Pearton noted in his acceptance that compound semiconductors and silicon technology now appear to be merging to some extent, and he congratulated the silicon community for “catching up.” — B.H.

December 10, 2007 – The Formosa Plastics Group is spending about $4.6M on R&D of ethylene vinyl acetate (EVA) film, a packaging material for solar cell modules, in a bid to develop a high-margin business in a high-growth domestic sector, notes the Taiwan Economic News.

The company is positioning itself to fill a domestic need for materials used in solar cell manufacturing, the paper notes, citing group executives who point out that there’s a $312M market for EVA materials, and Taiwan’s solar cell industry currently imports all that it uses (e.g., DuPont from the US, and Japan’s Hisheet). The company plans to ramp to volume production next year — hoping for 40% gross margins — targeting local solar-cell makers, which consume 20% of global supply of the material, the paper notes.

Work began last year to research packaging materials for solar cell modules, deciding that EVA was a good candidate, and the group also has been working with Taiwan’s Industrial Development Bureau (IDB) of the Ministry of Economic Affairs, according to the paper.

The R&D investment will be put aside for material R&D and a 10-person team. The company already has the EVA production equipment, and can push to volume production by just improving the process and technology — something the Formosa group has demonstrated it can to in other traditional product areas to make a lucrative profit, the paper notes.

December 10, 2007 – IBM and JSR Micro say they will worth together to explore new technologies for emerging semiconductor materials and processes, targeting next-generation lithography as well as self-assembly applications.

Under the joint research agreement, they will collaborate on a set of exploratory projects, initially targeting new materials for future lithography technology, but later possibly including nontraditional areas such as self-assembly. Work will be done at IBM’s Almaden Research Center in San Jose, CA.

“We view this as a strategic extension of our research and development (R&D) program which will yield benefits for all of our customers,” said JSR Micro president Eric Johnson, in a statement.

“Our joint research with JSR helps us do even more exploratory work at critical mass,” added Gian-Luca Bona, senior manager, science & technology, at IBM’s Almaden Research Center. “This partnership combines the deep chemistry and materials science expertise of IBM Research and JSR’s record of innovation and technology impact in the electronic chemicals arena.”

December 10, 2007 — NIL Technology has further increased the availability of cost-efficient nanostructures for nanoimprint lithography (NIL). Last year the company introduced nickel standard stamp with structures as small as 100 nm, and thereby made available NIL beyond large conglomerates to researchers and engineers. Now the company has introduced its second standard stamp, in quartz (fused silica) and silicon, with features as small as 50 nm.

“We have shown that there is a large market for standard stamps”, says managing director Theodor Nielsen. “With the introduction of the Quartz and Silicon standard stamps we now cover a wide market need and this time with structures down to 50 nm.”

Nanoimprint lithography (NIL) is an economically efficient production technique for sub-100 nm structures. NIL Technology has priced its Qz and Si stamps at 4900 Euros.

by Debra Vogler, Senior Technology Editor, Solid State Technology

Intel execs revealed highlights from select papers the company will be presenting at IEDM, including some details about its 45nm HK+MG transistors that incorporate a redistribution layer as part of a 9-layer copper interconnect. Also featured is the company’s success in mitigating process variation to the extent that results in variation at 45nm is comparable to that achieved at 130nm. Additionally, quantum well FETs may be ready at ~2015 to extend Moore’s Law scaling.

Advancing technology with one step forward, three steps back

An invited paper (#18.2, “Reducing Variation in Advanced Logic Technologies: Approaches to Process and Design for Manufacturability of Nanoscale CMOS”) outlines how Intel is mitigating certain aspects of process variation in 45nm devices relative to past generations. The company will reveal some of the details behind how it has been able to achieve across-wafer and within-die variation at 45nm to levels comparable to variation at the 130nm generation.

“Although device dimensions continue to shrink each generation, Intel continues to optimize its layout and its design and process improvements to maintain, or even improve, process variation from generation to generation,” said Kelin Kuhn, Intel Fellow and presenter of this paper. “Much of the literature extrapolates from generation to generation and comes to the erroneous conclusion that Moore’s Law is going to end because the variation is getting so high,” she said. “Part of the function of this paper is to show no, that’s not true — we actively reduce variation each generation in order to keep it either constant, or better, each time around.”

To demonstrate Intel’s ability to maintain very low random variation, both across the die and across the entire wafer, Kuhn will describe one of the techniques the company uses to measure it: special ring-oscillator test structures. Random variation is measured by taking the difference between two adjacent test structures. She will also present data that illustrates that the variation at 45nm is comparable to what Intel achieved at 130nm.

Other data to be presented compares SRAM structures at 90nm, 65nm, and 45nm (see Fig. 1, below). In going from 90nm to 65nm, Intel used a design mitigation strategy by changing the cell geometry from a “tall” design to a “wide” design. This “significantly improves variation by aligning the poly in one direction and eliminating diffusion corners,” said Kuhn, noting that that this kind of design mitigation has been done by several other companies.

At 45nm, however, Intel uses a process mitigation strategy — i.e., changing the patterning process to create square endcaps that improve variation relative to rounded endcaps, which are characteristic of the design at 65nm. At 45nm, the poly achieved has no bubbles or variation. Many details of how Intel had to change the lithography to be compatible with the “wide” design process will remain proprietary, but some have been released previously, and additional examples will be shown at IEDM, Kuhn told WaferNEWS.

45nm HK+MG: Hitting all the high notes

In another widely anticipated paper (#10.2, “A 45nm Logic Technology with High-k + Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging) Intel VP Kaizad Mistry will show how the ninth layer of a 9-layer copper interconnect is used as a redistribution layer, able to achieve uniform power distribution across the die, thus eliminating voltage droops and current spikes associated with hot spots. The latest 45nm HK+MG transistor also uses Intel’s third generation strained silicon and features Intel’s Hf-based high-k gate dielectric and dual metal gate electrodes. Other process features to be discussed are the use of trench contacts instead of rectangular or round contacts, as well as lead-free packaging.

The redistribution layer, i.e., the 9th interconnect layer, is “very” thick, allowing for “very nice” on-die power distribution, Mistry told WaferNEWS. “The redistribution layer enables a more uniform current distribution across the die so that when a hot spot is drawing a lot of current, there isn’t a resultant voltage droop or current spike,” he explained. However, this redistribution layer does not deal with the thermal ramifications of a hot spot.

Mistry added that he will describe “in detail” the process flow to generate the high-k transistors, as well as some of the electrical characteristics that support a very high performance (very high drive current). He also will go into some of the details of how the company improved the strain process in going from 65nm to 45nm, the third generation of strained silicon.

According to Mistry, the benefits attained from Intel’s 45nm HK+MG and the enhanced strained silicon include a better than 10X reduction in gate leakage, 30% lower switching power over the prior generation, and, either a significant increase in performance (over 20% at the same leakage) or a reduction in leakage of 5X at the same performance or drive current (see Fig. 2, below). “This is a trade-off between leakage and drive current,” explained Mistry. “If you have a lower threshold voltage, you’ll get more drive current and more leakage


A carbon nanotube AFM tip. (Image: Xidex)

December 7, 2007 — Xidex Corp., an Austin, Texas-based nanotechnology company, has been awarded a contract from the U.S. Department of Energy (DOE) for scaleable manufacturing of carbon nanotube (CNT) based field emission sources for use in scanning electron beam instruments such as scanning electron microscopes (SEMs) and transmission electron microscopes (TEMs).

The project is aimed at significant improvement in the imaging resolution, signal-to-noise ratio (SNR), and processing speed of SEMs and TEMs used in materials science, biotechnology, forensics, medical research, the semiconductor industry, and the emerging nanotechnology industry.

“We plan to manufacture CNT field emitters on metal substrates that can be integrated into SEM and TEM electron guns,” said Vladimir Mancevski, Xidex’s chief technology officer. “The company plans to demonstrate a scaleable production processes for making the CNT emitters.”

CNT emitters directly address a longstanding problem in electron microscopy, said Paul McClure, Xidex’s president and CEO. “Electron optical columns have improved significantly in the last 15 years, but the field emission source itself has basically not changed. Our carbon nanotube based source represents a new possibility for a breakthrough. This project will have a huge impact on all areas of electron microscopy.”

December 5, 2007 – C. Uyemura & Co., an Osaka-based supplier of metal plating chemicals, has developed an additive that prevents formation of “tin whiskers” on circuit boards and other electronic components, according to the Nikkei Business Daily.

Circuit boards historically have been plated with tin-lead plated finish to prevent oxidation and improve soldering, but the switch to tin plating has exacerbated the problem of “tin whiskers,” needle-like crystals of metal that can grow spontaneously on tin-finished surfaces, potentially causing current leakage and shorting due to bridges. Using materials other than tin-silver for plating avoids the problem, but these materials can be up to twice as expensive.

The company says its new additive, “GRX-70,” a mix of surfactants and organic compounds, doesn’t entirely eliminate the tin whiskers, but it does help limit their length to just 3-5 microns, or half the usual size, the paper notes. The smaller, evenly sized crystals better distribute the force of expansion that occurs at the interface between a component’s tin plating and copper wiring, the force behind whisker growth.

Samples of the additive are now being sold at roughly 2000 yen/liter (~US $18).

December 5, 2007 – ATMI and IBM have agreed to jointly develop and demonstrate advanced chemical formulations for highly implanted photoresist strip applications targeting 45nm, 32nm, and 22nm chipmaking processes.

Under the agreement, the two firms will work on integrating new materials and thin-film processes, combining ATMI’s semiconductor materials and process experience with IBM’s IC design and manufacturing know-how. Work will be done at both ATMI’s facilities in Danbury, CT, and IBM’s TJ Watson Center in Yorktown Heights, NY.

“New materials are driving integrated circuit performance,” noted Tod Higinbotham, EVP of process solutions for ATMI, in a statement, adding that the partnership will address “specific materials issues that are plaguing the semiconductor industry worldwide today-and those that will become obstacles in the future.”

December 5, 2007 – Semiconductor equipment sales this year are turning out slightly better than expected, according to SEMI’s year-end forecast update, but the outlook for 2008 now indicates the equipment sector’s first year in the red since 2005.

Following a 23% surge in tool sales in 2006, equipment sales are seen slowing to 3.0% growth this year to $41.68B, though that’s better than the 1.1% SEMI predicted in July (and the group notes in a statement that in dollar amounts that’s still the second-highest total ever). Wafer processing equipment sales are seen rising 6% in 2007, with mixed results in backend tools (test down ~15%, assembly/packaging up ~11%).

In 2008 SEMI now thinks tool sales actually will contract -1.5% to $41.05B, instead of previous projections of a 6.5% increase, with ~5% lower sales in wafer processing tools only partially offset by 6%-8% growth in backend equipment.

2009, however, looks better than before, with double the growth as previously thought (8.8 vs. 4.4%) to $44.65B, and 2010 is also slightly more bullish at 7.5% growth to $47.99B. As with other years there’s a division in growth between front/backend — the projected ~8%-9% growth in tool sales during both years is weighted toward wafer processing (10.6%) and “Other” (14.6%).

Two interesting points are worth noting in SEMI’s forecast in 2009-2010. After topping $2.88B in 2008, assembly/packaging tool sales are seen plunging 17% over the next two years. Meanwhile, sales of “other” semiconductor manufacturing equipment are expected to surge nearly 35% over the same period to $4.22B.

By region, Taiwan is expected to rise nearly 30% to snatch the spot from Japan (-3.1%). Also enjoying growth on the plus side this year are Korea ($7.38B, 5.2%) and China ($2.87B, 23.8%), while North America ($6.67B, -8.9%), Europe ($3.18B, -11.7%) and rest-of-world ($3.25B, -12.4%) are in the red.

Next year, SEMI sees only Europe ($3.24B, 2.0%) and rest-of-world ($3.62B, 11.4%) staying above water in tool sales, with other regions ranging from flat to down 7%. Japan and Taiwan will continue to seesaw in the No. 1-2 slots in 2008 and 2009; both regions are seen cracking $10B by 2010, with Taiwan pulling further ahead after two years of low-teens growth.

Forecast by equipment segment

(Sales in US $B)

……………………………………2007 (% growth)…..2008 (% growth)…..2009 (% growth)…..2010 (% growth)

Wafer processing…………….30.61 (6.5%)……….29.12 (-4.9%)……….32.22 (10.6%)……….34.64 (7.5%)
Assembly/packaging………….2.72 (10.6%)……….2.88 (5.6%)………….2.64 (-8.2%)…………2.39 (-9.4%)
Test………………………………..5.47 (-14.7%)………5.91 (8.0%)………….6.20 (4.9%)……………6.74 (8.6%)
Other………………………………2.87 (0.6%)…………3.13 (9.1%)……………3.59 (14.6%)……….4.22 (17.7%)
TOTAL EQUIPMENT*………41.68 (3.0%)………..41.05 (-1.5%)………..44.65 (8.8%)………..47.99 (7.5%)

Forecast by region

……………………………..2007 (% growth)…..2008 (% growth)…..2009 (% growth)…..2010 (% growth)

North America…………….6.67 (-8.9%)……….6.50 (-2.6%)……….6.98 (7.4%)…………..7.46 (6.9%)
Japan……………………….8.92 (-3.1%)……….8.90 (-0.3%)……….9.53 (7.2%)………….10.42 (9.3%)
Taiwan……………………..9.42 (28.9%)……….8.77 (-6.9%)……….9.93 (13.2%)……….11.13 (12.1%)
Europe……………………..3.18 (-11.7%)………3.24 (2.0%)……….3.38 (4.5%)…………..3.49 (3.1%)
South Korea………………7.38 (5.2%)………..7.29 (-1.2%)……….8.04 (10.4%)…………..8.67 (7.9%)
China………………………..2.87 (23.8%)……….2.73 (-4.6%)……….2.99 (9.4%)……………2.93 (-1.9%)
Rest of World……………..3.25 (-12.4%)………3.62 (11.4%)……….3.79 (4.8%)………….3.88 (2.4%)

*Totals and percentages may differ due to rounding of numbers

Source: SEMI

by Ed Korczynski, Senior Technical Editor, Solid State Technology

Gerald Yin, CEO and co-founder of Advanced Micro-Fabrication Equipment Inc. (AMEC), provided an exclusive interview to WaferNEWS to discuss the OEM’s first products and its business strategy. A global semiconductor OEM with headquarters in China, AMEC has designed and released its first thin-film deposition and etch tools for leading-edge IC manufacturing.

A brief backgrounder….Earlier this year AMEC finalized a $43M Series B round of financing with funding from Qualcomm and Samsung Venture Investment Corp; KLA-Tencor’s VC arm, KT Venture Group, participated in an earlier round. AMEC’s board “observers” include a host of VC and investor representatives, with histories at Applied Materials, TEL, Intel, Toshiba Semiconductor, and Novellus Systems.

AMEC currently has 250 employees, of which 85 are claimed to be experienced executives from the semiconductor equipment industry, and 32 director-level or higher from the US. Main operations are in Shanghai’s Zhang Jiang High Tech Industry Zone, with sales headquarters in Singapore and subsidiaries being set up in Japan, Korea, and Taiwan. Yin explained that the global nature of the IC fab industry made it challenging to consider where best to locate different company functions — e.g., “Do you want to have a US head of sales or an Asian head of sales?”

To support global customers, the company consciously decided to staff itself with a mix of nationalities. “At the beginning we decided to have eight different nationalities. Only one nationality can lead to an insular mindset,” explained Yin.

AMEC’s tools are all for 300mm wafers and based on a standard cluster-tool design, with two or four wafers/chamber and a maximum of three chambers/cluster. “Primo” is the trademarked brand name for the tools targeting 65nm and below manufacturing.

The two-wafers/chamber Primo dual-frequency reactive ion etch (RIE) system for dielectric etch uses proprietary hardware to couple two independent plasma frequencies into the chamber. Independent control of both 2MHz and 60MHz frequencies allows for separate control of plasma energy and density, providing for a much wider process window and allowing a single chamber to do cleaning, etching, and ashing of a wide variety of dielectrics. The company claims it has developed efficient processes for low-k dielectric strip, FSG trench and via etch, and HAR etching.

The four-wafers/chamber Primo sub-atmospheric chemical vapor deposition (SACVD) system for dielectrics uses individual showerheads, gas delivery, and heaters for each wafer. Shared pumping and exhaust design minimizes costs for a system design that looks a lot like the Novellus Vector, though without multi-station sequential processing (each wafer experiences all deposition in a single spot). Claimed innovation in the gas distribution system keeps gas precursors from pre-reacting above the wafer, which leads to better gap-fill capability at a higher rate with reduced particles for both shallow-trench isolation (STI) and boro-phospho-silicate-glass (BPSG) deposition applications. “Multi-channel” gas distribution is not a new concept — it was used in Watkins-Johnson’s dielectric APCVD systems sold in the 1990s — but its embodiment in a pseudo-single-wafer showerhead chamber is novel.

AMEC claims that alpha tools and first beta tools at customers demonstrate excellent repeatability, low particles, and high uptime as is expected in a tool for advanced IC fabs. Six beta tools are planned for installation by 1H08, going into advanced manufacturing lines for logic, flash, and DRAM. — E.K.