Category Archives: Materials and Equipment

January 16, 2012 — Mitsubishi Heavy Industries, Ltd. (MHI) launched a fully automated 12" (300mm) wafer bonding tool, Bond Meister MWB-12-ST, capable of producing 3D large-scale integration (LSI) circuits at room temperature. The 300mm bonder targets production of memory chips and microprocessor units (MPU).

The first system was installed at the National Institute of Advanced Industrial Science and Technology (AIST) in Japan.

The Bond Meister MWB-12-ST uses a fast atom beam (FAB) gun instead of a traditional ion beam gun. The FAB gun irradiates atoms to activate a material surface for bonding. Whereas an ion gun radiates an argon ion beam, an FAB gun radiates a neutral atom beam of argon, offering about 20x more energy per particle. The FAB gun effectively removes oxide film on the surface of the bonding metal. Up to 20-ton weight loading is applicable for bonding.

The system bonds up to 5 300mm wafers continuously, performing wafer transfer and alignment for automatic bonding. It can preliminarily set the bonding conditions for each wafer individually, for small lot, mixed type production. Room-temperature wafer bonding eliminates heat stress and strain, reduces wafer processing time, and could enable more miniaturization in LSI designs. The tool can bond silicon and various metals.

Also read: MHI 8" wafer bonder produces 3D LSI ICs at room temp and MHI ships first 200mm MEMS bonder

AIST is an advanced public research institute involved in industrial technology fields, with technical expertise in room-temperature bonding. The MHI wafer bonder will be used in semiconductor-related work. Learn more about AIST at http://www.aist.go.jp/index_en.html

Going forward, MHI will further intensify its proposal-based approach to potential customers to expand the adoption of room-temperature bonding as a key technology for 3-D LSI circuit production, the company reports.

MHI launched its room-temperature wafer bonding platform in 2006. MHI is involved in the engineering, manufacture and sale of ships, environmental improvement equipment, industrial machinery, aircraft, space systems, air-conditioner, etc. Learn more at http://www.mhi.co.jp/en/index.html.

January 11, 2012 — Zymet introduced the CN-1736 reworkable underfill encapsulant for 0.4mm-pitch package-on-package (PoP) assemblies.

Figure. Void-free underfill of 0.4-mm pitch POP with CN-1736.

The underfill boasts low viscosity and a lower CTE than its predecessors, and greater flux compatibility. The 650cps viscosity enables optimized flow speed with finer pitch devices. The CTE of 55 ppm/

January 10, 2012 — The SMTA released its call for presenters for SMTA International (SMTAI) 2012, October 14-18 in Orlando, FL. The association, along with Chip Scale Review magazine, also announced the keynote for the International Wafer-level Packaging Conference (IWLPC), held November 5-8, San Jose, CA.

SMTAI papers are sought on electronics assembly as well as advanced packaging and components. Packaging papers can cover 0.3mm Pitch Area Array, 3D Packaging and Integration, BGA/CSP, Biomedical Packaging, Bumping, Chip on Board, Direct Chip Attach, Embedded and Miniature Passives, Failure Analysis, Fine Lead Pitch, Flip Chip, High Temperature Packaging, Lead Finishes, Leadless Packages (LGA/QFN/BTC), MEMS and Sensors, Package on Package (PoP), Photonics, Photovoltaics and Solar Packaging, Reliability, Solid and Collapsible Wafer Bumps, Through Silicon Vias (TSVs), Tin Whiskers, and Wafer Level Packaging (WLP). See SMTA’s Call for Papers site to check out all the suggested topics for emerging technologies, electronics assembly, supply chain/business papers, PCB technology, process control, and energy papers.

SMTA International offers Best of Conference Presentation, Best of Proceedings Paper, and Best International Paper awards at the show.

Abstracts (300 words) are due March 12, 2012, and can be submitted here: http://www.smta.org/smtai/call_for_papers.cfm. All abstracts must be submitted online and will not be accepted by e-mail.

Proposals are also solicited from individuals interested in teaching educational courses related to surface mount technology, advanced packaging, and electronics manufacturing.

Paper manuscripts and course workbooks are due by July 27, 2012. Papers should be 6-15 pages long (including graphics) and describe significant results from experiments, emphasize new techniques, or contain technical, economic, or appropriate test data. Presentation materials and papers must be original, unpublished, and non-commercial in nature.

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John Ellis will keynote IWLPC, discussing Cyber-Physical Terrorism in his presentation, "A Trojan Chip in Your Smartphone? It’s Coming…"

The topic is malicious circuits receiving commands via social networks. Hacking a few highly-followed celebrity accounts would provide a perfect avenue for distributing ‘self-destruct’ codes to millions of Trojan chips. A widespread, cyber-physical attack, which would have been almost impossible to pull off just a few years ago, could soon become reality.  

After graduating from the University of Texas with a Master’s in Mechanical Engineering, John worked at Sandia National Labs, where he focused on R&D projects for the Department of Energy, Department of Defense, National Institute of Standards and Technology, and other federal agencies. His experience includes nuclear weapons testing, missile guidance (Advanced Cruise Missile), air-borne and space-borne imaging systems (Predator UAV), and semiconductor manufacturing. John

January 9, 2012 — Multitest, semiconductor test equipment provider, qualified its UltraFlat process for high parallel vertical probe card tests. UltraFlat provides permanent overall PCB flatness for better wafer-level test.

For applications such as DDR3 memory, board flatness is crucial at wafer-level testing. For optimizing MLO/MLC attachments and contact element interfaces, a better surface is needed. Additionally, flatter PCBs require less compliance from the probe interface and reduce interface wear.

UltraFlat is based on PCB stack up engineering and PCB construction technologies, allowing for a very tight overall flatness tolerance to be maintained by removing bows/twists in the PCB. The technique creates a permanent overall flatness, unlike baking techniques that are temporary, Multitest reports.

With UltraFlat, Multitest typically is able to comply with bow/twist requirements of 1.0%.

Multitest manufactures test handlers, contactors, and ATE printed circuit boards for semiconductor test. For more information, please visit www.multitest.com/pcb.

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January 9, 2012 — Camtek Ltd. (NASDAQ and TASE: CAMT) launched Xact200, its second generation transmission electron microscope (TEM) sample preparation system for the semiconductor industry. Camtek calls the system an alternative to traditional focused ion beam (FIB) analysis.

Camtek has received its first purchase order for the tool, from a leading semiconductor company in Asia.

TEM enables analysis of small semiconductor feature dimensions and complex materials. The Xact200 enables sample preparation for 2X and 1X nodes, combining Adaptive Ion Milling (AIM) technology with an integrated FE SEM column and in-process STEM imaging capability. AIM can reduce lamella thickness <20nm over a large area with high precision, artifact-free quality, and higher throughput, Camtek reports.

Camtek Ltd. provides intelligent imaging, image processing, adaptive ion milling (AIM) and digital material deposition (DMD) for semiconductor and PCB and IC substrate production. Website: www.camtek.co.il.

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January 6, 2011 — Wedge and wire bonder maker Hesse & Knipps Inc., the Americas subsidiary of Hesse & Knipps Semiconductor Equipment GmbH, launched its next-generation BONDJET BJ93X heavy wire bonder for back-end semiconductor assembly, targeting manufacturers of power semiconductors and automotive electronics.

Hesse & Knipps will demo the wire bond tool at APEC 2012, February 6-9 in Orlando, FL (http://www.apec-conf.org/), Booth 914.

The BONDJET BJ93x heavy wire bonders feature a heavy wire bond head with integrated pull test and 305 x 410mm table travel for automotive electronics and power semiconductor interconnect requirements. The BONDJET BJ920 handles aluminum, gold and copper heavy round wire and ribbon wire at speeds of 3 wires/sec. Patented PiQC Process Integrated Quality Control analyzes 5 critical measurements of bond quality in real time for every bond

January 5, 2012 — Haruo Matsuno, president and CEO of Advantest Corporation (TSE:6857, NYSE:ATE) announced the company’s major goals in his New Year’s address to employees and stakeholders.

By fiscal year (FY) 2014, Advantest plans to bring in revenue of 250 billion yen, over 20% operating margin, and have over 50% total market share of semiconductor test systems and test handlers. The $1B acquisition of Verigy in 2011 boosted Advantest’s offering for memory and SoC customers, Matsuno said when the deal was announced. It combined Advantest’s strength in memory semiconductor test systems and mass production lines and Verigy’s strength in non-memory semiconductor test systems and R&D.

"To reach out new targets above and maximize synergies from the Verigy integration, we will spark innovation in all areas," said Matsuno, pointing to a new business model utilizing cloud computing, flexible productions processes, and a global marketing and organizational structure.

Outside of semiconductor test products, Advantest will bring its measurement technologies into scanning electron microscopes (SEM), electron beam (e-beam) lithography, RF measurement devices, MEMS switches, terahertz analysis systems, and healthcare products.

Advantest manufactures electronic measuring instruments, automatic test equipment, and electron beam lithography systems. Learn more at www.advantest.co.jp.

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January 3, 2012 – PRNewswire — Packaging equipment provider NEXX Systems sold a 300mm Stratus electrochemical deposition (ECD) system to Powertech Technology (PTI), a major IC packaging and testing company in Taiwan. PTI will use the Stratus to make copper pillar bumps and re-distribution layers (RDL) for portable intelligent device packages, targeting smart phone and tablet PC applications.

The tool will be evaluated for PTI’s through silicon via (TSV) commercialization program.  

Also read: Nantong Fujitsu Microelectronics installs NEXX tool for copper pillar, RDL packaging

PTI is primarily known for memory device assembly, in high volumes, supplying integrated device manufacturers (IDMs) and fabless companies, said Scott Jewler, Senior General Manager, PTI. Jewler expects that the new deposition tool will help PTI lower the cost of leading-edge packaging.

NEXX Systems offers electrochemical deposition and physical vapor deposition systems for advanced semiconductor packaging. Learn more at www.nexxsystems.com.

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December 30, 2011 — As the semiconductor industry moves into the 22nm silicon technology node, device fabrication is not the only challenge that the industry will face. According to the International Technology Roadmap for Semiconductors (ITRS), a porous ultra-low-k (ULK) material will replace the traditional silicon dioxide. Stresses within the die must be controlled, not only during wafer fabrication, but also in packaging and assembly.

This will be even more challenging than the industry

December 29, 2011 — The updated IEST "Garment System Considerations for Cleanrooms and Other Controlled Environments" recommended practice document includes new sections on measuring cleanroom footwear, frocks and other garments, as well as a new subsection for tracking system use, such as RFID chips and barcodes.

A new edition of IEST-RP-CC003.4, Garment System Considerations for Cleanrooms and Other Controlled Environments, includes a 20-page supplement on recommended garment measurement specifications. The supplement, Guide to Measuring Cleanroom Garments, provides illustrated instructions for measuring coveralls, frocks, hoods, and footwear.

The revised Recommended Practice (RP) is published by the Institute of Environmental Sciences and Technology (IEST).

Also read: ISO Cleanroom standards update

IEST-RP-CC003.4 addresses the gowning of personnel as a critical aspect of cleanroom contamination control. Specification and use of an appropriate gowning system is essential in preventing human-generated contamination from reaching and affecting product or processes in the cleanroom. The RP provides non-mandatory guidance for the selection, specification, maintenance, and testing of garments or apparel and accessories appropriate for use in non-aseptic and aseptic environments.

The RP defines required performance criteria, test methods, and procedures for gowning system use and maintenance. It also features guidelines for developing a quality control (QC) plan for the apparel and accessories that may be part of the system. This edition includes a new subsection on the use of advanced tracking systems, such as barcodes and radio-frequency identification (RFID) chips, to monitor garment service life. Also provided is a section describing types of fabrics and relevant properties and methods of testing of the materials used in cleanroom garments, as well as the design and construction of appropriate configurations and special features of such garments.

Appendix B explains the Helmke drum test method, introduced in an earlier edition of the RP and based on round-robin testing performed by the IEST Working Group. This method is used to quantify particles dislodged through the application of mechanical energy under dry conditions as a means of simulating particle shedding from the surface of the garment during use. Garments being tested are tumbled in a rotating drum to release particles from the fabric in a controlled manner, while a discrete-particle counter is used to sample the air within the drum.

Ordering information for IEST-RP-CC003.4 and other IEST publications is available at www.iest.org.

IEST is an international not-for-profit technical society of engineers, scientists, and educators that serves its members and the industries they represent (simulating, testing, controlling, and teaching the environments of earth and space) through education and the development of recommended practices and standards. IEST is an ANSI-accredited standards-developing organization; Secretariat of ISO/TC 209 Cleanrooms and associated controlled environments; Administrator of the ANSI-accredited US TAG to ISO/TC 209; and a founding member of the ANSI-accredited US TAG to ISO/TC 229 Nanotechnologies.