Category Archives: Metrology

June 4, 2012 — AKHAN Technologies Inc., advanced diamond electron device designer, will collaborate with the Center for Nanoscale Materials (CNM) at Argonne National Laboratory (Argonne Labs) to fully characterize Miraj Diamond devices and materials, which are made by doping n-type diamond and can be used in the semiconductor industry.

Through "Characterization of Novel N-type Nanocrystalline Diamond and Related Diode Devices," the team will better understand the electronic properties of n-type doped diamond thin films, using CNM’s various nanoscale characterization techniques. Results of these studies will be disseminated in a non-proprietary manner.

“Europe has been focused on the delta doping method, which has extremely narrow process requirements including the requirement of very thick diamond on expensive single-crystal diamond carriers, implemented commercially by companies like Element 6 De Beers. Japan has been forward looking, investing heavily in more cost-effective diamond-on-silicon microchip technology, [which is] useful only in very hot and otherwise extreme environments with epitaxial diamond-on-diamond wafers but not at all with diamond-on-silicon wafers, implemented by institutions like Japan’s National Institute of Science and Technology and Nippon” said Adam Khan, AKHAN founder and chief executive.

The n-type diamond material Miraj Diamond, developed in the US with the help of wafer fabs, enables highly manufacturable, fully functioning diamond microchips, Khan said. The Miraj Diamond platform enables fabrication of complex devices such as high speed/power transistors, RF, and microwave electronics.

AKHAN Technologies is a fabless semiconductor company pioneering research and development of diamond-based semiconductor devices with applications in the microelectronics industry. For more information, visit http://www.akhantech.com. AKHAN’s Miraj Diamond IP portfolio is currently brokered by ICAP Patent Brokerage, a division of ICAP plc and the world’s largest intellectual property brokerage and patent auction firm.

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May 31, 2012 — Sanjay Rajguru, director of ISMI, will present “Tool Obsolescence and the Impact on 200mm Manufacturing” at The ConFab 2012’s final session, Maximizing the Longevity of Investments.

The ConFab is an invitation-only event for the semiconductor industry, June 3-6 in Las Vegas. Rajguru will join John Frank, SVP Industrial and Advanced Technology, CH2MHill; Gary Robertson, division GM, KLA-Tencor; and Mike Barrow, EVP and COO, International Rectifier, in the session.

Moore’s Law dictates that some portion of our semiconductor product base becomes obsolete every year, Rajguru points out. A growing list of 200mm manufacturing parts also becomes obsolete every year. Tool obsolescence is possibly the most critical problem faced by legacy manufacturers.

To help identify the root cause and possible solutions to obsolescence, ISMI conducted over a year’s research. Rajguru will cover tactical and strategic methods that semiconductor manufactures in the mature production sector can use for dealing with tool obsolescence.

Sanjay Rajguru is the director of International SEMATECH Manufacturing Initiative (ISMI), responsible for the consortium’s manufacturing technology programs. His role includes leading ISMI’s Manufacturing Capabilities and Mature Fabs programs, which are focused on the systematic improvement of manufacturability: factory and equipment stability, productivity and cost improvements, and equipment lifecycle management. He also oversees the ISMI ESH Technology Center, a global collaborative research organization including chip manufacturers and equipment and material suppliers devoted to collectively finding and implementing the most cost-effective, environmentally friendly manufacturing processes and procedures. Prior to joining ISMI, Rajguru was a fab manager at National Semiconductor for 13 years and held various engineering and management positions with Nortel Semiconductors.

Other ConFab previews:

Bridging the fabless-foundry gap

EUV lithography readiness

Packaging progress

Emerging growth sectors

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May 29, 2012 — Rudolph Technologies Inc. (NASDAQ: RTEC), back-end macro defect inspection tool supplier, will deliver 14 NSX Series 320 inspection systems to a large outsourced semiconductor assembly and test (OSAT) provider.

The inspection tools will be installed in Q2, at multiple steps in wafer-level chip-scale packaging (WLCSP) production.

The packaging house chose to order NSX 320 systems following a competitive evaluation, in which they noted its high speed and efficient, easy-to-use operating procedures.

This is a new product for Rudolph. The NSX320 System performs defect inspection and 2D bump metrology, and acquires on-the-fly defect images at production speeds. WLCSP lines require flexibility for handling substrates in various formats while collecting detailed defect and 2D metrology information during the inspection process, said Nathan Little, vice president and general manager of Rudolph

May 29, 2012 — KLA-Tencor Corporation (NASDAQ:KLAC), maker of semiconductor manufacturing metrology tools, measures a 70% increase in fab process steps from 90nm to 32nm semiconductor nodes. This doubles the critical inspection steps required, report Citi analysts from a non-deal roadshow with KLAC’s CFO and EVP Mark Dentinger.

Node changes are not accelerating, but continue to present technology challenges that should enable both inspection and metrology to outgrow the overall equipment market. Importantly, KLAC noted that the 28nm node’s process control spending cycle is still in the early to middle inning and nowhere near its ending phases.

New device architectures — like 3D gates — and processing technologies — like double/triple patterning and extreme ultraviolet (EUV) lithography — will accelerate the demand further. Some will change metrology tool requirements — EUVL will shift fab demands from optical inspection to reticle inspection, overlay metrology demand will grow with adoption of double patterning. KLAC noted that electron-beam inspection, which it refers to as an R&D rather than process line tool, will see flat growth in the near future.

In addition to new nodes, the move to 450mm wafers will push fabs to add metrology/inspection tools. KLAC is supplying its first bare wafer inspection system for 450mm this quarter to an OEM. KLAC believes Intel will develop 450mm pilot lines in 2016 with volume production starting sometime in 2018. The pace at which INTC executes this transition will determine the pace at which other manufacturers (foundries) embark on the transition.

Inspection/metrology spending will be 16-20% of foundry/logic capital expenditures, and 8-12% of memory’s, with combined 15% share of wafer fab equipment spending, Dentinger said. This could go higher on foundry strength. In total, for all tools, KLAC foresees 2012 spending flat to down 5%.

KLA-Tencor Corporation provides process control and yield management products, including state-of-the-art inspection and metrology technologies for the semiconductor, data storage, LED, photovoltaic, and other related nanoelectronics industries. Additional information may be found at www.kla-tencor.com (KLAC-P).

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“The Dangerous Disappearing Defect” is the first article in a new series called Process Watch. Authored by experts at KLA-Tencor, Process Watch articles focus on novel process control solutions for chip manufacturing at the leading edge.

Finding and classifying defects on a wafer is a statistics game. The defect pareto—the bar graph showing the number of defects by type caught by the defect inspector and identified by the e-beam review system—drives the actions of the defect engineers in the fab. However, it’s not necessarily the tallest bar in the graph that tells the experienced defect engineer how to fix a defect problem. Far too often, the tallest bar is the insidious “SNV”—SEM Non-Visual. Some fabs bluntly label this category “Not Found.”

It might be more accurate to call the category “Not Found Again.” The defect inspection system did indeed find these defects and reported them in the KLARF, the output file that lists the locations of the defects detected on the wafer along with some descriptive information such as the size of the scattering signal associated with them. The “Not Found” problem arose when the wafer was moved to the e-beam review system to identify defect type. As the e-beam review system drove to the sites of the defects found by the inspection tool, sometimes it didn’t see a defect. This situation can arise for any of several reasons. First, the inspection system could have experienced a glitch, a result of electrostatic discharge or system noise, and therefore reported a false event. Second, misalignment between the coordinate system of the inspector and that of the e-beam review system could have resulted in the defect lying outside the field of view (FOV) of the e-beam review system. Third, the inspection system could have detected a defect at a previous layer that’s covered by a film transparent to the (optical) inspection system but not to the e-beam review system. Fourth, the defect could have arisen from nuisance variation, such as line-edge roughness, that shows up as a defect when the inspector uses a die-to-die detection algorithm, but is not evident in a review image, which is viewed alone. In any of these cases, the defect will be classified as “Not Found” or “SNV.”

SNV Type One: False events. As defined above, false events are a rare occurrence for today’s wafer inspection systems. Advances in signal processing algorithms, mechanical and electrical subsystems, and system integration have virtually eliminated false events. (False events are not to be confused with nuisance defects, which are defects arising from real, physical phenomena on the wafer—that defect engineers have designated as not affecting yield, performance or reliability. Examples of nuisance defects besides line-edge roughness might include particles that reside in open areas and bridges within dummy pattern. Nuisance defects can be culled from defects-of-interest (DOI) through multiple means, including choice of wavelength, aperture and polarization in the inspection recipe, and by various defect classification schemes post-detection. Nuisance defects like particles on open areas might be successfully re-detected by the e-beam review system, then binned or classified as nuisance, or they might be SNV, like line-edge roughness.)

SNV Type Two: Field-of-View Errors. For previous-generation inspection and review tools, insufficient coordinate accuracy often meant that the e-beam review tool had to search for each defect using a large field of view, then “zoom in” to image the defect with sufficient resolution to allow its classification. This strategy had two drawbacks: 1) it was very time-consuming, and thus limited the number of defects that could be reviewed on a wafer so that a statistically representative defect population was nearly impossible to attain; and 2) with a large FOV, the resolution of the image was too low to find the smallest critical defects. It didn’t matter that the ultimate resolution of the review tool was a couple of nanometers; if that resolution had to be compromised while the system was searching for defects, a significant number of defects would be missed. Defect engineers began to realize that, while resolution of the e-beam system is necessary for defect classification, the tool’s ultimate resolution is useful only if the defects of interest can be located reliably. 

Recent advances in stage accuracy on the wafer inspection and review tools, and improved communication between the tools, have now made it possible for e-beam review tools to drive directly to the location of the defect using a sub-micron field of view. The latest e-beam review tools can now reliably and efficiently locate the smallest yield-critical defects reported by the latest inspection systems and, without zooming in, image these defects for classification. This breakthrough has had a tremendous effect on the reduction of SNV counts, and the redistribution of these counts to appropriate defect classes (see Figure). Having a defect pareto that more accurately represents the defects on the wafer allows defect engineers to direct their efforts toward solving the most critical problems.

SNV Types 3 and 4: Previous-Layer Defects and Nuisance Variation. With the matter of false events out of the way, and having ensured that the review system is looking in the right place, we are left the problem of separating previous-layer defects—which truly should be SEM non-visual—from SNV nuisance, i.e. defects correctly imaged by the e-beam review tool but difficult to identify as defects from the review image. If the layer inspected is transparent to the wavelength band of the optical inspection tool, then the possibility that the defect is from the previous layer should be considered. In some cases the previous layer was also inspected, in which case defect source analysis (DSA) can be used to compare the locations of the previous layer’s results to those of the current layer. If the possibility of previous-layer defects has been ruled out, the expertise of the defect engineer is essential for determining the source of the “defect.” If it’s nuisance variation, it may be possible to hone the defect classification schemes to disposition nuisance variation defects into their own category in the defect pareto. Alternatively, the defect engineer may need to adjust the recipe of the inspection system to lower its capture rate for these SNV defects, through choice of a different aperture, wavelength band or polarization mode.

Why does it matter that the SNV defects are properly categorized? Defect engineers act on the information given by the defect pareto, and a high SNV count can disguise or hide real problems. For example, some of these mysterious, disappearing defects may be important DOI lying just outside the field of view of a previous-generation review tool. A misleading defect pareto can result in a delay in getting a new process to yield, or even a delay in getting a new chip to market. Using every means possible to ensure that the defect pareto properly represents the defects on the wafer—especially those defects that affect device yield, performance or reliability—gives fabs the best chance to bring their products to market profitably and on time.

Rebecca Howland, Ph.D., is a senior director in the corporate group and Christina Wang is a senior product marketing manager in the e-beam technology division at KLA-Tencor.


Check out other Process Watch articles: “The Dangerous Disappearing Defect,” “Skewing the Defect Pareto,” “Bigger and Better Wafers,” “Taming the Overlay Beast,” “A Clean, Well-Lighted Reticle,” “Breaking Parametric Correlation,” “Cycle Time’s Paradoxical Relationship to Yield,” and “The Gleam of Well-Polished Sapphire.”

About thirty five well-polished professionals (…pun intended…) attended the May 16th meeting of the NCCAVS CMP Users Group at SEMI headquarters in San Jose. The agenda comprised several topics with the overall theme of CMP consumables and their management. Presentations will be posted in the coming weeks at CMP User Group Proceedings.

The meeting kicked off with Mike Fury (yes, he’s related to me) of Vantage Technology speaking on "The Sampling Statistics of Low Slurry Particle Counts." Slurry contains millions of particles/ml below 0.5µm by design, with a rapid decrease in particle counts as the particle size increases above that. In a well-managed slurry, low particle counts are expected above 1µm. Line control using periodic slurry sample sizes of 1ml down to 0.25ml provides a good statistical representation of small particles which are plentiful, but the sampling error for large particles quickly increases over 100% for average particle counts lower than 10 particles/ml. Periodic sampling and dilution measurements do not provide a good statistical representation of large particle counts (LPC). Continuous sampling improves this representation considerably. More importantly, the availability of continuous LPC data allows the implementation of six-sigma line control practices to identify, track down and eliminate the root causes of the LPC drifts or spikes to ultimately reduce scratch defect yield losses.

Paul Bernatis, DuPont EKC Technology, presented "Tackling Critical Requirements for Advanced Post-CMP Cleans" and described the design of EKC PCMP 5600, a 4th generation PCMP cleaning solution product. The challenge for formulators continues to be a vanishingly small process window in which the chemistry can perform all of the cleaning functions required without contributing to corrosion or delamination. Impact on TDDB was studied closely in several copper / low-κ dielectric systems. Electrostatic attraction of residues to the wafer surface is another issue that needs to be moderated by the formulation. Electrochemical studies showed the successful avoidance of corrosion conditions in experimental Cu on Co barrier systems. Mitigation of Cu dendrite growth after processing was based on prior DuPont experience in the prevention of Ag migration.

John Mendonca, Asahi Glass Corp. spoke on "Front-end, back-end and substrate slurries: Key process data", providing an overview of the ceria and silica slurries and contrasting their key properties. Ceria is finding applications beyond STI, including ILD, polySi, poly stop and backside TSV. Emerging applications include sapphire and SiC polishing. Ceria abrasives are migrating from a D50 of 0.18µm down to 0.14µm. The poly stop slurry has a TEOS/poly selectivity >500:1. A silica slurry for sapphire has been used successfully with continuous recycling and reuse.

Floyd McClung, founder of CV Nanotechnology (CV being Castro Valley, CA and not capacitance-voltage) talked about his current incarnation, "Advances in optical polishing abrasives and slurries." Semiconductor CMP and silicon wafer polishing, after all, had their roots in optical polishing. Slurry recycling is common, slurry filtration is not, and chemistries are much simpler and less aggressive than chip CMP. Ceria is the most commonly used abrasive for its high removal rate on the silicon oxides that are most commonly polished. The most widely used PCMP solution is Dawn, the same stuff as under your kitchen sink. Some of the slurries used are quite large, with D50 ~0.8µm and a tail beyond 5µm. Applying the process advances in CMP to the optical polishing industry is likely to prove beneficial to them. To hear Floyd describe it, retiring to optical polishing after a career in CMP is a bit like kicking your feet up on the porch with a cool adult beverage in your hands.

The organizers may not have realized that the speaker lineup for this meeting had a heavy bias toward EKC genealogy, as Floyd and I also have roots there, as did a few attendees. An alumni reunion was hastily organized and enjoyed by all.

In an exclusive series of blogs, imec’s science writers report from the International Technology Forum (ITF) in Brussels. This year, ITF’s theme was “It’s a changing world. Let’s make a sustainable change together”.

Tomorrow’s data centers and smart mobile devices will require extreme computation and storage capabilities, orders of magnitude above what today’s processors and memories can deliver. This drives the need to keep on scaling technologies. In her ITF presentation, An Steegen, Senior Vice President Process Technology at imec, discusses the three technology knobs that are key for a further system scaling.

First, in pursuit of Gordon Moore’s law, there is area scaling. Lines and spaces within the transistor will become smaller and smaller, and the specs for overlay – how the lines and spaces are aligned to each other – get ever more severe. Where in 1985, technologists could still live with 300nm overlay for a 1000nm technology on a 100mm Si wafer, the overlay spec has gone down to 5nm for a 20nm CMOS node in 2013. Advanced lithography is the key knob to get there, and for future nodes, EUV shows great capabilities. With one single exposure, it promises to go down to 16nm lines and spaces, and reach less than 2nm overlay.

A second technology knob is power/performance trade-off. Reaching increasing computation power requires a look into new materials and device architectures. For the 32/28nm technology node, the semiconductor industry did so by introducing high-k/metal gates. Moving on to the 22/14nm, fully depleted devices such as the FinFET are being implemented, allowing to improve the transistor’s sub-threshold slope and electrostatic behavior. Moving further, higher mobility channels will be inserted as a replacement for the Si channel. Beyond 10nm, technologists will have to move away from the solid-state based transistors, and go into other mechanisms like quantum-mechanical tunneling. And very far out, more novel materials such as graphene will probably take over. But also the back-end and interconnections will require material innovations, such as moving away from Cu metallization for reliability reasons, and moving into ultralow-k materials as a dielectric. One new area that comes along is variability and how to deal with it when moving forward into these very small devices.

Last but not least, there is cost as a third technology knob. How to keep the cost factor under control when the roadmap gets ever more complicated? Well, inserting EUV e.g. at the 14nm node will certainly help, as cost analysis has shown. Of course, there is the question of 450mm: is economy of scale also helping us out to scale our future technology nodes?

The challenges for scaling are huge, but imec is confident that, together with its partners, they will find the right solutions. They did so in the past, when scaling was considered to already have reached its limits. Today, it will be just a little harder than it used to be.

Mieke Van Bavel, science editor, imec, Belgium

ITF: Life has changed


May 25, 2012

In an exclusive series of blogs, imec’s science writers report from the International Technology Forum (ITF) in Brussels. This year, ITF’s theme was “It’s a changing world. Let’s make a sustainable change together”. More info: www.itf2012.com

Life has changed. Take for example the energy problems we are facing today, or the many diseases people have to deal with. Luc Van den hove, President and CEO of imec calls on the industry to create a sustainable change to deal with these problems. And the way to do this is by bringing together different technologies, expertises and by leveraging synergies among various disciplines. “Open innovation is the way to go,” underlines Van den hove.

One domain in which the potential of cross-disciplinary innovation is enormous is healthcare. “Today we treat diseases in a generic way, we diagnose and treat diseases when symptoms occur. It’s time for a drastic change towards a more personalized, preventive, predictive and participative healthcare system,” states Van den hove. He compares the change to come with the change that microelectronics has gone through: from mainframe to desktop pc to smartphone. “We will see the same revolution in diagnostics, enabled by the tremendous progress in ICT,” says Van den hove. “We will migrate from big medical analysis tools in large labs towards desktop like diagnostic tools in the practice of a healthcare practitioner.” As an example of this evolution Van den hove shows the Biocartis molecular diagnostics platform. “Or think of a blood glucose meter connected with your smartphone to do measurements in your home environment,” says Van den hove. As an example of imec research in the domain of diagnostics, Van den hove tells about the goal to make a chip with thousands of parallel inspection circuits able to inspect 20 million cells per second. By combining electronics, microfluidics, imaging hardware and cancer research, a chip could be made for the early detection of cancer cells in blood.

Van den hove ends its presentation with the remark that business has changed. Before, big companies used the fully captive model in which research, development and manufacturing were performed by three separate organizations within the company. “With the huge challenges we are facing today, it is clear that the captive model has become unaffordable and ineffective,” says Van den hove, “the only way to achieve real innovation is through open innovation.” Van den hove talks by experience. In its various research programs, imec has set up a full ecosystem of research groups and companies covering the whole value chain. “Confronting different ideas and opinions, sharing resources and expertise across companies, institutes, countries and continents is the fundament of sustainable business for a sustainable world,” concludes Van den hove.

Els Parton, Science editor imec

May 25, 2012 — THE BEST rankings from VLSIresearch identify the highest-rated suppliers of wafer processing, assembly, and test equipment. Chipmakers applauded their suppliers with increased ratings this year, according to a survey by VLSIresearch.

See the semiconductor assembly and test equipment suppliers here.

See the best of THE BEST here.

Large suppliers of wafer processing equipment
Rank Company Rating
1 Novellus 8.95
2 ASML 8.07
3 Applied Materials 8.02
4 Tokyo Electron 7.74
5 Hitachi Kokusai Electric 7.58
6 Nikon Corporation 7.48
7 Hitachi High-Technologies 7.27
8 Lam Research 7.16
Source: VLSIresearch 2012 Customer Satisfaction Survey.

With a 9% increase and an outstanding average rating of 8.95, customers honored Novellus with first place for the second year in a row. This is Novellus’ fourth appearance in first place. This supplier of deposition equipment excelled in all rating categories and earned the highest ratings among all Large Suppliers of Wafer Processing Equipment in 14 of 15 categories. With ratings in nine categories at 9.0 or above, Novellus’ highest rating was in trust in supplier at 9.2. The companies rating Novellus represented 56% of the chip market.

ASML, the premier lithography supplier, jumped from 4th place to 2nd with an average rating of 8.07. Not surprisingly, ASML earned its highest rating, as well as the highest rating among all large wafer processing suppliers in technical leadership at 9.3. ASML’s ratings were earned with responses from 54% of the chip market.

Applied Materials, the worldwide chip equipment leader, shot up six positions to 3rd place this year. A 17% increase boosted its rating to 8.02. Applied Materials’ highest ratings were in technical leadership and quality of results, both at 8.4. This supplier was reported on by 72% of the chip market.

Small suppliers of wafer processing equipment
Rank Company Rating
1 Oerlikon 8.19
2 Plasma-Therm 8.18
3 EV Group 8.14
4 Nanometrics 8.10
5 Agilent Technologies 7.60
6 SUSS MicroTec 7.35
7 Canon 7.12
8 Mattson Technology 7.05
9 Axcelis 7.00
Source: VLSIresearch 2012 Customer Satisfaction Survey.

Oerlikon, a supplier of PVD equipment, earned the number one spot for the third consecutive year as its rating rose to 8.19 this year. The company received its highest ratings in five categories, two of which were the highest among all Small Suppliers of Wafer Processing Equipment: product performance and usable performance at 8.4. Oerlikon was represented by 35% of the chip market.

Plasma-Therm bounced into 2nd place, slightly behind Oerlikon, with a rating of 8.18. A supplier of etch and clean equipment, Plasma-Therm received its highest ratings, as well as the highest ratings among all small wafer processing suppliers in commitment and field engineering support, both at 8.7.

EV Group increased its rating 13% to an 8.14 and jumped 3 slots to 3rd place. The company earned its highest rating, as well as that of all small wafer processing suppliers, in trust in supplier.

VLSIresearch received feedback from more than 99% of the chip market for this year’s survey. The survey spans two and half months and covers five languages. Worldwide participants were asked to rate equipment suppliers among fifteen categories based on three key factors: supplier performance, customer service, and product performance. 2,102 surveys were returned, resulting in 49,480 total responses.

Stay tuned for additional rankings from VLSIresearch’s survey!

The VLSIresearch annual Customer Satisfaction Survey on Chip Making Equipment allows chip manufacturers to provide feedback on their suppliers. VLSIresearch is a leading provider of market research and economic analysis on the technical, business, and economic aspects within nanotechnology and related industries. Website: www.vlsiresearch.com.

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May 25, 2012 — VLSIresearch polled semiconductor manufacturers about their tool suppliers, asking chipmakers to rank equipment providers on customer satisfaction. This year’s results show renewed focus on fab needs.

Large suppliers of chip-making equipment

Rating

Focused suppliers of chip-making equipment

Rating

1 Novellus

8.95

1 F&K Delvotec

8.51

2 Advantest

8.37

2 Oerlikon

8.19

3 Teradyne

8.35

3 Plasma-Therm

8.18

4 Hitachi High-Technologies

8.09

4 EV Group

8.14†

5 ASML

8.07

5 LTX – Credence

8.14†

6 Applied Materials

8.02

6 Nanometrics

8.10

7 Tokyo Electron

7.84

7 Delta Design

7.62

8 Kulicke & Soffa

7.70

8 Agilent Technologies

7.60

9 Hitachi Kokusai Electric

7.58

9 Seiko Epson

7.56

10 Nikon

7.48

10 ACCRETECH – Tokyo Seimitsu

7.45

Source: VLSIresearch 2012 Customer Satisfaction Survey.

† Rankings for the #4 and 5 positions were determined on ratings carried out to three decimal places.

For the first time in the history of the survey more than half of the suppliers in each category had greater than an 8.0 average rating, compared to two suppliers last year. As a result the average rating for these 10 BEST suppliers was 8.0, an increase of 0.35 points over last year. “This year’s ratings reflect new supplier initiatives to focus on their customers’ satisfaction, with better service and products,” commented G. Dan Hutcheson, Chairman and CEO of VLSIresearch.

Large Suppliers of Chip Making Equipment

Novellus retained its #1 spot this year with an increase of 0.77 points to 8.95. The company’s dedication to customer satisfaction paid off this year by earning the highest ratings among all Large Suppliers in 14 of the 15 rating categories. Advantest and Teradyne improved ranking positions substantially this year while competing for the 2nd and 3rd positions, with Advantest slightly exceeding Teradyne by a mere 0.02 points. Teradyne leaped from the 9th spot and Advantest from 7th, with point increases of 1.35 and 1.01 respectively. Advantest achieved its highest rating in trust in supplier at 8.7; Teradyne in would recommend supplier, also at 8.7.

Although both Hitachi High-Technologies and ASML achieved increased ratings this year, they dropped a slot to 4th and 5th positions as a result of Advantest and Teradyne’s jumps. ASML, well-known for its highly-productive lithography tools earned the highest rating of all Large Suppliers in technical leadership. Hitachi High-Technologies’ highest attribute was in quality of results.

Focused Suppliers of Chip Making Equipment

F&K Delvotec, a supplier of wire bonders, rose to the top spot for the first time this year with a rating of 8.51. The company garnered the highest rating of all Focused Suppliers in nine categories, with its highest rating of 9.0 earned in both field engineering support and support after sales.

Oerlikon retained its #2 rank with a rating of 8.19. This PVD supplier achieved its highest rating of 8.4 in five categories: would recommend supplier, trust in supplier, product performance, usable performance, and uptime.

Plasma-Therm moved up five slots to the 3rd position with a rating of 8.18. Customers applauded this etch & clean supplier as the highest in commitment of all Focused Suppliers as well as a tying for spares support with F&K Delvotec.

Most Improved Suppliers

In Large Suppliers, Teradyne showed the most improvement with its movement up from 9th to 3rd position and a 19% surge in its rating. Teradyne is followed by Applied Materials with a 17% jump in its rating. Nikon closed out this race with an increased rating of 16%.

Nanometrics deserves particular notice in Focused Suppliers with a remarkable 47% climb in its ratings, leaping from the 36th to the 6th slot. LTX-Credence’s significant increase of 33% moved it up from the 31st to the 5th slot. EV Group also showed a notable improvement with a 16% rise from the 15th to the 4th spot.

Stay tuned for additional rankings from VLSIresearch’s survey!

The VLSIresearch annual Customer Satisfaction Survey on Chip Making Equipment allows chip manufacturers to provide feedback on their suppliers. VLSIresearch is a leading provider of market research and economic analysis on the technical, business, and economic aspects within nanotechnology and related industries. Website: www.vlsiresearch.com.

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