Category Archives: Metrology

Nov. 30, 2006 — Veeco Instruments Inc., a supplier of instrumentation to the nanoscience community, announced the launch of the new Dektak 150 Surface Profiler for high-performance research and industrial metrology applications.

The company says the Dektak 150 delivers the highest repeatability and lowest noise over the largest scanning range available for a stylus profiler, enabling Veeco’s customers to benefit from greater scan range and ease-of-use.

The modular design of the Dektak 150 enables it to be configured to meet stringent application requirements. The compact system is designed to accommodate samples up to 100 millimeters thick and performs long scans of 55 millimeters. The company says the half-millimeter vertical range is industry-leading standard Z performance, and a 1-millimeter option extends the vertical capabilities even further. With sub-nanometer step-height repeatability, the Dektak 150 accurately measures step-heights for thin films below 10 nanometers thick, up to nearly one-millimeter thick-films.

Nov. 28, 2006 — Hyphenated Systems, a Burlingame, Calif., provider of hybrid microscopy solutions for three-dimensional imaging and metrology in micro and nanotechnology, announced the release of its new HS200A NanoScale Optical Profiler. The company says the HS200A adds extensive automation capability to the Hyphenated Systems workhorse — the HS200OP — for fast, repeatable non-destructive analyses in critical metrology, inspection, failure analysis and quality control applications.

The system incorporates Hyphenated Systems’ Advanced Confocal Microscopy (ACM) technology that acquires and displays high-resolution (<50nm) three-dimensional images in seconds. The HS200 systems also provide the user with all the capabilities and flexibility of a fully functional, research-grade binocular optical microscope. The system is intended for 3D imaging and metrology of rough or sloped surfaces of MEMS and other semiconductor devices, or imaging subsurfaces through transparent materials.

“Adding automation makes it an even more valuable tool in applications that require a large number of repetitive, routine operations,” said Terence Lundy, Hyphenated Systems’ vice president and general manager, in a prepared statement. “Unlike other 3D metrology techniques, such as scanned laser confocal or interferometry, the HS200OP series also provides the user with a versatile optical microscope, offering a real, viewable optical image and all of the ancillary imaging and analysis capabilities that optical microscopy can support.”


Hyphenated Systems’ new optical profiler is designed for fast, repeatable non-destructive analyses in critical metrology, inspection, failure analysis and quality control applications.

The NanoScale Optical Profiler acquires a series of images that slice through the sample at varying heights, then combines these images into a three-dimensional model of the sample. Its ability to collect data simultaneously through multiple confocal apertures greatly accelerates the data acquisition process, allowing it to construct and display 3D images in seconds.

The company says the new automation capabilities of the HS200A add more speed to routine tasks and improve the repeatability of measurements by removing the variability associated with the operator. The HS200A can move the sample to predefined locations, find features of interest and acquire measurements — without operator intervention, and without the variability introduced by operator judgment, differences between operators, or operator fatigue.

November 28, 2006 – Brion Technologies and Hitachi High-Technologies are collaborating on a DFM platform that will enable chipmakers to detect, measure, and monitor optical proximity correction (OPC) defects during volume production of advanced semiconductors. Brion and Hitachi say the combined technologies in one interface will “vastly reduce the amount of time and number of operations required to generate a several-hundred point CD-SEM recipe for OPC evaluation.”

The companies say they are working with a joint semiconductor manufacturing customer to develop a common interface that works with Brion’s Tachyon lithography design verification and Hitachi’s DesignGauge scanning electron microscope (CD-SEM) metrology system. In the new platform/interface, OPC hot spots will be detected by Tachyon, which will send defect location, classification, and grouping information to be measured and monitored by Hitachi’s DesignGauge.

In a statement, the companies explained that the technologies are already complementary — Tachyon depends upon accurate CD-SEM measurements for design verification, while DesignGauge uses Tachyon output to automate recipe generation and control SEM wafer observations.

“To calibrate Tachyon, one needs to have the most accurate CD measurements possible; this impacts how the process model is built and ultimately the design’s verification,” said Jun Kanamori of Hitachi High-Technologies, quoted in the statement. “So an efficient interface between model construction and CD measurements is extremely useful. And after Tachyon has identified hot spots in a design, they can be verified with the SEM for closed-loop control of design and manufacturing.”

Eric Chen, CEO of Brion, hinted that the common Tachyon-DesignGauge interface “is only a first step” in a collaboration between the two companies to evaluate and leverage synergies between their technologies.

November 21, 2006 – Days after a business unit reorg and executive shuffle, Nova Measuring Instruments Ltd. has announced layoffs of about 8% of its workforce in all parts of the organization, but mainly in R&D and operations and including management positions. The company will take a $300K charge in 4Q06 to cover termination expenses and other costs, but foresees saving $2 million in 2007.

The company had seen positive results from its localization initiative laid out last year, which involved increasing headcount for customer support and sales in specific regions, but that increase in resources has had to become balanced by lowering expenses in other areas, explained Gabi Seligsohn, president and CEO of Nova, in a statement. “This was done in order to fit to a new set of requirements, as we accelerate the penetration of our new offerings and begin developing our next generation of products. The new management team has acted as quickly as possible to complete this organizational realignment in order to reduce our breakeven point and accelerate the attainment of our business goals,” he said.

Days ago Nova shuffled its management team and reorganized business units around profit lines and to integrate the operations of recently acquired HyperNex. The company also posted a 3Q net loss of $800K, slightly more than 2Q net loss of $400K but less than its year-ago net loss of $1 million. Quarterly revenue rose 9% sequentially and 40% year-on-year to $12.5 million.

The gradual improvement in the business side offsets distractions from the legal end of things. Last month Nanometrics filed a new patent infringement lawsuit against Nova over optical critical dimension technology, following similar litigation in the spring regarding its UV reflectometry and optical critical dimension tools. Nova itself filed suit against Nanometrics in early 2005, over its US patent #6,752,689, “Apparatus for optical inspection of wafers during polishing.”

In September, Nova put a number of lithography metrology patents up for auction, relating to use of a lithography tool with integrated metrology. The company “invited” bids from approximately 100 companies, including leading-edge IC manufacturers, semiconductor equipment manufacturers, and metrology firms, and indicated it would be open to selling outright ownership in the technology.

October 26, 2005 – Nanometrics Inc. and ASML Holding NV have entered into a cross-licensing agreement to incorporate Nanometrics’ overlay and critical-dimension control metrology technology into ASML’s lithography systems.

“We are committed to offering our customers extendible, open-architecture Overlay and CD control solutions that scale beyond 32nm,” said John Heaton, president and CEO of Nanometrics, in a statement. “We are extremely pleased to be working with ASML to create solutions that improve lithography performance and economics.”

“Metrology within the scanner is a key element for the current performance of ASML lithography systems. With increased access to advanced metrology technology we see further opportunities for advancements in lithography and wafer patterning,” added Karel van der Mast, senior VP of ASML.

Oct. 26, 2006 — Nanometrics Inc., a Milpitas, Calif., supplier of advanced integrated and standalone metrology equipment to the semiconductor industry, announced it has entered into a cross-licensing agreement with ASML, the provider of lithography systems for the semiconductor industry based in Veldhoven, the Netherlands.

The agreement reflects the commitment to offer customers extendible, open-architecture Overlay and CD control solutions that scale beyond 32nm, according to statements by John Heaton, Nanometrics’ president and CEO.

Oct. 20, 2006 — The UK government has published a progress report which provides an update on the government’s direction and details of progress made on research into possible risks posed by engineered nanoparticles to human health and the environment.

The report demonstrates the work already in hand across government to ensure that fundamental elements of understanding, such as how to measure and detect nanoparticles, is known. Further results from the research are intended to help inform decisions on appropriate control within the development of nanotech-based products and throughout their lifecycle.

The interim report follows the publication in November 2005 of the first UK government research report ‘Characterising the potential risks posed by engineered nanoparticles’. The 2005 report committed the government to an program of research to help address recognized gaps in knowledge about the health and environment-related risks and identified 19 research objectives.

The area is being looked at by five task forces, reporting to the Nanotechnology Research Coordination Group, addressing the following subjects/areas:

1: Metrology, Characterisation, Standardisation and Reference Materials

2: Exposure – Sources, Pathways, Technologies

3: Human Health Hazard and Risk assessment

4: Environmental Hazard and Risk assessment

5: Social and Economic Dimensions of Nanotechnologies

The new report includes details of the UK’s action plans covering the above subjects and sets out progress made towards meeting the 19 research objectives. It is intended to contribute evidence for regulators and provide a source of information both for applicants for research funding and for managers of research funding bodies.

This report can be viewed at http://www.defra.gov.uk/environment/nanotech/research/reports/index.htm. A full progress report, updating both current knowledge and research objectives, is slated to be published by the end of 2007.

by James Montgomery, News Editor

October 17, 2006 – ASML Holding NV says it has received the first order from an unidentified customer for a pre-production EUV system, following shipments of two alpha tools earlier this year to IMEC and Albany Nanotech.

In a conference call to discuss EUV news and research progress from the 2006 International Symposium on Extreme Ultraviolet Lithography (Barcelona, Spain), ASML acknowledged that these “preproduction” tools won’t have the desired throughput for desired manufacturing, mainly because of work still to be done with source power. Noreen Harned, VP of marketing, technology and new business, ASML, noted that both alpha tools at IMEC and Albany are using a low-power xenon source, but the company plans to eventually integrate tin sources (supplied by Philips Extreme UV GmbH) to achieve the ~180W power (intermediate focus) required to boost throughput to >100 wafers/hour. “The only fuel that seems to have the right version efficiency is tin,” she said. “Early sources on xenon really shows there’s a limitation.”

Harned explained that the early EUV systems are vacuum-based but still share certain components with ASML’s TwinScan platform (e.g. the Athena sensor, as well as e-beam writers, repair tools, and some metrology), though some technology will be brand-new, e.g. reticle handling. The preproduction EUV tools will be able to accommodate either laser-produced plasma (LPP) technology or an electrical discharge-based power source. She indicated that more integration work at IMEC and Albany, with some early data on critical metrology, should be available by next February’s SPIE conference.

Martin van den Brink, ASML’s EVP of marketing and technology, noted that the pricepoint of the first EUV tools will be around 40 million euros (US $50 million), vs. ~35 million euros ($~43.8 million) for the company’s newest immersion systems (NA=1.35) announced in July of this year. Compared with previous tool prices at previous nodes, “that’s quite consistent, you won’t see an extraordinary price jump.” Once EUV is able to achieve 100WPH, it will actually be cost-competitive with immersion requirements when taking into account things like double-patterning and longer cycle times.

During the press conference Q&A, when asked about ASML’s planned production ramp for its new EUV systems, van den Brink expressed “surprise” that other suppliers are sticking to a roadmap to push out production-ready EUV tools by 2009. “We took a precaution in the productivity specification for 2009, but we remain bullish on that productivity,” he said.

ASML pointed to other announcements at the EUV symposium as evidence that much progress is being made to make EUV a viable lithography technology for the 32nm node and below. Industrywide achievements discussed at the event include: optical trains from Carl Zeiss SMT AG, with work continuing for mirror fabrication, coatings, mechatronics, and system metrology; advancements in power source, including LPP and tin. Rohm and Haas is touting a “breakthrough” in EUV photoresist with 40nm, 1:1 feature resolution, as well as 35nm line/space resolution, sub-40nm contact hole resolutions, and 25nm-resolution chemical amplification resist. Toppan Photomasks says it is readying commercial supplies of EUV masks. And European light source supplier XTREME technologies GmbH plans first shipments by December of its 10W-range integrated source/collectors, with a volume production-worthy 100W EUV source design ready by 2008. — J.M.

DFM: Are we there yet?


October 10, 2006

by M. David Levenson, Senior Technical Editor

The special Friday session of BACUS ’06, organized by Bob Naber of Cadence, addressed the question of industry progress and readiness for DFM, and discussed the remaining challenges as well as proposed solutions. Mark Mason of Texas Instruments pointed out that “DFM is a journey, not a destination,” and worried that management did not yet understand how hard it was going to be. Michael Lercel, director of lithography at SEMATECH, noted that all manufacturing options have limits that must be respected by designers. In particular, said Lercel, limiting the number of exposures needed for “double patterning technology” to merely two will require design restrictions. He worried that variability will limit CD uniformity no matter what, and that the 1.2nm (3σ) spec for 32nm half-pitch on the ITRS roadmap is just unfeasible — even for EUV. If so, designers will have to learn to accommodate more variability.

Luigi Capadieci of AMD captured part of the challenge, saying that the pages of
design rule manuals are growing exponentially: 250 pages today and 2000 predicted for 22nm, most of them “restrictive rather than prescriptive” — basically, pages and pages of things not to do, but little information as to what should be done. Still, tools are becoming available and design info is being shared with metrology and APC. What is needed more than anything, according to Capadieci, are standard interfaces to facilitate sharing.

Naoya Hayashi of DNP lamented that the total edge length on a typical mask is now 42km — the length of a marathon run — and mask inspections are expected to find 20nm sized defects or anomalies on this route. Just writing a 45nm CD mask takes 30 hours today, even before inspection and repair. For maskmakers, he predicted the key DFM tool will be a “mask behavior model.”

At Intel, the main DFM approach is “designing variety out,” according to Sunit Rikhi, Director of Advanced Design. He described a unique organization that transformed tape-out into the technology module (DMW, for “design-mask-wafer”) where manufacturing begins. The Intel DFM framework deals with variability in three stages: mitigation, co-optimization (both for design and manufacturing), and control.

Fabless companies have a completely different challenge, as described by Tim Horel, VP of hardware development at startup Tabula, and Artur Balasinski of Cypress. Depending on their phase in the technology cycle, different companies have different needs, with DFM enabling leading-edge products but “only” increasing yield for trailing nodes. Horel believes that improving the education of designers is crucial, and foundries should be responsible for facilitating it.

There is quite a ways to go before mask customers understand what actually can be made, according to data presented by Peter Buck of Toppan Photomasks. He reported that 13% of masks have unresolvable data that cannot be transferred to the physical plate, and that 16% of that is in the main pattern, rather than scribe lines, fill, or company logos. Mask-makers are left to guess at the designer’s intent, and have disincentives for alerting customers (who may go elsewhere) of the problem. To ship product, questionable regions are often labeled “do not inspect” (DNIR), with little or very late customer input. While mask rule check (MRC) procedures can mitigate this problem, the EDA tools owned by many customers cannot comply with MRCs, according to TI’s Mason.

Kevin Lucas of Freescale Semiconductor outlined the difficulties of implementing something as new as DFM in our complex industry environment. Even though implementing DFM would conservatively increase yield by 2% across the industry and save $4 billion, comparable to the entire revenue of the EDA industry, DFM is still a hard sell. For example, it requires at least three split lots to document a 1% yield increase — and it is possible that DFM methods can actually reduce yield. Thus, DFM is adopted only for the minority of designs where large improvements can be documented or are expected with confidence. David Lan of leading foundry TSMC also lamented the difficulty of convincing designers to adopt DFM methods, partly because it is so hard to estimate the return-on-investment early in the process. (And several speakers alluded to the perception that designers have always moved on to other things before the DFM problems appear, so there is no one to whom fab engineers can complain!)

The resistance to adopting best practices is, perhaps, the reason that so much of what happened at BACUS this year seemed like marketing rather than technology — we generally know what to do to live with the pattern transfer capabilities, but cannot yet bring ourselves to do it. Promoters of DFM and EDA tools need to adapt them to current processes so they do not seem disruptive and, in the words of Wojtek Poppe of U. California-Berkeley, help designers develop a gut feeling for manufacturability. Once today’s good ideas are adopted, the way may be cleared for something really new. — M.D.L.

What are the real pain points of DFM that are being underestimated? How can we take the step to embrace and assimilate DFM capabilities, and clear the way for some really new concepts?

by James Montgomery, News Editor

Chris Moore, CEO of metrology equipment supplier Philips AMS (now known simply as AMS — Advanced Metrology Systems) talks with WaferNEWS about the decision to break free from former parent Royal Philips, the new reality of semiconductor market cycles, and where the company is pushing new inroads for its trench-measurement technology.

Late last week, Royal Philips announced the sale of its majority ownership in metrology equipment unit Philips AMS to JHW Greentree Capital, an affiliate of J.H. Whitney & Co. of New Canaan, CT. According to Chris Moore, CEO of the newly renamed Advanced Metrology Systems LLC (AMS), both the business and its former parent (which will retain a 19.9% stake) long understood a divestiture was in the cards, as Philips narrowed its core focus to markets such as medical and lighting.

“There was never an issue with them investing in us to keep us going, and growing at a certain level,” he told WaferNEWS, “but there was no long-term home for us. It was going to happen at some point.” In fact, this deal was put together before the Philips Electronics’ semiconductor business (since renamed NXP) was sold months ago to private equity investors led by the Blackstone Group, he said.

Moore acknowledged that AMS turned down other proposed combinations with bigger metrology firms (“we didn’t want to be part of one of the big players that would gobble us up”) and smaller ones (Royal Philips would still have been the majority owner, putting them back at square one of having a foothold in a noncore market). “Private equity was a good way to get us the money we needed to grow, and get a parent to support us,” he said.

With new private-equity ownership, Moore sees a symbiotic relationship where the technology know-how is handled at the management level, while the board focuses on market strategies and growth, with a general knowledge about the business of the industry and just a “comfort level” of technical understanding. “That can stop you from getting tunnel vision, which is very easy in this industry…it forces you to look at the big picture,” he said. The private-equity model also takes a longer-term view of business growth, whereas VC or publicly traded companies are ultimately driven by quarterly results, and are tough to convince that a return-on-investment could take 18 months, if it happens at all.

In addition, life as a public company is increasingly risky and expensive — see the laundry list of companies being investigated for stock options manipulations, which is already amounting to hundreds of millions of dollars in restatements and charges. “I saw a pitch a couple of weeks ago: ‘Come to the UK, where reporting is easier,'” Moore quipped.

AMS’ 50% Y-Y growth was a big draw for equity investors, as was the company’s business strategy — “finding key enabling metrology points in new processes that companies are bringing up, then solving that particular need,” Moore explained. “String enough of those together, that’s a good business model. Not, ‘Gee, I want 10% of a big market’ — that’s not easy.” He pointed to AMS’ work with Infineon and its former memory chip unit, Qimonda, to solve a problem with etch trench structures, which led to AMS licensing MKS Instruments’ model-based infrared reflectrometry (MBIR) thin-film metrology technology in Jan. 2005. “Now we’re the dominant metrology [supplier] for measuring high-aspect ratios in trench DRAMs,” Moore said, noting the company also is working with Asian DRAM fabs including Winbond, SMIC, and Inotera.

Moore also hinted that AMS is now working with some customers to solve problems involving trench measurements for power devices — similar to what it’s done with DRAM, but with adaptations in technology and modeling.

One reason that private equity investors have become keen on the semiconductor industry is a perceived smoothing of historically cyclical market ups and downs. Moore pointed out that in the past, volatile cycles were usually driven by economic conditions and what happened to a particular end-product (e.g., PCs), but now there’s a wider range of end markets, and a down cycle in one chip segment (e.g. memory) may be mitigated by growth in another (e.g. logic). He also pointed out that equipment makers can ramp up much more quickly than in the past, and can run lines much harder to keep utilization rates high instead of reinvesting in more capacity. “Now fabs are running 110%-120% of what they were designed to do, because the equipment can let them do that,” Moore said.

Moore echoed comments made by analyst Stuart Muter at a recent SEMI breakfast near Boston, who suggested that the industry has now basically compressed its market cycles to one-year intervals — with strong orders in the first half of the year, followed by a slowdown to digest capacity, then ramping up toward the end of the year to meet holiday demand. “When it took much longer to ramp, people tended to overbuy, which made the whole cycle worse,” Moore noted. However, he pointed out that R&D cycles have actually lengthened out — e.g., low-k, high-k, and metal gates have all been shifted out beyond their originally intended nodes, as both IDMs and equipment suppliers struggle to get the technologies to work properly. “You’ve got two cycles in the equipment industry: one shorter, and one longer,” Moore said. “What you’re seeing is people getting nodes out on time in terms of size, but pushing technologies further out” — e.g., DRAM makers are not doing things at the 50nm node that they thought they’d have to two years ago, he said. — J.M.