Category Archives: Metrology

Quartz Imaging Corp., Vancouver, BC, Canada, will be showing its newest FA-LIMS system (failure analysis laboratory information system) at the International Symposium for Testing & Failure Analysis (ISTFA 2012), held in Phoenix, AZ on November 13 and 14.

Quartz’s FA-LIMS is designed specifically for semiconductor failure analysis labs. The new FA-LIMS system utilizes new underlying technology to operate with Windows Server 2012 and supports the latest browsers, including Internet Explorer, Chrome, Firefox, and Safari. This web-based system has an improved security model, making it easier to administer system security. The job management process has been further streamlined from previous versions, while providing more advanced management reports of key performance indicators. The system has improved search capabilities and the use of keywords that can be easily added to job and image data.

The "Image Smart" FA-LIMS is a web-based application that features: detailed job requests from authorized internal and external customers; job approval and priority schemes; assignment of tasks based on the approved request; preliminary and approved reports that are very quick and easy to generate; and lab performance reports for management.

by Paul Feeney, Axus Technology

The International Conference on Planarization/CMP Technology (ICPT) was held Oct 15-17 in Grenoble in southern France. This international event is the world’s largest conference covering chemical mechanical planarization (CMP) and related topics, over a 2.5 day period. Over time, the CMP users groups from around the world that come together to form this event are acting increasingly as one body, and the quality of the information has risen.

ICPT oral and poster presentations can be grouped into a handful of major themes:

  • Integration of new device structures, and the CMP processes and slurries needed to support them;
  • Advances in equipment and in endpoint and control methods;
  • Advanced copper interconnects, and the extension of this to 3D and MEMS technologies;
  • Consumables, with a keen focus on mechanistic understanding; and
  • Alternative planarization methods and the application of CMP to new materials.

CMP and new device structures

Leading off the discussion of the application of CMP for new devices was a plenary talk by Daniel-Camille Bensahel from CEA-Leti. He stressed the parallel paths that exist today for 14nm technology and beyond between fully depleted silicon-on-insulator (FD-SOI) and multi-gate or FinFET devices. As technology goes beyond these two architectures, the future will lie in making the transition from silicon channels to some combination of germanium, nanowires, and graphene. All of this bolsters the effect we have already seen putting more focus on the use of planarization in creating devices rather than solely in making interconnects.

Invited talks from IMEC and GlobalFoundries nicely covered the complexity of CMP steps now being employed to fabricate leading-edge devices. In years past, shallow trench isolation (STI) CMP was the only set of CMP steps in the front-end-of-line (FEOL) process flow. Now, many new CMP applications are being added and each calls for multiple process steps. The special dielectric fill for FinFET’s creates the need for steps very similar to those used for STI, but drives the need for stopping on the extremely small nitride features that cover the fins. The ILD 0 or pre-metal dielectric or poly-open-polish (POP) CMP that exposes the tops of the dummy silicon for metal gates also has similarities to these two. The metal gate CMP that follows was discussed as being implemented with either aluminum (Al) or tungsten (W) as the bulk material. There was also coverage of techniques similar to those of replacement gates for formation of replacement channel materials made from germanium (Ge), indium phosphide (InP), or indium gallium arsenide (InGaAs).

Papers that delved into a portion of these new CMP applications pointed out some of the unique challenges. Catherine Euvrard from CEA-Leti pointed out that POP CMP must not only retain tight control over remaining film thickness, but must do so while simultaneous removing nitride and oxide materials deposited at slightly different heights due to the non-planarity remaining after STI. Another difficulty is that the pattern removal rates of nitride and oxide do not follow what might be expected from blanket rates on each of the films when polished separately. Patrick Ong from IMEC went into the development of a 2-step process for replacement Ge channels. The epitaxial overgrowth of Ge is polished back to oxide and then buffed to produce roughness in the range of 2Å. Ulrich Kuenzelmann from TU Dresden showed results from their implementation of Al CMP. These papers were all geared towards advanced logic. Hynix also contributed with talks on new ceria particles for lower defectivity in STI and CMP for buried gates or wordlines for advanced memory. For buried wordline CMP, the bulk metal includes W and must stop on a nitride layer.

CMP equipment, materials, and methods

On the second theme of equipment, a variety of new hardware and control options were highlighted. Len Borucki from Araca pointed out the slurry flow reduction or oxide removal rate gain with a “slurry injector” apparatus. A second talk from Araca described similarities and differences seen in doing CMP of 300mm vs. 450mm wafers. Polishing of 450mm wafers can generate temperatures a few &degC higher, which is likely to have a noticeable effect on temperature sensitive steps such as Cu CMP. Pusan National University and G&P Technology showed that they were able to achieve a radial non-uniformity (NU) of 3% at 2mm edge exclusion with their wafer carrier that contains an “edge profile ring” between the wafer and the retaining ring.

A number of papers described ideas for metrology. Applied Materials and a few customers covered the application of white light illumination for endpoint control across a range of FEOL CMP applications. Improved results were presented for STI thickness, POP thickness with closed loop control of both profile and polishing time, as well as establishment of endpoint control of a process for replacement SiGe channels. Silvio Del Monaco from STMicroelectronics displayed a technique for in-situ measurement of pad groove depth that could be used in characterizing the pad cutting rate of conditioner disks. Florent Dettoni from CEA-Leti described a technique they developed to stitch together interferometric scans to create accurate maps of topography both for whole dies as well as across wafers. Those results were correlated to profilometer scan data, but measurements can be done much quicker. Chandar Palamadai laid out the process that KLA-Tencor has created for quantification of scratching through analysis of blanket wafer haze maps.

CMP and Cu interconnects

The next major theme regarding copper (Cu) included advanced interconnects both for wafers as well as quite a bit on 3D interconnects. Olivier Robin from STMicroelectronics taught us how sheet resistance control mean and variation can be improved by switching to a barrier process with higher selectivity between the dual hardmask and the dense ultralow-k material just below them. Jie Lin from Fujimi described work to develop a slurry for Cu that can get good planarization efficiency despite being used with a pad of moderate hardness. Contributors from Fudan University and from DuPont covered work studying the corrosion and removal rate behavior of the cobalt and molybdenum materials being investigated as part of new barrier material stacks.

ICPT has given increased attention to 3D interconnects and the formation of through-silicon-vias (TSVs) over the last few years. This year included an overview by Viorel Balan from CEA-Leti of some of the issues that need to be addressed in order to do Cu-to-Cu direct bonding. A key to success was identifying and improving topography across several length scales. Both he and Benjamin Steible from ISIT gave evidence that new generations of abrasive-free slurries provide a nice advantage in controlling the dishing of especially larger structures. Jinhai Xu talked about his work at SMIC demonstrating that rings of corrosion at the edges of vias can be seen as a recessed area when there is still about a micron of bulk copper left on the wafer. Rob Rhoades showed two different processes for the TSV nail expose process depending on whether it is an active wafer or an interposer. Catharina Rudolph from Fraunhofer presented a story showing that the combination of high-density TSVs and a higher-temperature anneal actually leads to enough stress that the wafer can explode.

CMP consumables

Over time, consumables for CMP have become more specialized to fit the needs of individual process steps for each application. Consumable topics have always been a popular topic at ICPT and this year was no exception. In the area of pad conditioning, there were two topics that received the most attention. One was applying conditioning techniques to the double-sided polishers used in wafer polishing. Jorn Kanzow from Peter Wolters reported that conditioning provided edge control for the double-sided polishing that is now necessary for achieving flatness for 300mm wafers. The second was the study of pad debris that is generated during pad conditioning and how it leads to an increase in scratch defects. Scratching was shown to be best when doing excitu conditioning or when vacuuming the debris off the pad. A relatively recent style of conditioner uses diamond coating over an engineered surface. 3M presented a summary of their efforts to do that utilizing some of their micro-replication methods.

Keiichi Kimura from Kyushu Institute of Technology presented some very exciting concepts surrounding research done to identify individual removal events during CMP. Through the use of evanescent light, where laser light is bounced off a prism surface, individual slurry particles that come in contact with the prism are illuminated. Their findings put forth the idea that pad asperities and the fluid around them cause adhered particles to be pulled off the polished surface. This happens at velocities much slower than what the pad achieves across the wafer — which rebukes a standard theory that removal is from 3-body contact of a pad asperity pushing a slurry particle into the film being polished. Greg Gaudet from Cabot Microelectronics provided an argument for removal rate with softer pads being driven more by the number of contact points between the pad and wafer rather than the total area of contact. This data seems to back up the concepts presented by Kimura.

For slurries, Intel together with Bradley University and MIT had a few talks outlining the outcome of fundamental studies. Alex Tregub made the point that the characterization of particle size is often overly simplified into a mono-modal distribution. Those tests also often use highly diluted slurry that may not be behaving as it would in its normal state. Mansour Moinpour went over results showing how desorption of additives from particle surfaces can be characterized. Joy Johnson from MIT reviewed a collection of literature surrounding particle agglomeration and added some work showing the role additives can play in agglomerate formation. Along somewhat similar lines, Pall got together with Lewis University to characterize the interaction that slurry particles have with the fibers inside of slurry filters, which may lead someday to the use of novel fibers.

New and improved CMP materials, processes

The remaining major theme is the extension of CMP to new materials and other types of removal processes besides CMP that are also being improved upon. Talks covered new materials such as carbon nanotubes with titanium (Ti) for vias, potassium dihydrogen phosphate (KDP) crystals for optics, GST for phase change memory, SiC for hardmask removal, and Ti and Ti02 for biomedical applications. It turns out that lowering surface roughness of Ti02 improves the biocompatibility of surgically implanted materials.

Though there does not appear to be any technology that is threatening the continued adoption of CMP for many applications, there are also other types of processes that have their place. Hyuk-Min Kim from Hanyang University taught us how lapping results could be improved by switching to a fixed abrasive system. Chuljin Park from KIIT showed a multistep process where diamond mechanical polishing was useful followed by CMP for sapphire substrates. Paul Feeney from Axus Technology demonstrated that improvements in grinding technology can make the CMP of Si after grinding much easier and produce better results. Grinding of Si can be done two-orders-of-magnitude faster than CMP and with within wafer non-uniformity unheard of in CMP. Adding CMP afterwards then produces the best possible surface.

Overall, the technical content of this event was very good. Clearly a lot of energy is being applied around the world to make advances on a wide variety of planarization applications. A high bar has been set for next year’s ICPT in Taiwan!

Paul Feeney ([email protected]) is director of process technology at polishing and thinning company Axus Technology. He started his involvement in CMP at IBM in 1989, holding both process and equipment responsibilities there, including doing pioneering module process and integration work on copper and barrier CMP for the world’s first commercial copper chips. He spent many years at Cabot Microelectronics; as a CMP Fellow there, he led development of a wide range of materials for leading-edge CMP applications. He is also a co-leader for planarization topics for the ITRS.

November 1, 2012 – A group of partners in Europe say they have completed a project to deliver the first EUV lithography optics targeting the 22nm node.

Project participants were led by ASML and included and eight other participants (two Carl Zeiss businesses, six German companies and research facilities) develop EUV lithography. The national project, part of the European "EXEPT" project (EXtreme-UV lithography Entry Point Technology development) and the CATRENE Cluster, was supported with ~€16M from the German Federal Ministry for Education and Research (BMBF).

In a statement, Carl Zeiss summarized and credited the group’s achievements:

  • A more powerful projection lens, highly flexible illumination system without loss of energy, and a high-accuracy measuring systems necessary for their qualification (Carl Zeiss SMT, Oberkochen);

  • New optical elements for the precision measurement of the EUV mirror (IMS, Stuttgart);

  • Mask repair processes for EUV photomasks (Carl Zeiss SMS GmbH, Jena/Rossdorf);

  • Theoretical experiments using special EUV simulation software (Fraunhofer Institute for Integrated Systems and Device Technology, Erlangen);

  • EUV/XUV-based metrology solutions which can be used in reflectometers for the optical characterization of EUV masks (Bruker ASC, Cologne);

  • Process facilities and processes for the cleaning and automated handling of the EUV masks (Süss MicroTec Photomask Equipment, Sternenfels);

  • Facilities for the cleaning and decontamination of the EUV mask transport containers (Dynamic Microsystems, Radolfzell);

  • Appropriate cleaning technologies for 20 nanometer technology EUV masks (Advanced Mask Technology Center, Dresden).

Alignment of EUV optics. (Source: Carl Zeiss)

"The successful collaboration for the further development of this crucial technology helped further strengthen the leading role of German companies in the area of microelectronics," stated Dr. Hermann Gerlinger, Member of the Executive Board of Carl Zeiss AG and CEO of Carl Zeiss SMT GmbH. "Targeted support, like that from BMBF, supports us in expanding the necessary competencies." The demonstrators and technologies developed within the scope of this project (from Süss MicroTec and DMS, alongside Carl Zeiss) have been supplied to customers around the world, they add.

Of course 22nm is hardly the finish line for EUV lithography, or even the starting point — EUV’s potential has been pursued for years now, with technical and cost/benefit hurdles continuing to push out its adoption. BMBF has already committed funding for the next stage of this EUV litho work to improve the projection optics to 14nm resolution. Many in the industry hope EUV lithography will be ready for volume manufacturing by then — and it’s coming up very fast — assuming other improvements can also be achieved in source power and mask infrastructure.

Some improvements in EUV optics were discussed at the International Symposium on Extreme Ultraviolet Lithography in October, including "substantial" improvements to roughness and tolerance specs and a new higher-NA (0.33) mirror design enabling lower resolution. Carl Zeiss and Fraunhofer Institute also reportedly have developed a new collector mirror coating that enables an in-situ hydrogen cleaning process, improving collector mirror lifetime but still far below the lifetime that chip companies would require in a volume production environment.

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October 22, 2012 – In case anyone needed a reminder or a wake-up, new data from SEMI reiterates chip tool sales are slumping badly in the latter part of this year.

Worldwide orders reported by North America-based manufacturers of semiconductor equipment totaled $952.0M in September, -15% from August’s revised $1.12B level, but 2.8% higher than the same month a year ago. Billings similarly were down from August (-12% to $1.18B), but they’re also down -10.4% from a year ago.

The first half of the year was pretty good for semiconductor equipment demand, raising hopes of at least some minor full-year growth after a disappointing 2011 (particularly in the fall). It’s increasingly clear now, though, that the second half of 2012 is suffering from another investment slowdown. "In the current cycle, device makers are grappling with lower average selling prices and uncertainty with the broader economy, which clearly has a near-term impact on equipment purchases," noted Denny McGuirk, president and CEO of SEMI.

In the four months since peaking in May, equipment bookings have declined -40%, and are now right around where they were in the trough of Sept-Oct 2011, which was a two-year low point. Sales aren’t off by as much (-23%) but the dollar amount is also at the 3Q11 trough level. The B:B ratio has been plummeting since April when it was well above the parity level (1.12); it’s now at 0.81, meaning $81 worth of product orders are coming in for every $100 of equipment sold.

For the nine months through September, equipment orders tracked by SEMI are down -7% from the same period in 2011 to $11.9B. Sales are down -15% at $12.3B. SEMI’s official forecast, originally issued at SEMICON West, predicts an overall -2.6% decline for the year in global frontend + backend equipment.

Industry watchers and chipmakers were expecting a soft 3Q12, but holding out hopes for 4Q12 and especially 2013. Intel didn’t help with either timeframe in its 3Q12 results, when it announced lower overall 2012 capex and utilization rates slashed to 50% — and refused to forecast into 2013 spending due to visibility concerns, just two months away.

When something happens to a reticle, the consequences can be dire. Contamination in the wrong place on a reticle can result in a defect in every die of every wafer. Fabs have to keep their reticles clean.

On the other hand, if the reticle is cleaned too many times, the pattern can start to erode. Reticle pattern degradation eventually causes critical dimension uniformity (CDU) changes on the wafer, which can translate into issues of device performance or yield. Plus, while the reticle is going through the cleaning process, it’s not available to do its work in the scanner.  Unless reticle cleaning is carefully planned, production of that particular product may screech to a halt. Fabs need to check their reticles for contamination and pattern degradation—at a frequency that balances the cost of taking the reticle offline to inspect it and the cost of the inspection itself against the risk of printing reticle defects or CDU errors on the wafer.

Some fabs have moved their reticle cleaning facilities on site, greatly accelerating the turnaround time to get the reticle cleaned, re-inspected, and back online. New cleaning technologies have also come into favor, including wet processes like UV-ozonated water with hydrogen peroxide, and dry processes including plasma and laser shot cleaning. In general the new processes have resulted in reduced overall defectivity post-clean; however, the problem of pattern erosion remains, and the remaining defects can be more difficult to detect.

Recent studies1 have shown that contamination is more likely to occur at the edges of mask pattern features than in open areas between features. That’s bad news for the wafers, because a variation on the edge of the mask pattern will immediately affect the carefully engineered wavefronts of the light that transfers the mask pattern to the photoresist on the wafer. It’s also bad news for the reticle defect inspectors, because it’s much more difficult to detect a defect in an area of dense pattern than a defect the same size, sitting in the middle of an unused space. Also, the mask error enhancement factor (MEEF) of a defect within dense pattern is higher than that of a defect in open space—which means that the defect within the pattern is more likely to print on the wafer and more likely to affect die yield. It may be difficult to find defects on the edge of pattern, but these defects have the potential to be the most damaging. They must be found.

In the mask shop, reticle inspection is accomplished by comparing the pattern on the mask to the design information—a “die-to-database” inspection. In the IC fab, the mask database is often not available. For that reason, KLA-Tencor invented a database-free method for detecting contamination on a mask, a method called STARlightTM, named for its use of Simultaneous Transmitted And Reflected light. First introduced in 1995, the STARlight methodology2 compares the transmitted-light and reflected-light images of a reticle to determine whether or not a defect is present. Since then, STARlight has undergone many improvements, and today’s fifth-generation STARlight is optimized for detecting defects on edges of pattern features.

1. STARlight operated on the simultaneous transmitted (left) and reflected (middle) image to identify the defect (right).

STARlight addresses the issue of finding localized contaminants, even on pattern edges. It works for single-die, multi-die or shuttle masks (multi-die masks comprised of different die), inspecting any kind of random or repeating pattern—including the scribe line. Once these defects are found, the reticle can be cleaned and re-used.  But what happens when the cleaning process is modifying or removing pattern—material that’s supposed to be there—instead of contaminants?  Or what if the problem is not localized contamination, but a contaminating film that affects the reticle’s transmissivity? These issues may not create defects on the wafer, but they may affect the wafer’s CDU.

Some inspection systems now offer a mode that maps the reflectivity or transmissivity across the entire reticle. In some cases, these data are collected simultaneously with localized defect data. The reticle maps can then be processed and calibrated against a reference to extract CDU information.

2. Examples of intensity-based CDU maps from the reticle inspection system.

3. Degradation of a sub-resolution assist feature (SRAF), imaged by the reticle inspection system.

With the introduction of new cleaning processes and smaller pattern features, reticle management in the IC fab has extended beyond detection of localized defects to include detection of contaminating films and CDU changes. With thoughtful sampling strategies, regularly inspected reticles can live long, productive lives.

Rebecca Howland, Ph.D., is a senior director in the corporate group and Mark Wylie is a product marketing manager in the Reticle Products Division at KLA-Tencor.

Check out other Process Watch articles: “The Dangerous Disappearing Defect,” “Skewing the Defect Pareto,” “Bigger and Better Wafers,” “Taming the Overlay Beast,” “A Clean, Well-Lighted Reticle,” “Breaking Parametric Correlation,” “Cycle Time’s Paradoxical Relationship to Yield,” and “The Gleam of Well-Polished Sapphire.”

References

1. E. Foca, A. Tchikoulaeva, B. Sass, C. West, P. Nesladek, R. Horn, “New type of haze formation on masks fabricated with Mo-Si blanks,” Photomask Japan 2010.

2. F. Kalk, D. Mentzer, A. Vacca, “Photomask production integration of KLA STARlight 300 system,” Proc. SPIE 2621, 15th Annual BACUS Symposium on Photomask Technology and Management 112 (1995).

 

 

 

 

by Tom Morrow, executive vice president, Emerging Markets Group, SEMI

European government representatives, consortia and suppliers discussed programs to support and participate in the anticipated conversion of leading-edge wafer manufacturing to 450mm wafers at SEMICON Europa in Dresden. Possibly signaling a major change in the 450mm planning framework, representatives from G450C, imec, Fraunhofer IISB, and others discussed mechanisms for greater European participation, and emerging research initiatives, related to 450mm development. In addition, in probably the first major public discussion of the 450mm lithography system schedules following investments from TCMC, Intel and Samsung last summer, ASML provided a comprehensive presentation on their roadmap for 450mm EUV platforms.

Michael Liehr, newly promoted to executive Vice President of Innovation and Technology at the College of Nanoscale Science and Engineering (former IBM veteran, Paul Ferrar has been appointed General Manager, Vice President and coordinator of G450C project), provided an update on the consortium’s pilot fab, tool roadmap, wafer development, and wafer availability plans. Newly announced at Europa was G450C’s welcome of global collaboration efforts with regional consortia and government agencies. As a new consortium on the crowded stage of collaborative research development, G450C’s working relationship with other consortia in the industry has been an ongoing question for manufacturers, suppliers, and key stakeholders. G450C’s role in prequalifying tools for 450 wafer manufacturing places them in a powerful, central role in the future of the industry. With the industry consolidating and global R&D dollars needing increasing focus and efficiency, the roles, core competencies, and optimal distribution of research initiatives across the world is undergoing significant transformation.

"We’re looking forward to working with any regional organizations including wafer pool and adjunct tool demos," said Liehr during the session. While G450C priority remains on the specific program deliverables, Liehr spoke to the need to recognize and value the contributions of other players in global industry. He said that G450C selection, validation, evaluation of projects would proceed with criteria emphasizing technical and commercial transition value and that "G450C understands that public funding must be applied within the taxpayer region."

Liehr’s comments were welcome news to European consortia with a high stake in the semiconductor industry. The Fraunhofer-Gesellschaft network in Germany, for example, has 60 institutes, more than 1800 employees and an annual research volume of 1.65 billion euros (2010), of which 1.4 billion euros is generated through contract research. Lothan Pfitzner, head of department at Fraunhofer IISB provided an overview of his organization’s existing and planned activities in 450mm manufacturing process development. Pfitzner said Fraunhofer Group will support 450mm R&D&I activities based upon their strong expertise and experience in equipment assessment, manufacturing science (e. g. process control, automation, wafer handling, etc.), flying wafer concepts, green aspects, modeling and testing.

For reasons of cost optimization, Fraunhofer is also willing to reclaim 450mm wafers. In addition, Fraunhofer hopes to contribute in the area BEOL and of TSV in optimization of processes as well as in the area of metrology and defect detection and characterization. Part of these activities will take place at the Fraunhofer IISB Erlangen facilities.

Fraunhofer plays a key role in many current and planned public-funded research efforts related to 450mm manufacturing. The ENIAC EEMI450 is currently developing and evaluating wafer material, metrology tools, process equipment, and handling systems. The CATRENE NGC450 program is providing analysis and optimization of cluster platform performance. Planned programs under Framework 7 include SEA450 involving equipment assessment of cleaning and hot processing equipment and corresponding metrology tools. Another planned program is ENIAC 450EDL project involving virtual metrology and predictive maintenance models for 450mm metrology tools.

Imec, headquartered in Leuven, Belgium, has nearly 2000 researchers including more than 600 industry residents and guests, is also planning a 450mm pilot line to begin construction in 2013 and scheduled for completion in 2015. Phase one of the program is anticipating funding from the Flemish government, EU ENIAC FP7, and industry sources. Imec expects to play a key role in the acceleration of 450mm equipment development through installation of alpha and beta tools for early learning in an "industry-relevant technology flow." The organization’s track record of support for advanced process and lithography development is expected to be a key factor in securing a strong role in 450mm manufacturing programs.

Other European initiatives include those by Israeli "Metro450" Consortium comprised of five key companies: AMIL (metrology division of Applied Materials), Nova, Jordan Valley, Nanomotion, and Intel. University support comes from four institutions and public funding comes from the Israeli Chief Scientist budget. The regional interest in 450mm manufacturing stems from Israel’s strong success in wafer fab metrology, now accounting for over 30% of world’s share and approximately $1.3 billion in sales. Menachim Shoval, Metro450 Board Chair, said the transition of current 300 mm metrology solutions to 450mm manufacturing is not trivial and threatens their current world position.

Other regional interests expressed during the forum include those from the state of Saxony in Germany. Silicon Saxony, the organization representing the interests of the substantial semiconductor cluster, has a vision that by 2018 it "will be seen as a trendsetter for innovative semiconductor manufacturing technologies for 450mm and may plan to install its 1st 450mm manufacturing site in the Dresden region."

The scale and diversity of interests in 450mm is impressive, but a realistic forecast for European pilot lines and public funding is hard to gauge. Currently G450C plans to qualify "one or two…maybe three" tools per process, limiting broad supplier participation in future 450mm manufacturing. European efforts to supplement the G450C qualifying process may help open the participation opportunities for other companies in 450mm manufacturing, especially for European companies hoping to benefit from public funding. But significant EU and country funding of 450mm R&D is not yet assured. With the current European debt crisis and emphasis on austerity, significant funding for semiconductor R&D may be limited. Furthermore, there remains significant debate over research priorities with many in the European semiconductor community, including leading European device makers, favoring R&D emphasis on "More than Moore" programs.

Opening up the qualifying process for 450mm high volume production tools to European consortia would seem to benefit 450mm device makers, tool makers and the overall industry move towards 450mm wafers. In addition to expanding the number of qualifying tools and public R&D funding sources, European consortia can be expected to link important process development efforts in 3D transistors, 3DIC, and other areas with 450mm production requirements. Many of the current EEMI450 programs also feature unique approaches to metrology and material handling, adding an important "innovation" element to 450mm development efforts. At this stage of the 450mm transition, however, it is uncertain how likely G450C will move to open up their primary tool qualification role to organizations they may perceive as competitors. According to Liehr, "The same consolidation forces affecting device makers and suppliers are affecting R&D facilities. Specialization will need to be furthered so there is minimal overlap."

ASML begins 450mm development

Another noteworthy discussion in the European 450mm session was ASML’s plans for large wafer lithography systems to support high volume 450mm production. ASML successfully negotiated billions of dollars in capital investment by Intel, TSMC and Samsung this summer to support accelerated development of extreme ultraviolet (EUV) systems for 450mm manufacturing. Until a 450mm EUV lithography system is developed, 450mm pilot line development will utilize nano imprint technology, a significant R&D limitation according to many observers.

In perhaps the first public discussion of the company’s 450mm plans, ASML’s Frank Bornebroek discussed the product strategy and technology challenges for 450mm EUV systems. He described how ASML will now simultaneously develop four tools on two platforms to accommodate 450mm production. He said the initial versions will provide 30 wafers per hour in 2016-2017, extended to 60 WPH for EUV in 2018-2019. For immersion systems, ASML is targeting 50 WPH in 2016 and high volume systems in 2018.

While the company is committed to the G450C schedule for high volume production, significant technical barriers will need to be overcome. "It’s not just a scale up, but significant overlay improvements will be required…overlay drives patterning" said Bornebroek. "The larger the wafer, the more difficult it will be to improve productivity. We will need to accelerate 3-times more mass at 2-times more accuracy."

ASML is in process of hiring an additional 200 employees to meet the aggressive delivery goals. 450mm systems will require a "full base frame redesign" with major changes to chucks, mirror blocks, stages, tables and handlers, with adaptations to sensor and metrology systems. Bornebroek indicated that "450mm wafers will provide limited cost benefit for scanning systems."

October 17, 2012 – Industry watchers have been awaiting the worst after Intel lowered its 3Q12 expectations a month ago. In the end, the chipmaking bellwether produced better-than-feared results even with concerns about end demand.

Revenues for 3Q12 were $13.5B, at the cap of Intel’s reduced outlook, and gross margins were a notch better than warned (63.3% vs. 62%). Both were flat sequentially. Net income actually improved about 7% to $3.0B. Intel sees sales picking up a bit in 4Q12, to $13.1-$14.1B, though gross margins will slip to 55%-59% due to charges relating to excess capacity, what Intel CFO Stacy Smith characterized as "aggressive tactical actions." Those charges will be mostly restricted to 4Q and not beyond 1Q13.

"The enterprise PC market has gone relatively flat now," a reflection of cautious business end-demand, and this has "spilled over from the client side of the enterprise [to] data center server part of the enterprise," acknowledged Paul Otellini, Intel president and CEO, during the results conference call. Overall PC business growth was about half what is seasonal normal in 3Q12, and will be again in 4Q12 — the real question is whether that’s due to macroeconomic factors, or due to end demand awaiting Windows 8 and new PC/tablet/ultrabook refreshes in the coming months.

To that end, Otellini expressed optimism over demand in the near-term 4Q and beyond. "The world of computing is in the midst of a period of breakthrough innovation and creativity," he said, citing more than 140 core-based ultrabooks in the pipeline, a third of which will have tablet-like touch capabilities and many at or below the $699 price point.

In response to end-demand softness, Intel as expected is reducing its 2012 capex "pretty significantly" to $11.0B-$11.6B, a full billion dollars below its trajectory a month ago. CFO Stacy Smith reiterated the reasoning: reign in utilization to clear out inventory until demand recovers, and keep reusing existing equipment in its 14nm node efforts. "We are taking down utilization in the factories down to sub 50% again to take inventory out and free up the opportunity to move both space and equipment and redirect that to 14nm," noted Smith. He specifically declined to issue a forecast for 2013 capex, saying it will depend on unit growth and visibility into 2014 — but "right now we want to fight through a Q4 where we don’t have a lot of visibility before we lock in on a 2013 number."

We’ll be updating this story with analysts’ feedback about Intel’s results and its impact mainly on the semiconductor manufacturing ecosystem — but generally speaking, cutting over a billion dollars and capex, and acknowledging little visibility to even formulate (publicly) 2013 expectations, is likely to reverberate across the landscape.

October 16, 2012 – SEMI has extended the call for papers for the 2013 China Semiconductor Technology International Conference (CSTIC) to October 22. Paper abstract guidelines are listed here, and SEMI says there remain "just a few openings" for proposed talks on semiconductor technology and manufacturing. Original and overview papers from integrated device manufacturers (IDMs), equipment/materials suppliers, and academic and research institutes are welcomed.

The CSTIC (March 17-18 in Shanghai), held in conjunction with SEMICON China (March 19-21), is the largest annual semiconductor technology conference for the industry in China. (Last year’s CSTIC featured 100 technical lectures, 300 speakers, and nearly 1000 attendees.) Confirmed plenary speakers for CSTIC 2013 are RPI prof and Nobel Laureate Ivar Giaever, and "father of SOI technology" Ghavam Shahidi, IBM Fellow and director of Silicon Technology at IBM.

The CSTIC program offers 10 symposia covering all aspects of semiconductor technology and manufacturing, including a just-announced new track covering "circuit design, system integration and applications." Other tracks include: device engineering and technology; lithography and patterning; dry & wet etch and cleaning; thin-film technology; CMP, wafer substrate polishing and post-polish cleaning; materials and process integration for device and interconnection; packaging and assembly; metrology, reliability and testing; emerging semiconductor technologies; and advances in MEMS and sensor technologies.

SEMI and ECS are the organizers along with China’s High-Tech Expert Committee (CHTEC) with co-sponsors IEEE, MRS, and the China Electronics Materials Industry Association.

October 9, 2012 – Multiple reports summarizing this year’s International Symposium on Extreme Ultraviolet Lithography noted a mixed bag of results and updates: a few slippages in technology performance and roadmaps, some key improvements, and overall progress that’s still slow but in a generally forward direction.

It’s increasingly clear that EUV volume production is a matter of when and not if. "It is clear to us that the entire supply chain is beginning to support the technology," notes CJ Muse from Barclays. "EUV remains potentially the biggest product cycle in the history of semiconductor capital equipment," echoes Satya Kumar from Credit Suisse. (It’s a small supplier group poised to take advantage of that, though; ASML and Cymer, with other source firms making noise.) At the same time, for devicemakers, "EUV at high throughput is the best thing that can happen to leading-edge chip makers to counter rising capital intensity."

EUV source productivity remains the top concern, with a consensus at the symposium that EUV source productivity needs to "increase dramatically over the next 1-2 years" to push EUV lithography into high-volume manufacturing by the latest target date of 2014, reports imec which hosted this year’s EUV Symposium in Brussels in cooperation with SEMATECH and Japanese consortium EIDEC. Specifically, a reliable 200W source is needed by 2014 for initial cost-effective production — and followed by a push toward 500-1000W to keep the technology cost-effective down the long-term path of continued IC scaling. Reliability of sources has improved, though, and researchers are demonstrating ways to increase conversion efficiency to 4%-5%.

Progress is reported in another key hurdle, EUV mask handling, but imec acknowledges that availability of yielding masks to support pilot lines and later high-volume production "remains a serious concern." As a result, imec acknowledges that the EUV pellicle solutions are once again being explored to help mitigate the defect challenge.

Elsewhere, symposium presenters reported incremental improvements in resists to meet requirements of resolution, linewidth roughness, and sensitivity simultaneously. One identified issue is that best-performing resist materials sometimes show a lower photo speed that does not align with sensitivity assumed in the exposure tool suppliers’ productivity roadmap, imec notes. Another area of improvement, noted Kumar, is in line-edge roughness (LER) and line-width roughness (LWR), and how etch can play a role here. At 22nm half-pitch, <2nm LER/LWR is required; the NXE3100 shows around 4.7nm, an improvement from the alpha demo tool’s 5.9nm. Imec and Lam Research have developed a hydrogen passivation-based process to smooth and lower the LER/LWR down to 3nm, and see further room for improvement.

ASML

Source power improvements are tracking slower than expected, but more significant advancements are expected once the new ASML NXE3300B ships out in coming months, containing Cymer’s 2nd-gen HVM-II source, noted Kumar. ASML has tripled its EUV source manufacturing capacity to 23 "cabins" and is currently building seven systems of its anticipated 11 shipments in 2013. "We expect to see reports of substantial progress by SPIE in Feb. ’13" he writes. Specific anticipated improvements to the new ASML NXE3300B system include:

  • Higher transmission: The light enters the scanner at a steeper angle, resulting in lower energy loss as it reflects off the mirrors;

  • Better optics: Zeiss has "substantially improved the roughness and tolerance specs" to reduce aberration and flare (Barclays’ Muse pegs it as a 3× improvement in lens aberration). And a new mirror design allows a higher numerical aperture (NA) of 0.33, vs. 0.25 in the 3100 tool, enabling lower resolution — and Zeiss has a roadmap to get EUV NA to 0.6;

  • Better illumination: A new capability in the 3300B is "off-axis illumination" with no energy loss — yet another knob for lithographers to improve uniformity and resolution of printed features;

  • Wafer handling: Tighter overlay, faster speeds, and better matching between tools; and

  • A better source: The NXE3300B will incorporate Cymer’s new HVM-II source, which includes a pre-pulse option to improve power.

Cymer

Cymer’s source progress is "a mixed bag," with improvements on some metrics but missed targets on others, and some data not appreciably improved from SPIE in February, Kumar reports. Specifically, the throughput timeline to upgrade sources in the field has slipped by about six months from February targets (i.e. 50W sources in 3Q12), though better power performance is being seen on R&D sources. Similarly, Cymer reports improvements to the droplet generator (a new steering mechanism has improved tin droplet stability, points out Muse), but improvements to collector mirror lifetime are below targets.

Kumar cited comments from Intel’s IDF last month indicated that 50-70 wafers/hour throughput would make EUV acceptable for some applications. Samsung, meanwhile, wants to use EUV for some 20nm DRAM layers at throughputs barely half that (30 wph). Both Toshiba and Hynix said at the EUV Symposium that NAND throughputs need to be much higher (at least 125wph). Hynix added that doses have to be doubled to 22-24 mJ/cm2 to achieve necessary CD uniformity.

General consensus is that an ASML EUV litho system shipping in 2013 with Cymer’s HVM-II source at 80W power, 100% duty cycle, and a new four-amplifier configuration would support 40 wph throughput if it works as planned. 250W of power will be needed to reach 125 wph.

Cymer currently has 10 HVM-I sources, five of which are at customer sites, running 9-13W at 60% duty cycle and 0.5% dose stability — that’s behind Cymer’s progress expected at SPIE in Feb., which is now shifted to a target date of 4Q12. The previous 4Q plans were 100W operating power in continuous mode (with prepulse) at 0.2% dose stability; now the company plans 40-60W in continuous mode with prepulse, and unchanged 0.5% dose stability, by 2Q13.

Three HVM-I sources are kept in-house in Cymer’s San Diego facilities, with one being upgraded to 50W using the prepulse technology by 4Q12. (Two other HVM-I sources are at ASML.) Six of the new HVM-II sources are being built, four at Cymer and two at ASML, which will ship with the 11 3300B systems in 2013, Kumar noted.

Another mixed improvement is in the optics. Carl Zeiss and Fraunhofer Institute have developed a new collector mirror coating that enables an in-situ hydrogen cleaning process, improving collector mirror lifetime at least 45bb pulses on a customer-site HVM-I source — a 4× improvement from previous levels but equally lagging the 120-260bb pulse targets issued in February. (Apparently the mirror was removed at 45bb after a chamber leak, not a problem with the sputtering process, so that 45bb might not be the actual limit.) Cymer claims that 45bb pulses translates to four months of performance on ~100 wafers/day; Kumar extrapolates that volume production at 70wph would mean just 2-3 weeks of collector lifetime which would be "unacceptable for chip companies."

One key update to the EUV source is an improvement in Cymer’s "prepulse" technology. At SPIE in February the company said prepulse on its in-house HVM-I sources had shown 50W average power with high duty cycle but only for a short duration, and 90W in burst power at 20% duty cycle. That’s now been improved to 50W at 40% duty cycle but in a continuous automated mode for five hours (and 160W peak raw power on a development tool, notes Barclays’ Muse). Kumar translates this to 10wph throughput for five hours at 15mJ dose, which would double the output (to 200 wafers/day) with much better imaging results and 90% die yield. If Cymer can indeed deliver 90W power at 100% duty cycle with a 4-amplifier configuration by this time next year (2H13), chipmakers might have 40wph throughput in production — and we’ll start hearing more and louder rumbles of EUV production possibly in 2015.

Other sources

Cymer isn’t the only EUV source developer, though. Ushio (in what Kumar called "an enthusiastic presentation") reported 74W of power in burst mode at 12% duty cycle for a short 1hr run, better than the 30W/100% duty cycle and 37W/50% duty cycle it reported a year ago. The company’s source at imec (using 2 lasers to tailor the pulses) is exhibiting 10-12+J of energy, well improved from the previous version’s ~3J, notes Muse; the company cited specs of ~70%-80% average uptime, and hit ~96% uptime just days ago. A test source, Obelix II, supports very high (>250W) power at low repetition rates. imec, currently the only customer with an ASML 3300 and Ushio source, noted significantly improved uptime after a few Ushio hardware changes.

Still, Ushio "still has not demonstrated high power at high duty cycle, continuous mode operation for extended periods of time," Kumar notes. Its main problem is how to handle molten tin (don’t let it solidify and stay in the system), managing the extremely high electric field in between the drums as power is scaled up, and managing heat extraction from the drums. "Perhaps ASML may consider diverting a portion of the monies received from chip maker customers to keep Ushio’s R&D efforts alive," as a hedge against Cymer, Kumar writes. In the long run, though, "there will likely be only one source supplier," and he’s betting on Cymer.

Gigaphoton, meanwhile, "continues to make incremental progress" but "remains far behind" both Cymer and Ushio/Xtreme, noted Muse. Its Proto 2 source released this year with improvements to the droplet generator, CO2 laser, and EUV chamber is hoped to reach 50W clean power for 1 week stable operation by 1Q13, and a pilot tool ready later in 2013.

Mask inspection

KLA-Tencor says it shipped its first Teron 630 EUV inspection system on Sept. 25. The system, which uses DUV light with flexible illumination and polarization, takes 2-4hrs scan time, and can be extended from 22nm HP to 18nm HP. An actinic tool is under development, with a go/no-go decision needed by 4Q12; the company currently sees no showstoppers, though, and still expects to record actinic tool sales in 2015. This system takes 4-6 hrs for pattern reticles, Kumar notes, and pricing could exceed $50M.

Muse also pointed to another actinic light source from Swiss firm Adlyte, which showed its own high-brightness LPP EUV light source for actinic mask inspection. At SPIE in early 2011 the company described results of low conversion efficiency (about 1%) but respectable source brightness in a compact footprint requiring comparably lower power. Now, this "upstart company" has completed characterization of the engineering tool, with a prototype now in development and bill-of-materials procurement completed. Installation and integration is planned for 4Q12 and testing/demo in 1H13, followed by volume production.

Demonstrating brightness and cleanliness with improved positional stability is important, Muse notes, because of the critical need to perform metrology and inspection on what is printed via EUV. More players in this sector, besides KLA-Tencor and Applied Materials, is "a clear positive that the entire food chain is starting to support EUV," he writes.

Four of the leading micro- and nanoelectronics regions in Europe are joining forces to form a cluster alliance called “Silicon Europe.” The four groups, Silicon Saxony (Dresden/Germany), DSP Valley (Belgium), Minalogic (Grenoble/France) and Point One (Eindhoven/Netherlands), will be cooperating in research, development and business expertise.

Together they represent about 800 research institutes and companies, which account for more than 150,000 jobs; among the companies are global market leaders such as Philips, NXP, Globalfoundries, Infineon, STMicroelectronics, Schneider Electric und Thales.

This is a three year effort, as shown in the diagram. “We want to set up a joint action plan that is organized between the four clusters,” said Frank Bösenberg, in charge of administration of Silicon Europe, speaking at a press conference in Dresden. “Not only this, in the third year, we also want to start implementing this action plan. It’s not only about creating paper, but doing some action. In addition to this, we want to involve if possible additional European players.”


 “Global competition is tough and investments into European microelectronics are declining”, says Jean Chabbal, Chief Representative and CEO at the French Cluster Minalogic (Grenoble/France). In 2007 only 10% of all worldwide investments into microelectronics, around 28 billion Euro, went to Europe, while about 48% went to Asia. Since 2000 Europe’s market share in the semiconductor industry has dropped from 21 to 16 percent, yet the European microelectronics sector still employs 135,000 people directly along with another 105,000 in its supplier industries. “Europe is home to a number of the world’s best known, and most active regions in the micro- and nanoelectronics industry and the semiconductor industry, more specifically. These clusters, established over many years, with strong consolidated structures from industry, research and local governments, serve all application fields of micro- and nanoelectronics and have access to the most advanced research and key competencies – the European micro- and nanoelectronics sector must take advantage of this leading position and further expand upon it. This is the only way for Europe to maintain its role as a world-renowned leader in technology research and development”, continues Jean Chabbal.

Silicon Saxony (Dresden) is a unique conglomeration of companies with know-how in micro- and nanoelectronics, photovoltaic, organic and printed electronics, energy efficient systems, communications technology and sensor networks. More than 300 cluster partners employ 48,000 people. 

At the cluster Minalogic (Grenoble) 204 cluster partners with more than 39,000 employees develop modern micro- and nanoelectronics and integrated system-on-chip technologies. Their work applies to the sectors energy efficiency, connectivity and mobility, health systems and traditional industries. 

Point-One (Eindhoven) connects 170 cluster partners, who jointly develop solutions for mechatronics, integrated systems, photonics and micro-and nanoelectronics. Their solutions apply to lighting systems, to semiconductor and photovoltaic production and also the mobility, logistics and security branches. 

The 75 partners of the technology cluster DSP Valley (Leuven) are focusing on the development of hardware and integrated software technology for digital signal processing and system-on-chip solutions. 

Silicon Europe calls for a European ICT-Summit

 “Our activities and plans will not end at national borders as they did before – Silicon Europe stands for the common interest of the European microelectronics industry”, explains Peter Simkens, Managing Director at the Belgian Cluster DSP Valley. “However, to be successful in the long run, Silicon Europe and European microelectronics need active political support. We are appealing to all national governments to increase the synchronization of their economic and innovation policy with the European Commission and its guidelines. In order to realize this we are calling for a European micro- and nanoelectronics summit, which – similar to the German IT summit – shall bring together leading actors and decision makers from the European Commission, the national governments and all relevant branch organizations and associations. The European economy needs to expand on its strengths now, if it wants to remain competitive in the global market for the long run.”

Transnational Cluster Alliance as a new impetus

“Silicon Europe stands for a new quality of an European industry policy”, says Thomas Reppe, General Manager of the German Cluster Silicon Saxony. “In close cooperation with regional development agencies and institutes we transfer the cluster concept of Saxony’s Research Cluster for Energy Efficiency ‘Cool Silicon’ – the strong cooperation across organizational and institutional borders – onto a transnational level. Through this new and strong cluster alliance we are securing not only Europe’s current know-how in production of KET relevant technologies, but we are also working together on a strategic technology roadmap, which can serve the European Commission as a template and development guide for future programs.”

Silicon Europe offers a platform for active exchange among the clusters and their nearly 800 members, including internationally leading corporations; more than 75 percent of all partners are small and medium sized businesses. By performing a detailed analysis of each of the four cluster’s main research topics and by synchronizing their activities, previously unused synergies are being utilized.

Europe 2020

By intensifying transnational cooperation of regional research-oriented competence clusters, Silicon Europe will make a substantial contribution to “Europe 2020”, the EU growth strategy for the coming decade. The program’s focus is the advancement of research and development as a basis for a modern and strengthened European society. “With their activities, the European Commission aims at a digital and resource-efficient development – for both of these core goals micro- and nanoelectronics are a decisive factor”, says Eelco van der Eijk, contact person for the high-tech industry at the Dutch Ministry of Economic Affairs.  One of the key words for these activities is ‘smart specialization’ – the EU’s control mechanism to tailor and efficiently distribute development funds in the European technology regions.

Michael Kretschmer, Vice-Chairman of the CDU Parliamentary Group at the German Bundestag, member of the German Bundestag and member of the Committee on Education, Research and Technology Assessment explains his support for the initiative: “The Europe-Cluster of the micro- and nanoelectronics sites is a very important signal for both German and European politics. Together and across national borders we have to ensure that this key technology still has a home in Europe in the future. In the past, European clusters seldomly worked together – luckily, this is going to change now. I appreciate the Silicon Europe initiative and wish for it to find numerous supporters and advocates also in the German Bundestag and the German government. The high-tech nation Germany can simply not forego these technologies that by enabling innovations in various industries create jobs and prosperity”.