Category Archives: Semicon West 2013

When it comes to defects and contamination in the semiconductor manufacturing industry, most people tend to think of small, sub-nm defects at the transistor level. As important as those are, there are plenty of things that can go wrong and be seen at the macro level. Scratches, fingerprints, hot spots, spin defects, edge chips, poly haze, missing patterns, etc. are usually visible with the naked eye, perhaps aided by a green light or a microscope.

Fabs often do manual visual inspections, but it tends to be fairly random, only sampling a few wafers at a time. “You put some wafers on the screen, and you look sporadically at five, ten points on a few of the wafers,” notes Reiner Fenske, founder, CEO and president of Microtronic (Hawthorne, NY). “If you find something, typically it’s very difficult to feed that information forward. You might take a picture, but then where does that picture go?” It’s also difficult to compare defects, such as scratches, with previously seen defects. “How many scratches did you have last week? Does that scratch look like the one that you had last night?” Reiner asks.

An automated macro inspection tool – such as the newly released Microtronic EAGLEview 5, which will be running wafers at North Hall Booth #5467 at Semicon West this week — solves those problems, without requiring any recipes and quickly scanning every wafer in the cassette, noting and logging various defects. The EAGLEview 5 represents a big upgrade over the company’s previous offering. “There’s really a dramatic difference in terms of defect detection, defect resolution, defect sensitivity, and there’s no hit to throughput, so we’re still looking at 3,000 wafers a day, which is incredibly fast,” said Mike LaTorraca, Microtronic’s Chief Marketing Officer. Errol Akomer, Applications Director at Microtronic, adds that in addition to the higher resolution, it’s a much cleaner signal. “The signal-to- noise ratio is much better — there’s a 5X improvement in that as well,” he said. Internally developed software algorithms also results in less nuisance defects and increased defect detection.

With these new capabilities, LaTorraca said they’ve created a bridge between micro and macro, and manual and automated. “We can take manual microscope images and put them into the same software that runs on EagleView. We can start to integrate defect information and the actual defect images from the manual microscope world into our tool, and that gives the fab owners a much more unified approach, a better, more comprehensive view, to make better decisions,” he said.

EAGLEview 5 is equipped with advanced imaging technology, analytical software, robotics and a 4-cassette multi-size (100mm-300mm) wafer platform. EAGLEview ProcessGuard Client Software provides defect visualization, digital guard-banding, wafer randomization/slot positional analysis, together with integration with manual microscopes for fab-wide defect tracking and reporting.

Every wafer is automatically OCR read, imaged, 100% inspected and stored for any step throughout the manufacturing process providing a comprehensive, centralized record – or ‘waferbase’ – that is also compatible with the fab’s manual microscope inspection data providing a more integrated, wholistic view of both micro and macro defects.

EAGLEview 5 acts as a hub for defect management across the fab by integrating manual microscope inspection, high resolution EAGLEview wafer images. EAGLEview 5 replaces legacy manual/micro wafer inspection by automating and standardizing wafer inspection processes. Blindly sampling 5 sites on a wafer is no longer needed. The newly developed ProcessGuard microscope interface software records micro defect classifications. This coupled with on-board commonality analysis allows root cause to be determined for micro defects and breathes new life into existing microscope inspection strategies. EAGLEview was originally designed to be comparable to naked eye 1x green light inspection.   EAGLEview 5 shifts the line between a macro green light inspection and microscope inspection.

“You can put all the micro defects into our database in the same ways you did the macro, so you classify your macro defects and you classify all your micro defects,” Fenske explained. “Now you have a record of what, where, how many, and because we collect all the history of where the lot went to, which tools it went through, we can then use that information to do commonality studies to figure out which tool caused the problem. With the microscope, there hasn’t been that type of integration, so we can now take all of those legacy things everyone needs to use and actually give them a new life.”

EV Group (EVG), a supplier of wafer bonding and lithography equipment for the MEMS, nanotechnology and semiconductor markets, today announced that it has established the NILPhotonics Competence Center, which is designed to assist customers in leveraging EVG’s suite of nanoimprint lithography (NIL) solutions to enable new and enhanced products and applications in the field of photonics. These include light emitting diodes (LEDs) and photovoltaic (PV) cells, where NIL-enabled photonic structures can improve light extraction and light capturing, respectively, as well as laser diodes, where photonic structures enable the tailoring of device characteristics to improve performance. The NILPhotonics Competence Center includes dedicated, global process teams, pilot-line production facilities and services at its cleanrooms at EVG’s headquarters in Austria as well as its subsidiaries in North America and Japan.


“Nanoimprint lithography is an enabling technology for the design and manufacture of all kinds of photonic structures, which can significantly shorten time to market and lower cost of production compared to conventional technologies, such as electron-beam writing and stepper systems for optical lithography,” stated Markus Wimplinger, corporate technology development and IP director at EV Group. “For example, compared with conventional lithography, our full-wafer nanoimprinting technology can pattern true three-dimensional structures in the sub-micron to nano-range as well as features as small as 20nm, which opens up a range of new photonic applications. With our NILPhotonics Competence Center, we’re not just providing our customers with the most advanced NIL systems; we’re also working closely with them during product development to help them determine how best to optimize their product designs and processes to take advantage of the resolution and cost-of-ownership benefits that NIL brings.”

The new NILPhotonics Competence Center builds on more than 15 years of NIL experience at EVG with the largest installed base of NIL systems worldwide. EVG’s NIL equipment portfolio includes the recently introduced EVG7200 UV-NIL system, which supports EVG’s next-generation SmartNIL large-area soft NIL process for high-volume manufacturing. The EVG7200 with SmartNIL provides unmatched throughput and cost-of-ownership advantages over competing NIL approaches.

Zvi Or-Bach, President & CEO of MonolithIC 3D Inc. blogs about the appearance of 3D integration on several roadmaps.

At the recent CEA Leti day, that took place as part of Semicon West2013, Laurent Malier, Leti CEO, presented his “A look at the coming Decade.” Slide 15 of the presentation provides Leti’s vision for CMOS roadmap:

Monolithic 3D is presented on Leti’s roadmap as the technology to follow the 7nm process node.

Early this year we blogged IEDM 2012: The pivotal point for monolithic 3D ICs. It is now quite reassuring to see monolithic 3D now as part of the industry roadmap. We discussed then that memory vendors are already gearing up for volume production of the 3D NAND. And, indeed, just this summer, Toshiba has been reported to leverage the monolithic 3D cost reduction advantage (Toshiba to Build Fab for 3D NAND Flash). It only makes senses for the CMOS market to follow.

Doubters would ask why the industry would introduce a new dimension to the roadmap that has been extremely successful for over 40 years. The answer is very simple – because it is not so successful anymore. We are all aware that the escalating costs of lithography had diminished transistors cost reduction, as is illustrated in the following ASML chart:

Even if we ignore the cost issues we should remember IBM’s Bernie Meyerson caution that “atoms don’t scale.” We are quickly approaching these limit as is visible on the following Intel chart:

Accordingly, Mike Mayberry, director of component research at Intel, said at the recent IMEC Technology Forum that he“has looked down the highway of conventional silicon development and reckons things become foggy beyond about the 7-nm node.” In fact, in his March 2013 presentation “Pushing Past the frontiers of Technology” Mike Mayberry also presents monolithic 3D on his road map:

This transition was well captured in the title of 2011 IEDM keynote address by Mark Bohr, the Senior Fellow of Technology and Manufacturing Group and a Director of Process Architecture and Integration of Intel, “The Evolution of Scaling from the Homogenous Era to the Heterogeneous Era.”

This Blog was prepared by Israel Beinglass, CTO of MonolithIC 3D Inc.

Like every Semicon West show in the past, where many experts are brought together for showing the latest and greatest semiconductor manufacturing equipment and bringing numerous seminar/panel discussions, this Semicon West of 2013 was no different. Two major issues were discussed, which on the face of it look unrelated, that caught my attention:

Progress in 3D –TSV technology, and EUV.

Obviously these two issues are very different, but they are quite similar in respect to the following:

1. As the advanced node progresses to smaller and smaller feature size we are getting closer to the “end of the roadmap” or the “end of Moore’s law”.

Going to EUV does alleviate some of the problems related to the current solution of double patterning (or quadruple in the future assuming, EUV doesn’t come to fruition soon enough).

As well, utilizing 3D devices with TSV has, in the grand scheme, a similar outcome; namely, advancing the integration via 3D structures rather than continued scaling. Though in the future, 3D devices and advanced nodes could go hand in hand.

2. The big miss of the roadmap. When one looks at some old roadmaps from a few years ago, one can ask how did we, the industry, miss by so much?

This actually reminds me of another miss from a few years ago-the low k inter-metal dielectric. Fig. 1 shows the low k dielectric roadmap trend of various ITRS published roadmaps and the prediction in 1999 that by 2004 we would be using k<2 !! Obviously we know what happened and even today 14 years later it is hard to breakthrough a k value of 2.5.

Figure 1: low k Dielectric roadmap

Figures 2 and 3 show the roadmap for EUV and TSV, respectively. Both are of 2009 vintage. In each case the prediction of the roadmap vs. actual is startling.

Figure 2: EUV roadmap

Figure 3: TSV roadmap

It is not the purpose of this blog to go over the reasons why the roadmaps of EUV and TSV missed the time table by miles, nor to blame anybody for it. There are many articles and discussions published on the subjects. Rather, I will touch on some of the highlights as well as try to make some conclusions regarding the pathway of the industry regarding these two important technologies.

EUV The EUV technology has so far gone through monumental achievements vis-à-vis the incredible tasks of developing the next generation stepper technology. The amount of engineering and resources poured into it is unprecedented in the short history of the semiconductor industry and maybe so for other industries.

It looks like as I write this blog that the only barrier for the technology from becoming a HVM tool is EUV source power that can provide a high enough throughput. Many experts doubt that it could ever be achieved; however, there are many other experts saying that it is within a reach.

TSV In this case I could see two totally unrelated issues:1) technology driven obstacles, and 2) logistics and supply chain issues.

In the case of the TSV it is one of the few cases where the “power point” presentation(s) of the TSV idea are so convincing that it is actually hard to oppose it. However, when it comes to the fine details of the technology development, there are many issues that still need to be addressed and resolved. I believe that it is just a matter of time before the technical obstacles will be resolved and a unified standardized solution emerges. However, on the other hand, I see a real problem from the point of view of logistics, cost and supply chain of the technology, and I have some doubts if it can ever be resolved. For further discussion on this issue, please refer to: 3D IC Supply Chain: Still Under Construction, and to a detailed comment in EE Time published blog and comments re. Semicon West 3D –IC TSV, provided here below.

In summary, I believe that the industry will come with a solution for EUV before TSV becomes a production technology.

Yet there is another alternative to TSV and to EUV – it is the Monolithic 3D methods. Moreover, it is very likely that monolithic 3D will reach volume production before EUV and TSV, as we already see the  NAND Flash vendors ramping up for production of 3D NAND.

Zvi Or-Bach, President & CEO of MonolithIC 3D Inc. blogs about an ASML presentation from Semicon West. This is a follow up to a previous post: "Dimensional Scaling and the SRAM Bit-Cell."

I just downloaded the ASML presentation from Semicon West2013 site – ASML’s NXE Platform Performance and Volume Introduction. Slide #5  – IC manufacture’s road maps – says it all.

Embedded SRAM will scale from 0.09µm² at 22-20nm node to 0.06µm² at 11-10nm node. In other words only 30% reduction instead of the 4x reduction expected of historical dimension scaling, to roughly 0.02µm² !!!

In our previous blog that followed ISSCC 2013 we saw some early indication of this slowdown.  Yet we were still surprised to realize how bad it really is. This might explain why after resisting IBM and other pushes for embedded DRAM, Intel announced few month ago that its Haswell processor will incorporate embedded DRAM after all.

Another point from this ASML slide is the adaption of monolithic 3D by the NAND Flash vendors. We believe this is a start of a trend, and that logic vendors has now one more reason to follow it.

DAS Environmental Expert GmbH of Dresden, Germany, has developed SALIX, a point-of-use system for removing waste gas pollutants in semiconductor wafer manufacturing wet bench applications. This solves a common problem where gases from the solvents, acids and alkaline materials used in wet processing combine to form a powder in the exhaust line. This powder can be a “toxic bomb” according to Dr. Horst Reichardt, CEO and president of DAS, or at least cause throughput and cost issues since the exhaust may have to be cleaned every one to two days.

The single-wafer cleaning process widely used for cleaning 300-millimeter wafers in wet benches distributes cleaning agents onto rapidly spinning single wafers and spins them off at the edge where baffle plates within the system collect the water, acidic and alkaline chemicals, and volatile solvents (the process for cleaning 200-millimeter wafers immerses the entire cassette). A large fab may have 20-30 such wet benches. With up to 12 stations per wet bench and exhaust from each chamber requiring several exhaust systems, the SALIX scrubber eliminates the need for elaborate change-over modules to avoid deposition in the pipes. It is more cost-effective and efficient at preventing clogging than conventional approaches used to separate and extract the acids, alkalines and solvents in the exhausts which require separate suction to prevent particle buildup and condensation within the pipes.

In contrast, SALIX removes the harmful substances from the gas stream directly at their point of origin using a two-stage scrubber process of chemical and physical absorption, and can treat up to 3600 m3/h of raw gas. Separate inlets feed the harmful gases from the wet bench process chambers into a SALIX pre-scrubber that pre-cleans the gas using spray nozzles. Next the waste gases pass into the first scrubber stage and then a second stage that uses a different scrubbing liquid. The remaining clean gas then can be released safely into the air without any danger to the technology or the environment. Because the SALIX system does not require any air dilution, the clean air remains in the clean room, further reducing cost.

Dr. Guy Davies, director of the Waste Gas Abatement business unit at DAS Environmental Expert explained, “When a global foundry based in Taiwan came to us seeking a better solution to treat water-soluble exhaust gases from a wet bench application, we installed SALIX as a first-of-its-kind point-of-use system. It has been running there since January of this year and, after six months of operation, emissions measurements show zero harmful substances in the exhaust. One SALIX system per wet bench is all that’s needed, and just one pipe for the cleaned exhaust. Salix “offers a smaller footprint with no switching boxes needed, and is far more cost-effective and efficient than central scrubbers for treating processes that create water-soluble waste gases. We believe our proven SALIX solution, which is SEMI S2 international and German TA-Luft standards compliant, opens new markets for point-of-use scrubbers in the semiconductor, LED, PV and FPD industries. In fact, we have seen increasing interest in SALIX and already have received multiple inquiries from U.S. customers. In addition, we are using the evaluation results for further process-based optimization and have developed a custom fit bypass function that will enable production to continue with no interruption.

DAS also announced it has added Technica, U.S.A. as a new local service partner to deliver faster response time for service and maintenance for U.S. customers.

Engineering samples of The Hybrid Memory Cube (HMC) are expected this summer, with high volume manufacturing coming next year. It will be one of the first high volume devices employing 3D integration and through silicon vias (TSVs), employing a bottom logic layer and 4-8 stacked DRAM layers.

The HMC is the result of a consortium formed in late 2011 by Micron, Samsung, Altera, Xilinx and Open-Silicon to define an industry interface specification for developers, manufacturers and architects of high-performance memory technology. The consortium has grown to 110 members, including SK Hynix, IBM and ARM. Analysts are projecting the TSV-enabled 3D market to be a $40billion market by 2017, or roughly about 10% of the global chip business.

We caught up with Micron’s Scott Graham, General Manager, Hybrid Memory Cube, at Semicon West. “Today, we’re very close to delivering our engineering samples this summer to our lead customers that are taking the technology into their system designs,” Graham said.  The lead applications are in high performance computing, such as supercomputers, as well as the higher end networking space. “Those will be the early adopters. As we move forward in time, we’ll see that technology evolve as costs come down for TSVs and manufacturing technology, it will enter into future space where traditional DDR type of memory has resided. Beyond DDR4, we can certainly see this of memory technology being a mainstream memory,” Graham said.

Since the HMC is an open specification in terms of the architecture of the device, it will be up to each memory manufacturer to decide how it might be customized and manufactured. “The way it’s done today is we source the substrate, we source the logic layer and then we bring those in-house and we complete the finishing of those logic wafers as well as all the slicing, dicing, stacking, assembly and test,” Graham said. “What we end up providing for the customer is a known good cube, or known good piece of memory, just like we would if it was a DDR device or wide I/O device,” he said. He added that the HMC is designed so that it has not only the repair capability during manufacturing but also out in the field. “It’s very flexible and very robust, so reliability is very high with this device,” he said.

The consortium delivered its first specification earlier this year. “We’ve since extended the consortium to work on both future generations of the HMC technology in both the short-reach and ultra-short reach configurations,” Graham said.

The HMC was designed to get high density and high bandwidth in a relatively small package. The team adopted an off-the-shelf SERDES I/O and that’s based on IBM’s 32nm process. “With that, we can achieve 10 Gbps, 12.5 Gbps, or 15 Gbps for those SERDES links,” Graham said. “If you look at a 2 GByte or a 4GByte HMC device, those first devices will deliver a total aggregate bandwidth of 160GBytes/sec. I want to emphasize those are bytes not bits. It’s a very high bandwidth and low energy per bit device that is something that can be designed into a multitude of systems.”

The consortium has several generations of the HMC device planned (this summer’s engineering samples are Gen2). “As we move forward, you’ll see us moving into the 28 Gbps SERDES as far as the I/O goes,” Graham said. Bandwidths are going to be 320 Gigabytes/sec and higher, and the density will be in 4Gbyte and 8 Gbyte configurations.

Graham said one of the main challenges they had to overcome was the stacking. “We’re stacking a logic layer on top of a substrate and then four to eight DRAM on top of those logic layers,” he said. “We have over 2000 TSVs in this package and it was a challenge to stack these ultrathin die and make sure that what we end up with is a high performance and very reliable package.” Graham declined to comment on the exact TSV process flow used at Micron, saying only that it was leading edge. “We had to make sure our equipment partners were up to speed and could deliver us the technology that would allow us to manufacture this in high volume,” he said.  

Because customer can customize the HMC design, another challenge it to make sure that the design capabilities are available at the foundry for that logic layer, Graham said.  

Heat dissipation in the device is achieved through a metal lid, and through the TSVs which acts as chimneys (in addition to conducting electricity). The photo shows two Gen2 HMC devices. The larger one, in a 31mm x31 mm package, is a 4 link device that will achieve 160 Gig-bytes per second. The smaller one is a two link device capable of 120 Gigabytes/sec, measuring 16mm x 19.5 mm. “Both are being manufactured now in our plant and we’re doing the whole debug phase,” explained Aron Lunde, program manager, DRAM solutions group at Micron in Boise. He said the metal lid was in contact with not only the top layer, but different internal layers. “We call it an integrated heat spreader. It makes contact at more than one level and that’s what really helps,” he said.

Although manufacturers such as Micron, Samsung and SK Hynix must now handle the manufacturing, assembly and test process, Graham believes that it could eventually evolve to the point where select foundry partners would be able to provide volume manufacturing services for these HMC cubes.

Graham said DDR4 will likely be the last DDR device. “Beyond DDR4, you have to move to managed memory like HMC technology,” he said.  “We’re solving the memory wall problem with HMC-like architecture and what’s really going to be happening in the future is that you’ll be running into a CPU wall. That’s going to be the barrier to system progress as we move forward.”

Graham expects some challenges with scaling of conventional memory at sub-20nm process nodes. “We get into physical challenges of meeting the timing requirements and the 12 pages of JEDEC specifications to be able to yield properly and to be able to provide a cost-effective memory device moving forward,” he said.  

Although the HMC is now designed around DRAMs, Graham said it would be possible to use other types of memories, and even a mixed set of memories. He noted Micron is looking at alternatives to the conventional DRAM cell, such as spin torque and resistive memories. “Micron is investing heavily in research in those technologies and of course the HMC team here at Micron is looking at future technologies that we can take HMC architecture and be able to utilize different DRAM or even flash types of memory,” he said. “As the technology matures and it becomes lower cost, we can see this technology certainly evolving into more global applications and utilizing different memory types in that stack – and perhaps even multiple memory types in that stack.”

HMCs could eventually make their way into mobile devices, but Graham said that is likely to be three or four years away. Mobile applications presently employ low power DDR3 solutions, which will be used for several years. “We’ll see quite a few interesting designs start spinning when the mobile folks see they can differentiate with a managed memory solution. It’s not going to be HMC as we know it today, it will have to be optimized for mobile,” Graham said.

Following last week’s formal announcement from Governor Cuomo of the formation of the Facility 450 Consortium (F450C), ten leading nanoelectronics facility companies from around the world will collaborate at CNSE to lead the global effort to design and build the next-generation 450mm computer chip fabrication facilities. At the semiconductor industry’s annual SEMICON West tradeshow, taking place at the Moscone Center in San Francisco, CA on July 9-11, the F450C will host its first public panel discussion about facility and infrastructure solutions for the transition to 450mm wafer fabrication.

Who: Members of the Facility 450 Consortium (F450C)

What: Panel entitled: The 450mm Facility; F450C’s Parallel Pathway

When: 4-5 pm on Tuesday, July 9

Where: The Impress Lounge, located at the B Bar above Moscone’s North

Why: Beyond the manufacturing hurdles that 450mm wafer processing brings, next generation fabs present new challenges with respect to the design of the facilities, substrate handling, tool connection, chemical distribution, water and electrical systems and many other areas. Where the G450C provides leadership in the area of 450mm equipment and process technologies, the goal of the F450C is to develop facility and infrastructure solutions essential to the transition to 450mm wafer fabrication.

On the Agenda:

  • Allen Ware, M+W Group & F450C: An Introduction to the F450C
  • William Corbin, G450C: Design to Requirement at the Utility Level
  • Adrienne Pierce, Edwards Vacuum: The ŒGreen Pump Strategy
  • Lothar Till, Ovivo: Water Use at 450mm

To register for the event please RSVP to [email protected]

The Facilities 450mm Consortium (F450C) is a first-of-its-kind partnership at SUNY’s College of Nanoscale Science and Engineering (CNSE) that is leading the global effort to design and build next-generation 450mm computer chip fabrication facilities. The collaboration includes 10 of the world¹s leading nanoelectronics facility companies, including Air Liquide, CH2M HILL, CS Clean Systems, Ceres Technologies, Edwards, Haws Corporation, Mega Fluid Systems, M+W Group, Ovivo, and Swagelok. Members of F450C are working closely with the Global 450mm Consortium (G450C), as announced by New York Governor Andrew M. Cuomo, to identify viable solutions required for 450mm high-volume facility construction, with initial focus areas to include reducing tool installation cost and duration, and improving facility sustainability.

SEMI today announced that Ajit Manocha, CEO of GLOBALFOUNDRIES, has been selected to receive the “SEMI Outstanding EHS Achievement Award — Inspired by Akira Inoue.” The Environment, Health and Safety (EHS) Award is sponsored by SEMI and will be presented on July 9 at 9:00am during the SEMICON West 2013 Opening Keynote and Ceremonies in San Francisco.

“We are pleased to present this award to Ajit Manocha for his outstanding contribution and commitment to EHS issues," said Denny McGuirk, president and CEO of SEMI.  “Ajit joins a distinguished group of semiconductor executives who have been honored by our industry for notable EHS achievement and leadership.”

“Excellence in Environment, Health and Safety is not only a mandate that we set for ourselves, but a fundamental expectation of our customers and the communities where we operate,” Manocha said. “Corporate responsibility is fundamental to our culture and our value proposition to our customers, the communities in which we live and do business, and our full range of global stakeholders.”

Manocha heads GLOBALFOUNDRIES Executive Stewards Council (ESC), the leadership forum for strategic direction and accountability for risk management, corporate responsibility and sustainability.  Manocha’s leadership has resulted in significant EHS achievements at GLOBALFOUNDRIES. Those cited by the Award committee in the selection of Manocha include:

  • Zero-Incident Safety Culture — GLOBALFOUNDRIES safety goal is to continually reduce all injuries and Manocha continually challenged the EHS and project management teams to achieve zero incidents. For example, Manocha ensured that there was a strong focus on safety metrics in the executive project reviews of the new Fab 8 in Malta, New York. GLOBALFOUNDRIES’ Singapore Fabs all received “Silver Awards” for Health and Safety presented by the Workplace Safety and Health Council and supported by the Singapore Ministry of Manpower.
  • Commitment to Eco-Efficiency in Foundry Operations — In 2012, GLOBALFOUNDRIES set corporate environmental goals to reduce GHG emissions 40 percent by 2015, electricity consumption 35 percent by 2015 and water consumption 10 percent by 2015, all normalized to a manufacturing index and compared to 2010.  Fab 8 incorporates multiple energy efficiency measures, waste heat recovery, and “idle mode” for abatement systems and vacuum pumps. Fab 1 in Dresden is powered by two energy-efficient tri-generation power plants that provide electricity, heating and cooling to fab operations, GLOBALFOUNDRIES’ Singapore utilizes reclaimed NEWater for incoming supply and achieved an energy reduction of 50 GWh in 2012, with a 2013 goal of a further 57 GWh reduction.
  • WSC Commitment to Best Practices for Perfluoro-Compound (PFC) Reduction — At the 2012 annual CEO meeting of the World Semiconductor Council (WSC), Manocha led the discussion of EHS topics, urging his fellow CEOs to take action to protect the environment, conserve resources, and achieve the WSC’s PFC reduction goal. GLOBALFOUNDRIES’ newest U.S. fab, Fab 8, meets the WSC Best Practice commitment for PFC emission reduction, and Fab 1 has incorporated best practices for PFC reduction since 1999.
  • WSC Commitment to a “Conflict-Free Supply Chain” — At the 2013 WSC meeting, Manocha  championed a “Conflict-free Supply Chain” policy to address concerns related to sourcing tantalum, tungsten, tin and gold from “conflict regions” of the Democratic Republic of Congo and adjoining countries. The WSC subsequently adopted such a policy. For its part, GLOBALFOUNDRIES has already met customer requests for “Tantalum Conflict-free” products in 2012.

In addition to receiving the EHS Award at SEMICON West, Manocha will deliver the Opening Keynote for the event on July 9 at 9:00am at Moscone Center (Esplanade Hall, Keynote Stage) in San Francisco, Calif.  For more information about SEMICON West — including registration and keynote attendance —   visit

The “Outstanding EHS Achievement Award — Inspired by Akira Inoue” is sponsored by the EHS Division of SEMI. The award is named after the late Akira Inoue, past president of Tokyo Electron Limited and a strong advocate of EHS. Inoue also served on the SEMI Board of Directors. The award recognizes individuals in industry and academia who have made significant contributions by exercising leadership or demonstrating innovation in the development of processes, products or materials that reduce EHS impacts during semiconductor manufacturing.

Past recipients of the SEMI EHS Akira Inoue Award include: Richard Templeton (president and CEO, Texas Instruments), Atsutoshi Nishida (president and CEO, Toshiba), Dr. Jong-Kap Kim (chairman and CEO, Hynix Semiconductor), Dr. Morris Chang (chairman and CEO, TSMC) and other prominent industry leaders.



Europe’s recently launched industrial strategy to reinforce micro- and nanoelectronics manufacturing is more than just a vision — it’s a major opportunity for equipment and material suppliers to participate to large-scale investment projects, increase their holding in key technologies and reach out to new customers and markets. Implementation is already underway: the first EU funding calls for projects will start at the latest in early 2014 and discussions are already underway on investment priorities.  The recent launch of five EU projects, worth over €700 Million and bringing together over 120 partners, around 30 percent of which are small and medium enterprises, is proof that Europe can put its “money where its mouth is.” So what should you be doing to join the 10/100/20 momentum?

10/100/20 in a nutshell

Dubbed the ‘10/100/20’ strategy, the EU initiative will see €10 billion worth of EU co-funded projects (public/private investment), coupled with €100 Euros investment by the industry with the goal of 20 percent of global chip manufacturing by 2020. The aim is to focus on Europe’s strengths, pool together EU, national and regional resources and invest in specific areas that can give Europe a competitive edge globally. EU investment will cover the entire semiconductor manufacturing supply chain, from research to design and device makers. Maintaining leadership in equipment and material supply is clearly stated as an objective of the EU’s strategy, as is the integration of small and medium enterprises (SMEs) in value chains and providing them access to state-of-the-art technologies and R&D&I facilities.

Why get involved, especially as a SME

A number of companies, and small and medium enterprises in particular, may shy away from EU projects, perceiving them to be too complex to access and placing too much of an administrative burden for little financial gain. But the true value of EU projects lies in the new network you have access to: a variety of companies across the supply chain, many of who will become your new customers, and access to state-of-the-art research facilities and technologies. Take the example of the five pilot lines recently launched with combined funding from the EU, national governments and partner companies under the ENIAC program:

The European 450 Equipment Demo Line (E450EDL) will support the equipment and materials industry in the 450mm wafer size transition. 43 partners from 11 European countries will develop and test lithography, front end equipment, metrology tools and wafer handling and automation equipment. The partners include the large European research centers and equipment and device manufacturers, as well as smaller companies. The demo line will provide a world-class research infrastructure to validate tools that remain at the manufacturers’ sites, thus giving suppliers access to state-of-the-art facilities and an opportunity to share the knowledge and financial burden of testing their products. The Lab4MEMS project will create the first European pilot line for innovative technologies on advanced piezoelectric and magnetic materials, including 3D packaging, offers SMEs and fabless companies a manufacturing route for their future projects that has been difficult to access so far.

Interested? So what’s next?

Now is the time to decide on the technology trends that you want your company to follow and start reaching out to your partners and customers. If you think your technology could give Europe a competitive edge and should be part of Europe’s investment strategy, then start talking about it, show its benefits and convince people that this is the way to go. In the case of EU projects, there is strength in numbers, so start talking to your customers and your suppliers, look at what others are doing, and see how you can fit into the technology and investment trends.

The EU pledge of €10 billion worth of public/private co-financed projects will be spent gradually in the form of regular EU funding calls, the first of which is expected by end 2013. The call will set the overall requirements for project ideas: what technologies the project should focus on, what parts of the value chain should be partners to the project, the estimated overall budget and duration of the project as well as the technical details for applying for EU funding.  By the time the call has been published, you should already have an idea of what it is you want to do, who you want to work with and how you can fit your idea into the investment priorities that will be announced.

How to get connected

If you are visiting SEMICON West in San Francisco, then mark your calendar for Wednesday, July 10. At 16:00/4:00pm there will be a presentation of the new 10/100/20 strategy for Europe at the TechXpot in South Hall. Join us to find out more about the new strategy, why it’s important and how to get involved.

Your next major opportunity to meet with the equipment and materials industry, learn about the latest technologies and discuss the EU strategy is SEMICON Europa 2013 (8-10 October, Dresden, Germany).  Our programs will cover each of the major projects, including 450mm wafer processing, power electronics, MEMS, FDSOI as well as advanced packaging including 3D and TSV technologies.  They will in one way or the other all address Europe’s 10/100/20 strategy. The SEMICON Europa Executive Summit will discuss implementation of the strategy and we are also organizing an EU funding workshop with hands-on advice about how to identify funding opportunities for your company and join EU projects.

For more information on SEMICON Europa, please visit: The event in Dresden will again be co-located with Plastic Electronics Europe. The conference and exhibition is the leading international technology-to-industry and industry-to-industry event focused on organic and large area electronics. It is the premium forum in its kind where professionals in the area and from around the world meet to present and to discuss progress of topics. For more information, please visit: