June 22, 2011

June 21, 2011 — The JEDEC Solid State Technology Association published a significant revision to JESD9B, Inspection Criteria for Microelectronic Packages and Covers.

JEDEC standard JESD9B allows users to verify quality and requirements of microelectronic packages and covers (lids) on hybrid microelectronic circuits/microcircuits. Package and microcircuit manufacturers implement the standard during incoming inspection of package components through final package inspection.

Metal and ceramic package manufacturers, hybrid/microcircuit/semiconductor manufacturers, and space/aerospace/military and commercial users provided user failure mode histories for the updated standard criteria. New criterion were added and old ones updated based on these data points. The revision aims to increase quality while trimming out unneccessary points. It includes clear and easy-to-interpret color photos or diagrams for every condition listed.

The JC-13.5 Task Group 134 updated the standard. The revised standard may be downloaded free of charge from JEDEC

June 20, 2011 – Marketwire — Technic Inc. debuted Pallaspeed Pd/Ni NFA, a production-proven sulfate palladium nickel process that produces low-stress ductile deposits over a wide current density range, for structures like semiconductor package leadframes.

The Pallaspeed Pd/Ni NFA process eliminates free ammonia, improving worker and environmental safety (environment, health and safety, EHS) by preventing harmful fumes. The process is also chloride free, which helps maintain stainless steel equipment without corrosion. The pH of Pallaspeed Pd/Ni NFA is more stable than conventional Pd/Ni processes, reducing the need for frequent ammonia additions.

The Pallaspeed Pd/Ni NFA process produces micro-crack-free deposits at thicknesses up to 2.5um with excellent adhesion, according to Technic. The deposits pass both the hydrochloric and sulfurous acid porosity tests commonly used in the electronics industry.

This process is available globally under either the "NFA" designation in North America or the Pallaspeed Pd/Ni LA designation in Asia and Europe.

Technic Inc. supplies specialty chemicals, custom finishing equipment, engineered powders, and analytical control systems to electronic component, PCB, semiconductor, photovoltaic, and other industries. For information, go to www.technic.com

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June 8, 2011 – PR Newswire — Tektronix Component Solutions purchased 5 Teradyne J750EX semiconductor test systems to screen a wider variety of complex ASICs, increase test capacity, and generate test programs faster.

Tektronix offers test and screening services for high-density and high-speed ASICs and FPGAs for military, commercial aerospace, and space customers. The company will also be able to use the Teradyne systems for memory testing complex digital ICs up to 384 pins. This could include full characterization of off-the-shelf parts at extended temperature ranges, which Tektronix expects to be of use to their "high-performance mil-aero" customers, said Tom Buzak, president, Tektronix Component Solutions, adding that the shorter new test development times should help reduce test costs.

Tektronix Component Solutions’ component screening service is used to test component quality and performance against the manufacturer’s specifications and/or customer’s application performance and reliability criteria. It includes:

• electrical (surge testing, parametric testing, functional testing, and device characterization);
• package integrity (highly accelerated stress testing [HAST], particle impact noise detection [PIND], salt fog, thermal shock and temp-cycle, and plastic encapsulated microcircuit [PEM] testing);
• assembly evaluation (destructive physical analysis [DPA], prohibited materials analysis [PMA], scanning electron microscopy [SEM]and X-Ray);
• and life-testing (Burn-in, operational life, dynamics, endurance and climatic test).

Tektronix Component Solutions is a microelectronics services provider offering a complete range of custom design, prototyping, manufacturing, and test services to equipment manufacturers. Tektronix Component Solutions can be found on the web at www.component-solutions.tektronix.com/.

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by Dr. Phil Garrou, contributing editor

June 8, 2011 – The major IEEE packaging award, the Field Award, was presented June 2^nd at the 2011 Electronic Component Technology Conference (ECTC) in Orlando, FL, to Professor Rao Tummala of Georgia Institute of Technology (GA Tech), industrial researcher and educator for his seminal contributions to microelectronics packaging.

The 2011 IEEE Field Award in Components, Packaging and Manufacturing Technologies recognizes Tummala’s "pioneering and innovative contributions to package integration research, cross-disciplinary education and globalization of electronic packaging."

Prior to joining GA Tech, he had a 25-year career at IBM pioneering technologies such as low-temperature, co-fired ceramics (LTCC) and polyimide-copper thin-film interconnections. His technology developments resulted in IBMs first 100-chip multichip module.

Tummala, currently director of Georgia Tech’s 3D Systems Packaging Research Center, has provided national leadership in making packaging an acceptable "academic subject " by developing courses, curricula, textbooks, and degrees. His 1989 "Microelectronics Packaging Handbook" introduced packaging to the academic community and his 1997 three volume update still serves as the "packaging bible" to practitioners. While at Georgia Tech he introduced and developed the concept of system-on-package (SOP).

Other IEEE ECTC award recipients include:

2011 IEEE CPMT Outstanding Sustained Technical Contribution Award:
John Lau, Industrial Technology Research Institute, Taiwan
For a decades-long record of developing and communicating packaging platform, material and process advancements through research and development leadership, publications and professional training.

2011 IEEE CPMT Exceptional Technical Achievement Award
Xuejun Fan, Lamar University, USA
For contributions in the area of modeling and characterization of moisture-related reliability in IC packaging, including model development, validation, numerical implementation, test methodology development and design.

2011 IEEE CPMT Electronics Manufacturing Technology Award
Mark Brillhart, Cisco, USA
For developing manufacturing technologies and industry supply chain capabilities in the areas of high-performance ASIC packaging, system in package, 3D and wafer-level packaging of high-speed memory and optics, and advanced coreless organic substrates for high-reliability networking products.