Category Archives: News

Plansee develops improved replacement parts from refractory metals, graphite, and ceramic for ion implanters from all major manufacturers. The latest development is a high performance extraction assembly for VIISta HCP, HCS, Trident, and NexGen configured systems.

Ideal Extraction for VIISta

Residual gas in the original extraction assembly from Varian reduces breakdown voltage across electrodes and results in high glitch rates for VIISta HCP, HCS, Trident, and NexGen configured systems. In turn, high glitching can destabilize ion beams potentially decreasing throughput and yield. Such instabilities also accelerate electrode wear resulting in more frequent maintenance and component replacement.

Costs resulting from the need to replace extraction assemblies and parts, including the associated downtimes, are considerable and prompted Plansee to produce a completely reworked extraction assembly.

Plansee’s Ideal Extraction has been shown to reduce glitching by more than an order of magnitude and, with routine cleaning, service life has averaged 3-4 times longer than that of the original assembly.

At the heart of the new design lies gas-permeable tungsten foil. The foil facilitates pumping between and behind the electrodes and thereby reduces residual gas pressure in the extraction assembly.  Consequently, the reduction in pressure increases breakdown voltage and yields a dramatically lower glitch rate.

However glitching is not the only issue: Time-consuming replacement of the original extraction assembly is both costly – in terms of downtime – and difficult. The original extraction assembly weighs approximately 8.2 kg and often takes the combined effort of two people to safely remove it from the tool. Plansee engineers have therefore replaced steel, molybdenum, tungsten, and aluminum mounting components with high-quality graphite, transforming the assembly into a 3-kg lightweight champion with increased thermal stability. As an added bonus, potentially damaging contamination by iron is a thing of the past.

To speed assembly and reduce the cost of replacement parts, electrodes in the Ideal Extraction have been designed to self-align, to allow installation in either slot position, and to be rotatable to offset potentially uneven wear. With this solution, the Plansee team has managed to substantially improve assembly and increase service life of the electrodes. No alignment tools required!

Mike Reilly is responsible for product development of components for the semiconductor industry at Plansee and sums up the advantages of Plansee’s Ideal Extraction: “Our advanced standard Ideal Extraction improves pumping in the electrode gaps and thereby limits discharges, reduces coating, and improves service life. Our engineers took a fresh look at the entire assembly and were able to reduce complexity while improving assembly and alignment – hallmarks of good design.  The final embodiments share components and concepts across the entire VIISta high current platform simplifying maintenance and supply chain challenges.”

The Ideal Extraction is available from Plansee as a complete, bolt-on, solution for VIISta HCP, VIISta HCS, Trident, and NexGen configured systems.

A new Department of Energy grant will fund research to advance an additive manufacturing technique for fabricating three-dimensional (3D) nanoscale structures from a variety of materials. Using high-speed, thermally-energized jets to deliver both precursor materials and inert gas, the research will focus on dramatically accelerating growth, improving the purity and increasing the aspect ratio of the 3D structures.

Known as focused electron beam induced deposition (FEBID), the technique delivers a tightly-focused beam of high energy electrons and an energetic jet of thermally excited precursor gases – both confined to the same spot on a substrate. Secondary electrons generated when the electron beam strikes the substrate cause decomposition of the precursor molecules, forming nanoscale 3D structures whose size, shape and location can be precisely controlled. This gas-jet assisted FEBID technique allows fabrication of high-purity nanoscale structures using a wide range of materials and combination of materials.

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By allowing the rapid atom-by-atom “direct writing” of materials with controlled shape and topology, the work could lead to a nanoscale version of the 3D printing processes now revolutionizing fabrication of structures at the macro scale. The technique could be used to produce nano-electromechanical sensors and actuators, to modify the morphology and composition of nanostructured optical and magnetic materials to yield unique properties, and to engineer high performance interconnect interfaces for graphene and carbon nanotube-based electronic devices.

“This unique nanofabrication approach opens up new opportunities for on-demand growth of structures with high aspect ratios made from high-purity materials,” said Andrei Fedorov, the project’s leader and a professor in the Woodruff School of Mechanical Engineering at the Georgia Institute of Technology. “By providing truly nanoscale control of geometries, it will impact a broad range of applications in nanoelectronics and biosensing.”

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Researchers have demonstrated the feasibility of the technique, and expect the three-year $660,000 grant to help them develop a fundamental understanding of how the process works, accelerate the rate of materials growth and provide improved control over the process. The research will include both theoretical modeling and experimental evaluation. Proof of principle for using thermally-energized gas jets as part of the FEBID technique was reported by Fedorov’s group in the journal Applied Physics Letters in 2011.

“Wherever electrons strike the surface, you can grow the deposit,” explained Fedorov. “That provides a tool for growing complex three-dimensional structures from a variety of materials with resolution at the tens of nanometers. Electron beam induced deposition is much like inkjet printing, except that it uses electrons and precursor molecules in a vacuum chamber.”

Two major challenges lie ahead for using the technique to manufacture 3D nanostructures: increasing the rate of deposition and eliminating the unwanted deposits of carbon that are formed as part of the process. To address these challenges, Fedorov and his team are using energetic jets of inert argon gas to clean substrate surfaces and carefully tune the energy of the desired molecules delivered in another jet to enhance the rate at which the precursor sticks to the substrate.

“If the energy of the jet is sufficiently high, the inert gas molecules striking the surface can knock away the adsorbed hydrocarbon contamination so that there is no parasitic carbon co-deposition,” he said. “We can also tune the properties of the precursor molecules so they stick more effectively to the surface. We have shown that we can increase the rate of growth by an order of magnitude or more while maintaining a high aspect ratio of deposited nanostructures.”

Overall, about two dozen materials have been successfully deposited using FEBID on different substrates, including semiconductors, dielectrics, metals and even plastics. The researchers also plan to create nanostructures containing more than one material, allowing them to create unique properties not available in each individual material. Examples might include new types of ferromagnetic materials and photonic bandgap structures with unique properties.

Fedorov’s group has used FEBID to fabricate low-resistance contacts to carbon nanotubes and graphene, a unique carbon-based material with attractive electronic properties.

Major technical challenges for the project include making tightly focused jets of thermally-energized precursor molecules to provide precise control of the fabrication. In operation, precursor molecules enter the reaction chamber from the micron-scale nozzle at sonic speeds, and accelerate in the vacuum environment to even greater speed, forming a molecular beam that impinges on the substrate. To make structures of the desired morphology, researchers will have to control the spreading of the generated molecular beam and its energy state at the point of contract with the substrate.

“We will be growing structures ranging in size from tens to hundreds of nanometers,” Fedorov noted. “This means we will not only have to confine electrons to very small regions, but we will also need to confine the precursor molecules to these same domains.”

The FEBID technique will likely not be used for high-volume fabrication because the process is difficult to scale up, Fedorov said. Accelerating the deposition rate will allow more rapid fabrication, but the 3D structures will still need to be produced one at a time. A partial solution to the scale-up challenge lies in the use of multiple electron beams and precursor jets operating in parallel.

The new technique will allow researchers to take better advantage of the unique properties of materials at the nanometer scale. Researchers will also have to account for those differences in developing the new manufacturing technique, as the interactions between electrons, precursor materials in the jet and substrate continually change with growth of the deposit.

“This research will open up the potential for some new discoveries in areas we may not be able to predict now,” said Fedorov. “We need to understand the basic physics of what is happening. That basic understanding could lead us to some truly unique applied capabilities, and the possibilities are almost limitless.”

Nanofluidic channels are useful for many biological and chemical applications, such as DNA sequencing, drug delivery, blood cell sorting and molecular sensing and detection. But in the effort to build a versatile lab-on-a-chip, it has been challenging to develop a wafer-scale nanochannel fabrication process compatible with CMOS technology.

At the upcoming International Electron Devices Meeting (IEDM), to be held December 9-11 in Washington, D.C., IBM researchers will report on a CMOS-compatible 200 mm wafer-scale sub-20nm nanochannel fabrication method that enables stretching, translocation and real-time fluorescence microscopy imaging of single DNA molecules.

Through the use of sacrificial XeF2 etching and various UV and e-beam lithography methods, sub-20-nm patterns in silicon were converted into macro-scale fluidic ports, micro-scale fluidic feed channels, and nano-scale channels for DNA imaging. Gradient nanopillars were located in the channels to stretch DNA molecules prior to imaging them. Fluid wasn’t pumped through the channels, but instead was transported by the force of gravity. The researchers say their techniques lead to highly manufacturable structures and can produce chips for a variety of biological applications.

A schematic of the nanochannel architecture. Grey represents silicon layers, while blue represents SiO2. The silicon layers serve as sacrificial material.

A schematic of the nanochannel architecture. Grey represents silicon layers, while blue represents SiO2. The silicon layers serve as sacrificial material.

The etching sequence of the silicon layers is shown: A) silicon-patterning with sub-20 nm features (note the inset SEM electron microscope photo); B) capping-oxide deposition followed by vent-hole patterning: and C) XeF2 gas-phase etching of silicon patterns embedded in SiO2.

The etching sequence of the silicon layers is shown: A) silicon-patterning with sub-20 nm features (note the inset SEM electron microscope photo); B) capping-oxide deposition followed by vent-hole patterning: and C) XeF2 gas-phase etching of silicon patterns embedded in SiO2.

SEM electron microscope photo of silicon nanochannels.

SEM electron microscope photo of silicon nanochannels.

Optical photos showing A,B) nanochannels with vent holes on 1-2 µm SiO2 capping layer, on top of silicon patterns; and C,D) following gas etching and removal of silicon patterns.

Optical photos showing A,B) nanochannels with vent holes on 1-2 µm SiO2 capping layer, on top of silicon patterns; and C,D) following gas etching and removal of silicon patterns.

Wang (14.1) Fig.12 (450x338)

 

Jordan Valley Semiconductors Ltd., a supplier of X-ray based metrology tools for advanced semiconductor manufacturing lines, received another order for its recently introduced JVX7300LMI scanning X-ray in-line metrology tool for patterned and blanket wafers.  The system has been purchased for advanced process development and production ramp-up for 14nm and 10nm nodes.

The tool provides fully automated advanced metrology for epitaxial materials such as SiGe, Si:C/P and III-V on silicon FinFET structures, as well as high-k and metal gate stacks and other critical layers.

Isaac Mazor, JV CEO, said: “We are pleased to have been selected by key customers to support their FEOL (Front-End-Of-Line) process metrology.  This selection represents the customers’ confidence in Jordan Valley’s ability to provide valuable metrology solutions for their most demanding advanced applications, trusting first principle X-ray based metrology to provide unique process control solutions.”

Mazor added, “Advanced logic devices set new metrology challenges and requirements for key transistor level structure such as FinFET, Ge and III/V materials on silicon, as well as high-k and metal gate stacks used to enhance the transistor performance. Jordan Valley was able to meet the customers’ stringent process requirements in a short period of development time.”

“In choosing the JVX7300LMI platform, the customers acknowledged the significant contribution of the product in shortening the process development cycle, coupled with enabling process performance and extendibility to future technology nodes.” Mazor concluded, “We believe that the JVX7300LMI can be a strong contributor to assure high yield in the current and next generation process nodes.”

The JVX7300LMI is an X-ray metrology system for 14nm and 10nm nodes R&D and production ramp for FEOL applications such as SiGe, Si:C/P, FinFETs, high-k/metal gate and replacement channel materials such as Ge and III-V layers on Si. It is also used for the development and production of the emerging GaN on Si market.

JVX7300LMI


This tool enables scanning HRXRD, XRR and (GI)XRD measurements. HRXRD is capable of measuring epitaxial layer composition, thickness, density, strain and relaxation of single and multi-layer stacks. Additionally, with XRR and (GI)XRD channels, the tool provides information on the thickness, density, phase and crystallinity of ultra-thin layers typically used in the FEOL process. Unlike optical or spectroscopic tools, the HRXRD and XRR are first principle techniques that deliver accurate and precise results without calibration.

InGaAs is a promising channel material for high-performance, ultra low-power n-MOSFETs because of its high electron mobility, but multiple-gate architectures are required to make the most of it, because multiple gates offer better control of electrostatics. In addition, it is difficult to integrate highly crystalline InGaAs with silicon, so having multiple gates offers the opportunity to take advantage of the optimum crystal facet of the material for integration.

Transistors with high mobility channels will likely be required for the 10nm and 7nm device generations, scheduled to go into production in 2016/2016 and 2017/2018, respectively. InGaAs is a good candidate for NFETS, while germanium is the candidate of choice for PFET devices.

At the upcoming International Electron Devices Meeting (IEDM), to be held December 8-11 in Washington, D.C., a research team led by Japan’s AIST will describe how they built triangular InGaAs-on-insulator n-MOSFETs with smooth side surfaces along the <111>B crystal facet and with bottom widths as narrow as 30nm, using a metalorganic vapor phase epitaxy (MOVPE) growth technique. The devices demonstrated a high on-current of 930 µA/µm at a 300nm gate length, showing they have great potential.

 

Triangular transistors produced with MOVPE demonstrate a high on-current of 930 µA/µm at a 30nm gate length.

Triangular transistors produced with MOVPE demonstrate a high on-current of 930 µA/µm at a 30nm gate length.

The National Institute of Advanced Industrial Science and Technology (AIST) is a public research institution largely funded by the Japanese government. About 2300 researchers (about 2050 with tenure: about 80 from abroad) and a few thousands of visiting scientists, post-doctoral fellows, and students from home and abroad are working at AIST.  About 650 permanent administrative personnel and many temporary staff support research works of AIST.

At the International Electron Devices Meeting (IEDM) in December, IBM researchers will describe a silicon nanowire (SiNW)-based MOSFET fabrication process that produced gate-all-around (GAA) SiNW devices at sizes compatible with the scaling needs of 10nm CMOS technology. They built a range of GAA SiNW MOSFETs, some of which featured a 30nm SiNW pitch with a gate pitch of 60 nm.

Devices with a 90nm gate pitch demonstrated the highest performance ever reported for a SiNW device at a gate pitch below 100 nm— peak/saturation current of 400/976 µA/µm, respectively, at 1 V. Although this work focused on NFETs, the researchers say the same fabrication techniques can be used to produce PFETs as well, opening the door to a potential ultra-dense, high-performance CMOS technology.

IBM F2

The integration scheme allows for a reduced, more uniform diffusion distance, affording a more abrupt junction.

The integration scheme allows for a reduced, more uniform diffusion distance, affording a more abrupt junction.

A new two-step anneal process shows that the nanowires can be smoothened with no loss of density compared to planar processes.

A new two-step anneal process shows that the nanowires can be smoothened with no loss of density compared to planar processes.

The TEM electron microscope images above show: a) a cross section of a completed device through a gate, illustrating the spacer, epitaxial source/drain and contacts; (b) the cross section of a silicon nanowire (SiNW) decorated with a high-Z film to better show the nanowire’s boundary. The effective SiNW diameter shown is 12.8 nm; (c) a close up of the region of interest indicated in a), showing that the source/drain is epitaxially regrown from the cut face of the nanowire. The lattice planes in the epi region are registered to that of the original SiNW channel (parallel red dashed lines).

The TEM electron microscope images above show: a) a cross section of a completed device through a gate, illustrating the spacer, epitaxial source/drain and contacts; (b) the cross section of a silicon nanowire (SiNW) decorated with a high-Z film to better show the nanowire’s boundary. The effective SiNW diameter shown is 12.8 nm; (c) a close up of the region of interest indicated in a), showing that the source/drain is epitaxially regrown from the cut face of the nanowire. The lattice planes in the epi region are registered to that of the original SiNW channel (parallel red dashed lines).

 

 

 

Semiconductor revenue worldwide will see improved growth this year of 6.9 percent and reaching $320 billion according to the mid-year 2013 update of the Semiconductor Applications Forecaster (SAF) from International Data Corporation (IDC). The SAF also forecasts that semiconductor revenues will grow 2.9 percent year over year in 2014 to $329 billion and log a compound annual growth rate (CAGR) of 4.2 percent from 2012-2017, reaching $366 billion in 2017.

Continued global macroeconomic uncertainty from a slowdown in China, Eurozone debt crisis and recession, Japan recession, and the U.S. sequester’s impact on corporate IT spending are factors that could affect global semiconductor demand this year. Mobile phones and tablets will drive a significant portion of the growth in the semiconductor market this year. The industry continued to see weakness in PC demand, but strong memory growth and higher average selling prices (ASPs) in DRAM and NAND will have a positive impact on the semiconductor market. For the first half of 2013, IDC believes semiconductor inventories decreased and have come into balance with demand, with growth to resume in the second half of the year.

“Semiconductors for smartphones will see healthy revenue growth as demand for increased speeds and additional features continue to drive high-end smartphone demand in developed countries and low-cost smartphones in developing countries. Lower cost smartphones in developing countries will make up an increasing portion of the mix and moderate future mobile wireless communication semiconductor growth. PC semiconductor demand will remain weak for 2013 as the market continues to be affected by the worldwide macroeconomic environment and the encroachment of tablets,” said Nina Turner, Research Manager for semiconductors at IDC.

According to Abhi Dugar, research manager for semiconductors, embedded system solutions, and associated software in the cloud, mobile, and security infrastructure markets, “Communications infrastructure across enterprise, data centers, and service provider networks will experience a significant upgrade over the next five years to support the enormous growth in the amount of data and information that must be managed more efficiently, intelligently, and securely. This growth is being driven by continued adoption of rich media capable mobile devices, movement of increasingly virtualized server workloads within and between datacenters, and the emergence of new networking paradigms such as software defined networking (SDN) to support the new requirements.”

Regionally, Japan will be the weakest region for 2013, but IDC forecasts an improvement over the contraction in 2012. Growth rates in all regions will improve for 2013 over 2012, as demand for smartphones and tablets remain strong and automotive electronics and semiconductors for the industrial market segment improve in 2013. •

Crossbar, Inc., a start-up company, unveiled a new Resistive RAM (RRAM) technology that will be capable of storing up to one terabyte (TB) of data on a single 200mm2 chip. A working memory was produced array at a commercial fab, and Crossbar is entering the first phase of productization. “We have achieved all the major technical milestones that prove our RRAM technology is easy to manufacture and ready for commercialization,” said George Minassian, chief executive officer, Crossbar, Inc. The company is backed by Artiman Ventures, Kleiner Perkins Caufield & Byers and Northern Light Venture Capital.

The technology, which was conceived by Professor Wei Lu of the University of Michigan, is based on a simple three-layer structure of silver, amorphous silicon and silicon (FIGURE 1). The resistance switching mechanism is based on the formation of a filament in the switching material when a voltage is applied between the two electrodes. Minassian said the RRAM is very stable, capable of withstanding temperature swings up to 125°C, with up to 10,000 cycles, and a retention of 10 years. “The filaments are rock solid,” he said.

Crossbar has filed 100 unique patents, with 30 already issued, relating to the development, commercialization and manufacturing of RRAM technology.

After completing the technology transfer to Crossbar’s R&D fab and technology analysis and optimization, Crossbar has now successfully developed its demonstration product in a commercial fab. This working silicon is a fully integrated monolithic CMOS controller and memory array chip. The company is currently completing the characterization and optimization of this device and plans to bring its first product to market in the embedded SOC market.

Sherry Garber, Founding Partner, Convergent Semiconductors, said: “RRAM is widely considered the obvious leader in the battle for a next generation memory and Crossbar is the company most advanced to show working demo that proves the manufacturability of RRAM. This is a significant development in the industry, as it provides a clear path to commercialization of a new storage technology, capable of changing the future landscape of electronics innovation.”

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FIGURE 1. The resistance switching mechanism of Crossbar’s technology is based on the formation of a
filament in the silicon-based switching material when a voltage is applied between the two electrodes.

Crossbar technology can be stacked in 3D, delivering multiple terabytes of storage on a single chip. Its simplicity, stackability and CMOS compatibility enables logic and memory to be integrated onto a single chip at the latest technology node (FIGURE 2).

Crossbar’s technology will deliver 20x faster write performance; 20x lower power consumption; and 10x the endurance at half the die size, compared to today’s best-in-class NAND Flash memory. Minassian said the biggest advantage of the technology is its simplicity. “That allowed us in three years time to get from technology understanding, characterization, cell array and put a device together,” he said.

Minassian said RRAM compares favorably with NAND, which is getting more complex and expensive. “In 3D NAND, you put all of these thing layers of top of each other – 32 layers, or 64 or 128 in some cases – then you have to etch them, you have to slice them all at once and the equipment required for that accuracy and that geometry is very expensive. This is one of the reasons that 3D has been very difficult for NAND to be introduced.” With the Crossbar approach, “you’re always dealing with three layers. It’s much easier to stack these and it gives you a huge density advantage,” Minassian said.

“The switching media is highly resistive,” explains Minassian. “If you try to read the resistance between top and bottom electrode without doing anything, it’s a high resistance. That’s the off state. To turn on the device, we apply a positive voltage to the top electrode. That ionizes the metal on the top layer and puts the metal ions into the switching media. The metal ions form a filament that connect the top and bottom electrode. The moment they hit the bottom electrode, you have a short, which means that the top and bottom electrode are connected which means they have a low resistance.” The low resistance state is the on state. He said that although silver is not commonly used in front-end CMOS processing, the RRAM memory formation process is a back-end process. “You produce all your CMOS and then right before the device exits the fab, you put the silver on top,” he said. The silver is deposited, encapsulated, etched and then packaged. “That equipment is available, you just have to isolate it at the end,” Minassian said.

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FIGURE 2. Crossbar’s simple and scalable memory cell structure enables a new class of 3D RRAM which can be incorporated into the back end of line of any standard CMOS manufacturing fab.

The approach is also CMOS compatible, with processes used to fabricate the memory layers all running at less than 400°C. “This allows you to not only be CMOS compatible, but it allows you to stack more and more of these memory layers on top of each other,” Minassian said. “You can put the logic, the controllers and microprocessors, next to the memory in the same die. That allows you to simplify packaging and increase performance.”

Another advantage compared to NAND is that the controllers used to address the cells can be less complicated. Minassian said that in conventional cells, 30 electrons are required to produce 1 Volt. “If you shrink that to a smaller node, the number of electrons is less. Fewer electrons are much harder to detect. You need a massive controller that does error recovery and complex coding so if the bits are changed, it can still provide you the right program to execute.” Also, because the Crossbar RRAM is capable of 10,000 write cycles, less complicated controllers are needed. Today’s NAND is capable of only 1000 write cycles. “If you write information 1000 times, that cell is destroyed. It will not contain or maintain the information. You have this complex controller that keeps track of how many cells have been written, how many times, to make sure all of them are aged equally,” Minassian said.

Non-volatile memory, expected to grow to become a $60 billion market in 2013, is the most common storage technology used for both code storage (NOR) and data storage (NAND) in a wide range of electronics applications. Crossbar plans to bring to market standalone chip solutions, optimized for both code and data storage, used in place of traditional NOR and NAND Flash memory. Crossbar also plans to license its technology to SOC developers for integration into next-generation systems-on-chips (SOC).

Michael Yang, Senior Principal Analyst, Memory and Storage, IHS, said: “Ninety percent of the data we store today was created in the past two years. The creation and instant access of data has become an integral part of the modern experience, continuing to drive dramatic growth for storage for the foreseeable future. However, the current storage medium, planar NAND, is seeing challenges as it reaches the lower lithographies, pushing against physical and engineering limits. The next generation non-volatile memory, such as Crossbar’s RRAM, would bypass those limits, and provide the performance and capacity necessary to become the replacement memory solution.” •

P. Singer

Edwards, a supplier of vacuum products, abatement systems and related value-added services, and Sweden-based Atlas Copco entered into a definitive merger agreement in a transaction valued at up to approximately $1.6 billion, including the assumption of debt.

Under the terms of the merger agreement, a subsidiary of Atlas Copco will acquire Edwards for a per-share consideration of up to $10.50, which includes a fixed cash payment of $9.25 at closing and an additional payment of up to $1.25 per share post-closing, depending on Edwards’ achievement of 2013 revenue within the range of £587.5 million to £650 million and achievement of a related Adjusted EBITDA1 target within the range of £113.9 million to £145 million. The transaction is expected to close in the first quarter of 2014.

Depending on the amount of any additional payment, the merger consideration represents a premium of approximately 11 percent to 26 percent to Edwards’ 30-day average closing share price of $8.33 up to August 16, 2013, the last trading day prior to this announcement. Edwards priced its initial public offering on The NASDAQ Global Select Market on May 10th 2012 at $8.00 per share.

Edwards’ shareholders representing approximately 84% of the current shares outstanding have entered into voting agreements with Atlas Copco to vote in favor of the merger, subject to the conditions set out in the voting agreements. Further, the Board of Directors of Edwards unanimously recommends the offer to all Edwards shareholders.

Edwards and Atlas Copco have a complementary businesses fit. Both companies share a similar strategic direction, with growth focused on technology leadership and customer service. The benefits of greater scale will help accelerate Edwards’ growth strategy and provide more opportunities for Edwards’ employees. Upon completion of the transaction, a new Vacuum Solutions Division will be formed within the Atlas Copco Compressor Technique business area, with headquarters in Crawley, UK.

news_quaterly

The Semiconductor Industry Association (SIA) announced that worldwide sales of semiconductors reached $74.65 billion during the second quarter of 2013, an increase of 6 percent from the first quarter when sales were $70.45 billion. This marks the largest quarterly increase in three years. Global sales for June 2013 hit $24.88 billion, an increase of 2.1 percent compared to June 2012 and 0.8 percent higher than the May 2013 total. Regionally, sales in the Americas jumped 8.6 percent in Q2 compared to Q1 and 10.6 percent in June 2013 compared to June 2012, marking the region’s largest year-over-year increase of 2013. All monthly sales numbers are compiled by the World Semiconductor Trade Statistics (WSTS) organization and represent a three-month moving average.

“There’s no question the global semiconductor industry has picked up steam through the first half of 2013, led largely by the Americas,” said Brian Toohey, president and CEO, Semiconductor Industry Association. “We have now seen consistent growth on a monthly, quarterly, and year-to-year basis, and sales totals have exceeded the latest industry projection, with sales of memory products showing particular strength.”

Quarterly sales outperformed the World Semiconductor Trade Statistics (WSTS) organization’s latest industry forecast, which projected quarter-over-quarter growth of 4.6 percent globally and 3.4 percent for the Americas (compared to the actual increases of 6 percent and 8.6 percent, respectively). Total year-to-dates sales of $145.1 billion also exceeded the WSTS projection of $144.1 billion. Actual year-to-date sales through June are 1.5 percent higher than they were at the same point in 2012.

Regionally, sales in June increased compared to May in the Americas (3.5 percent), Asia Pacific (0.4 percent), and Europe (0.1 percent), but declined slightly in Japan (-0.9 percent). Compared to the same month in 2012, sales in June increased substantially in the Americas (10.6 percent), moderately in Asia Pacific (5.4 percent), and slightly in Europe (0.8 percent), but dropped steeply in Japan (-20.8 percent), largely due to the devaluation of the Japanese yen.

“While we welcome this encouraging data, it is important to recognize the semiconductor workforce that drives innovation and growth in our industry,” continued Toohey. “A key roadblock inhibiting our innovation potential is America’s outdated high-skilled immigration system, which limits semiconductor companies’ access to the world’s top talent. The House of Representatives should use the August recess to work out their political differences on this issue and return to Washington next month ready to approve meaningful immigration reform legislation.” •