Category Archives: Editors Picks

Plessey today announced that samples of its Gallium Nitride (GaN) on silicon LED products are today available. These entry level products are the first LEDs manufactured on 6-inch GaN on silicon substrates to be commercially available anywhere in the world. Plessey is using its proprietary large diameter GaN on silicon process technology to manufacture the LEDs onits 6-inch MAGIC (Manufactured on GaN I/C) line at its Plymouth, England facility. The use of Plessey’s MAGIC GaN line using standard semiconductor manufacturing processing provides yield entitlements of greater than 95% and fast processing times providing a significant cost advantage over sapphire and silicon carbide based solutions for LEDs of similar quality.

The release of the availability of Plessey’s GaN on silicon LEDs was coincident with a visit to the Plessey Plymouth facility by the Rt. Hon. Dr. Vince Cable, MP, Secretary of State for Business Innovation and Skills and President of the Board of Trade. Business Secretary Vince Cable commented, “The government is supporting innovative companies like Plessey who are growing, creating jobs and exporting their products all over the world. That’s why we selected Plessey’s £3.25 million Regional Growth Fund bid for Government support, which will create 100 new, high tech and highly skilled jobs in the region.”

Michael LeGoff, CEO Plessey said, “We are very pleased to welcome Secretary of State Vince Cable today. The department of Business Innovation and Skills has been very supportive of our efforts to date and with the launch of our first range of LEDs today we are now looking towards aggressive growth in the solid state lighting markets.”

“Today is a significant step for us,” said Barry Dennington, Plessey’s COO. “From acquiring our first MOCVD reactor in August 2012 to having our first product in April 2013 is excellent progress. These entry level products will be used in indicating and accent lighting applications. We will continue to make progress in output efficiency and are on plan to release further improvements in light output throughout this year and into next. The operating and unit costs are on plan and we are seeing a number of routes to enhance our cost advantage over competing technologies.”

LEDs and the associated solid state lighting solutions are due to become the dominant form of lighting in all forms in within the next five years. Solid state lighting is an energy efficient eco-friendly technology that will save billions of tons of carbon emissions when fully implemented. There are also no recycling issues that fluorescent lighting poses with mercury content.

It’s no secret that Samsung is up against Apple in many ways, in products, sales and innovation. However, even in the face of Apple’s patent infringement lawsuits, Samsung is still climbing the charts. The electronics giant sold approximately $53 billion in revenue in the last quarter of 2012, in comparison to Apple’s $36 billion in revenue, though the profit margins both companies are seeing were relatively similar. And while Bloomberg is predicting Apple will post its lowest sales increase since 2009, Samsung is reportedly poised for big growth in a number of sectors.  

Samsung grabs No. 3 foundry spot

Samsung jumped into the foundry scene in mid-2010, and quickly became one of the anticipated long-term leaders in the sector. It’s now easily the biggest IDM foundry operation, with sales nearly 10 times that of IBM, IC Insights noted in January. IC Insights’ August update projected Samsung finishing in fourth place just behind UMC, separated by about $400 million, but anticipated Samsung surpassing the Taiwan rival in 2013.

Samsung followed a sparkling 82 percent growth in 2011 by nearly doubling sales again to $4.33 billion, putting it just shy of GLOBALFOUNDRIES which grew sales a solid 31 percent last year to $4.56B. In fact IC Insights believes Samsung will challenge GLOBALFOUNDRIES for the No.2 spot before 2013 is done, leveraging its leading-edge capacity and huge capital spending budget. With dedicated IC foundry capacity reaching 150,000 300mm wafers/month by 4Q12, and an average revenue/wafer of $3000, Samsung’s IC foundry capacity could pull down $5.4B in annual sales, the analyst firm calculates.

How did Samsung get so big so fast in the foundry business? It supplied chips to nearly half of the industry’s 750 million smartphones shipped in 2012 — application processors for the 220 million of its own handsets in 2012, plus the 133 million iPhones Apple shipped.

Thanks to the Galaxy S4, Samsung has 99% of the AMOLED market

Samsung has invested a considerable amount into the AMOLED market, which is now poised for steady growth, thanks to a growing demand for high-end smartphones and tablets. According to Forbes contributor Haydn Shaughnessy, Samsung now holds 99% of the AMOLED market.

AMOLED display shipments for mobile handset applications are expected to grow to 447.7 million units in 2017, up from 195.1 million units in 2013, according to insights from the IHS iSuppli Emerging Displays Service at information and analytics provider IHS. Within the mobile handset display market, the market share for AMOLED displays is forecast to grow from 7.9% in 2013 to 15.2 percent in 2017, as presented in the figure below. AMOLED’s market share for 4-inch or larger handset displays employed in smartphones is set to increase to 24.4% in 2017, up from 23.0% in 2013.

“Because of their use in marquee products like the Galaxy S4, high-quality AMOLEDs are growing in popularity and gaining share at the expense of liquid crystal display (LCD) screens,” said Vinita Jakhanwal, director for mobile & emerging displays and technology at IHS. “These attractive AMOLEDs are part of a growing trend of large-sized, high-resolution displays used in mobile devices. With the S4 representing the first time that a full high-definition (HD) AMOLED has been used in mobile handsets, Samsung continues to raise the profile of this display technology.”

Samsung anticipates MEMS pressure sensor market boom

Samsung has been ahead of its time in its adoption of MEMS pressure sensors, anticipating the state of the market and getting a jump on the competition.

Global shipments of MEMS pressure sensors in cellphones are set to rise to 681 million units in 2016, up more than eightfold from 82 million in 2012, according to the IHS iSuppli MEMS & Sensors Service at information and analytics provider IHS. Shipments this year are expected to double to 162 million units, as presented in the attached figure, primarily due to Samsung’s usage of pressure sensors in the Galaxy S4 and other smartphone models.

“Samsung is the only major original equipment manufacturer (OEM) now using pressure sensors in all its flagship smartphone models,” said Jérémie Bouchaud, director and senior principal analyst for MEMS and sensors at IHS. “The pressure device represents just one component among a wealth of different sensors used in the S4.”

Besides Samsung, few other OEMs have been using pressure sensors in smartphones. The only other smartphone OEMs to use pressure sensors in their products are Sony Mobile in a couple of models in 2012, and a few Chinese vendors, like Xiaomi.

Apple, which pioneered the use of MEMS sensors in smartphones, does not employ pressure sensors at the moment in the iPhone. However, IHS expects Apple will start them in 2014, which will contribute to another doubling of the market in 2014 to 325 million units.

But what about the patent infringement suit?

Six months after Samsung was ordered to pay an unprecedented $1.05 billion to Apple in the notorious patent infringement suit, Judge Lucy Koh, the federal judge presiding over two Apple v. Samsung cases in California, entered an order striking $450 million from the damages award determined by a jury in August 2012. This corresponds to 14 of the 28 Samsung products in question in the initial lawsuit. Koh disagreed with the notice date provided by Apple concerning its patents-in-suit, and, as a result, a new damages trial must be held, most likely after the appellate proceedings, which were sought by both parties.

The new trial could mean good news or bad news for Samsung. There is the possibility that the court could rule in favor of a reduction of damages to be paid. However, it is also just as likely that the court could rule Samsung owe Apple even more than the original $1.05 billion ordered in August.

Some analysts have speculated that, if the suit holds, consumers could see a jump in prices of Samsung, Google and Android devices. Only time will tell if will a price that the masses will be willing to pay. If it is, don’t expect to see Samsung slowing down any time soon.

GLOBALFOUNDRIES today announced the accomplishment of a key milestone in its strategy to enable 3D stacking of chips for next-generation mobile and consumer applications. At its Fab 8 campus in Saratoga County, N.Y., the company has demonstrated its first functional 20nm silicon wafers with integrated Through-Silicon Vias (TSVs). Manufactured using GLOBALFOUNDRIES’ leading-edge 20nm-LPM process technology, the TSV capabilities will allow customers to stack multiple chips on top of each other, providing another avenue for delivering the demanding performance, power, and bandwidth requirements of today’s electronic devices.

TSVs are vertical vias etched in a silicon wafer that are filled with a conducting material, enabling communication between vertically stacked integrated circuits. The adoption of three-dimensional (3D) chip stacking is increasingly being viewed as an alternative to traditional technology node scaling at the transistor level. However, TSVs present a number of new challenges to semiconductor manufacturers.

GLOBALFOUNDRIES utilizes a “via-middle” approach to TSV integration, inserting the TSVs into the silicon after the wafers have completed the Front End of the Line (FEOL) flow and prior to starting the Back End of the Line (BEOL) process. This approach avoids the high temperatures of the FEOL manufacturing process, allowing the use of copper as the TSV fill material. To overcome the challenges associated with the migration of TSV technology from 28nm to 20nm, GLOBALFOUNDRIES engineers have developed a proprietary contact protection scheme. This scheme enabled the company to integrate the TSVs with minimal disruption to the 20nm-LPM platform technology, demonstrating SRAM functionality with critical device characteristics in line with those of standard 20nm-LPM silicon.

“Our industry has been talking about the promise of 3D chip stacking for years, but this development is another sign that the promise will soon be a reality,” said David McCann, vice president of packaging R&D at GLOBALFOUNDRIES. “Our next step is to leverage Fab 8’s advanced TSV capabilities in conjunction with our OSAT partners to assemble and qualify 3D test vehicles for our open supply chain model, providing customers with the flexibility to choose their preferred back-end supply chain.”

As the fabless-foundry business model evolves to address the realities of today’s dynamic market, foundries are taking on increasing responsibility for managing the supply chain to deliver end-to-end solutions that meet the requirements of the broad range of leading-edge designs. To help address these challenges, GLOBALFOUNDRIES is engaging early with partners to jointly develop solutions that will enable the next wave of innovation in the industry. This open and collaborative approach will give customers maximum choice and flexibility, while delivering cost savings, faster time-to-volume, and a reduction in the technical risk associated with developing new technologies.

Gandharv Bhatara is the product marketing manager for OPC technologies at Mentor Graphics.

The long-expected demise of optical lithography for manufacturing ICs has been delayed again, even though the technology itself has reached a plateau with a numerical aperture of 1.35 and an exposure wavelength of 193nm. Immersion lithography is planned for the 20/22nm node, and with the continued delay of EUV, is now the plan of record for 14nm.

How is it possible to use 193nm wavelength light at 14nm? How can we provide the process window to pattern such tight pitches? The secret lies in computational lithography. For 20nm, the two key innovations in computational lithography involve enabling double patterning with concurrent OPC, and in improving difficult-to-print layouts with localized in-situ optimization and by using an inverse lithography technique.

For 14nm, computational lithography offers more tools for process window enhancement with better approaches to sub-resolution assist features (SRAFs). SRAFs have been used since the 130nm node for resolution enhancement, but for 14nm, SRAF placement has evolved considerably. SRAFs placement has traditionally been based on a set of defined rules, which has given excellent coverage for line-space layouts and moderately good coverage for complex 2D layouts, along with fast runtime. However, the final SRAF coverage is highly dependent on the OPC recipe that the user is able to tune. Setting up these highly tuned recipes for 2D layouts can be time consuming, and also inadequate on very complex 2D layouts, leading to catastrophic failures in certain locations. The complexity of developing a well-tuned SRAF rules recipe since the introduction of pixelated sources and the introduction of more sophisticated contact and via layouts has driven lithographers away from rules-based solutions and towards model-based approaches.

Two distinct model-based approaches have developed: inverse lithography (ILT)-assisted and model-based. In the ILT-assisted approach, you use inverse lithography analysis to create a golden reference for a rules-based SRAF placement. ILT provides the ultimate lithography entitlement, but may not be practical to deploy in manufacturing because of increased mask cost and runtime. So, you use ILT only to find the best rules, and then let a rules-based SRAF tool do the actual placement. This gives superior process window for critical blocks like SRAM where the rules are relatively easy to develop.

The second approach is a true model-based approach, where a model is used to determine which areas on mask would benefit most from SRAFS and also to perform the initial SRAF placement. The model-based SRAF optimization reduces dependence on rules generation and improves SRAF placement. Model-based SRAFs can provide a process window that is comparable to that provided by ILT tools, but with much lower mask cost and runtime. The model-based approach is particularly useful for random logic designs, where developing rules continues to be challenging. Figure 1 shows a wafer validation done by IMEC, which shows that the process window obtained using model-based SRAFs and dense OPC was the same as obtained by using an ILT tool.

Given that both the ILT-assisted, rule-based approach and the model-based methods are good, but for different design styles, what if you could combine them easily into a hybrid approach? A hybrid approach combining the best of both solutions provides a single, unified SRAF recipe for SRAM (rules-based) and random logic designs (model-based). This is one of the secrets to 14nm computational lithography: advanced SRAF solutions that provide flexibility, control runtime, and leverage both rules-based and model-based approaches for the most challenging layouts.

Process window with model based SRAFs and ILT
Figure 1. Similar process window with model based SRAFs and ILT

 

SRAF placement flow high lithography
Figure 2.  A novel hybrid SRAF placement flow guarantees high lithography entitlement and resolves the SRAF development challenge.

With the introduction of the Galaxy S4, Samsung Electronics continues to lead the market in the adoption of pressure sensors in smartphones, paving the way for massive growth in the market for these devices in the coming years.

Global shipments of microelectromechanical system (MEMS) pressure sensors in cellphones are set to rise to 681 million units in 2016, up more than eightfold from 82 million in 2012, according to the IHS iSuppli MEMS & Sensors Service at information and analytics provider IHS (NYSE: IHS). Shipments this year are expected to double to 162 million units, as presented in the attached figure, primarily due to Samsung’s usage of pressure sensors in the Galaxy S4 and other smartphone models.

“Samsung is the only major original equipment manufacturer (OEM) now using pressure sensors in all its flagship smartphone models,” said Jérémie Bouchaud, director and senior principal analyst for MEMS and sensors at IHS. “The company appears to be slightly ahead of its time in its adoption of pressure sensors, even though the most compelling application—indoor navigation—is still not ready for deployment. However, Samsung seems to want to anticipate the start of this market and get a jump on the competition for pressure sensors. The pressure device represents just one component among a wealth of different sensors used in the S4.”

Pressure’s rising

Besides Samsung, few other OEMs have been using pressure sensors in smartphones. The only other smartphone OEMs to use pressure sensors in their products are Sony Mobile in a couple of models in 2012, and a few Chinese vendors, like Xiaomi.

Apple Inc., which pioneered the use of MEMS sensors in smartphones, does not employ pressure sensors at the moment in the iPhone. However, IHS expects Apple will start them in 2014, which will contribute to another doubling of the market in 2014 to 325 million units.

Applying pressure

Although pressure sensors aren’t very useful currently in smartphones, they hold strong potential for the future.

The most interesting application now is the fast Global Positioning System (GPS) lock, wherein the GPS chipset can lock on to a satellite signal and calculate positions more quickly by using the pressure sensor to determine the smartphone’s altitude.

However, the most exciting use for pressure sensors in the future will be indoor navigation, an area with massive potential growth in retail and travel applications. Pressure sensors will provide the floor accuracy required to determine which level a user is on within a structure.

While the ecosystem is not yet fully in place for indoor location/navigation, IHS anticipates this market will reach a breakthrough in growth during the next 12 to 18 months.

By this time, Samsung will have a considerable lead over Apple and other competitors in the installed base of pressure sensors in smartphones.

Samsung takes lead in smartphone MEMS sensors

Although Apple pioneered the usage of MEMS sensors in smartphones, and was the top consumer of these devices for many years, Samsung in 2012 took the lead from Apple for the first time. With Samsung expected to maintain hegemony in smartphone shipments in 2013 and the company loading up on the number of MEMS and other sensors in each smartphone that it ships, its lead in this area is is likely to continue to grow.

Given its emphasis on detecting and adapting to consumer lifestyles, the Galaxy S4 integrates a wealth of different sensors, including the accelerometer, RGB light, geomagnetic, proximity, gyroscope, barometer, gesture and even temperature and humidity varieties.

Sensor suppliers

While IHS has not yet conducted a physical teardown of the Galaxy S4, the IHS iSuppli MEMS and Sensors Service is able to anticipate the likely suppliers of these devices for the smartphone.

The pressure sensor in the S4 is made either by STMicroelectronics, as it was in the Galaxy S III; or by Bosch, like what was used in the Galaxy Note 1 and 2. Both companies are the only mass producers of these devices today for handsets.

And just as in the Samsung Galaxy S III, STMicroelectronics and yet another supplier, InvenSense, are expected to share the supply of the S4’s inertial measurement unit (IMU), which combines the accelerometer and gyroscope.

Meanwhile, the S4’s compass could be supplied by any one of three entities: by AKM—the same as the Galaxy S III; or by Yamaha—as was used in a previous member of the Galaxy smartphone line; or by Alps—which is an up-and-coming manufacturer in this area.

Maximum RGB

IHS expects that Samsung will continue to use an RGB sensor in the S4, as part of a combo device that aggregates RGB, proximity, and IR LED emitter, as it did in the Galaxy Note 2 and the Samsung S III. Samsung was the only user of such combo sensors in smartphones in 2012.

If the RGB sensor is installed on the side of the S4 display, it will be used to sense the color temperature of the room where it’s located, and adapt the contrast and colors on the display to enhance the viewing experience. Such RGB sensors are useful for high-end displays. Since the Galaxy S4 is expected to have full high-definition display—unlike the S3—the added value of having an RGB sensor might be more obvious and noticeable in the S4.

The RGB sensor also could be installed on the back the Galaxy S4 in conjunction with the camera module. This can help in taking better pictures by correcting the white balance.

Capella Microsystems is likely to be the RGB supplier, just as in the Galaxy S III. Other potential suppliers are ams-TAOS, Maxim and Hamamatsu.

Intel semiconductor market inventory declineAfter reaching a worrisome high in the third quarter of 2012, global semiconductor inventories held by chip suppliers fell at a surprisingly fast rate in the fourth quarter, led by dramatic reductions for market leader Intel Corp.

Days of Inventory (DOI) for semiconductor suppliers in the fourth quarter declined by 5 percent compared to the third quarter—higher than the 1.5% initially forecast, according to an IHS iSuppli Supply Chain Inventory Market Brief from information and analytics provider IHS. Meanwhile, inventory value in dollar terms fell almost 5%—larger than the originally projected 3%.

“Semiconductor companies reduced their inventories at a faster-than-expected rate in the fourth quarter as they moved to adjust to weakening demand,” said Sharon Stiefel, analyst for semiconductor market intelligence at IHS. “Many chip suppliers demonstrated great agility in their reactions to the drop in demand. No. 1 semiconductor supplier Intel Corp. was the most aggressive, cutting its stockpiles by more than half a billion dollars—the largest decrease on a dollar basis of any chipmaker.”

Cutting inventories down to size

Among semiconductor suppliers that reduced their inventory levels between the third and fourth quarters last year, the percentage of decrease ranged from 5% to 25%, resulting in chip stockpile value of $60 million to nearly $600 million being shaved off in the companies affected, as shown in the attached table. And while inventory climbed in some companies during the same period, the spread was smaller, with the value of the increase worth slightly north of $40 million to approximately $250 million.

In the table and numbers cited in this release, memory suppliers are excluded from DOI and inventory value calculations because they report results much later than any other group in the semiconductor supply chain.

The rest of the companies covered effectively straddle the breadth of the semiconductor chain, including those engaged in the wireless, automotive, data processing and industrial segments.

Intel leads inventory liquidation

The largest decrease in inventory value during the fourth quarter belonged to Intel, down $585 million from the third quarter, representing an 11% reduction. The company made aggressive moves to cut stockpiles. It also reduced production as it migrated to a new process technology: 14-nanometer lithography.

AMD and STMicroelectronics also experienced large inventory declines of $182 million and $131 million, respectively, or 25% and 9%. In the case of AMD, inventory shrank for its microprocessors as a result of an amended wafer supply agreement with GlobalFoundries for reduced stockpiles. For its part, STMicroelectronics cut utilization rates after exiting its money-losing joint venture with Ericsson.

Two other chip suppliers had notable inventory drawdowns: Texas Instruments, down $91 million or 5%, due to weak end-market demand for its chips; and ON Semiconductor, down $63 million or 10%, as it burned bridge inventory and coped with reduced revenue.

Among inventory gainers, most faulted low seasonality and an uncertain global economy for a rise in chip stockpiles. Companies in this group included MediaTek, up $58 million or 14%; NXP Semiconductors, up $44 million or 7%; and Infineon Technologies, up $43 million or 6%.

Qualcomm bucks the trend

The one exception among gainers that could boast of a strong performance that was linked to an increase in chip inventory levels was Qualcomm, up $247 million or 24%. Given the strong market acceptance of its wireless chips in products like the Apple iPhone and iPad, Qualcomm is ramping up production and inventories in order to meet demand.

Semiconductor suppliers will be positioning their inventories in the first quarter this year to prepare for anticipated demand. Inventories are expected to rise in response to slightly positive global economic indicators as well as favorable semiconductor and end-equipment forecasts—unless major swings occur once more from the larger suppliers that could then end up skewing the industry.

Yole Développement announced today its new report “UV LEDs: Technology & Application Trends” which presents UV LED new applications and associated market metrics for the period 2012-2020, and a deep analysis of UV LED technology and UV LED lighting industry.

Thanks to UV curing, UV LEDs should become a $270M business by 2017, and could hit $300M if new applications boom

Thanks to its compactness, low cost of ownership and environmentally-friendly composition, UV LED continues to replace incumbent technologies like mercury. Hence, the UV LED business is expected to grow from $45M in 2012 to nearly $270M by 2017, at a CAGR of 43% — whereas the traditional UV lamps market will grow at a CAGR of 10% during the same time period.

In 2012, UVA/UVB applications represented 89% of the overall UV LED market. Amongst these applications, UV curing is the most dynamic and most important market, due to significant advantages offered over traditional technologies (lower cost of ownership, system miniaturization, etc.). This trend is reinforced by the whole supply chain, which is pushing for the technology’s adoption: from UV LED module and system manufacturers to ink formulators and (of course) the associations created to promote the technology. And with Heraeus Noblelight’s recent acquisition of Fusion UV (Jan. 2013), all major UV curing system manufacturers are now involved in the UV LED technology transition.

Concerning UVC applications, they are still in their infancy and their sales are mainly for R&D purposes and analytic instruments like spectrophotometers. But given some newly published results (increase of EQE over 10%, etc.) and the recent commercialization of the world’s first UVC LED-based disinfection system (2012), the market should kick into gear within the next two years.

In addition to traditional applications (UV lamps replacement), and due to their unique properties (compactness, higher lifetime, robustness, etc.), UV LEDs are also creating new applications that aren’t accessible to traditional UV lamps, i.e. apps that are miniaturized and portable.

“In 2012, several new UV LED based products were launched, including cell phone disinfection systems, nail gel curing systems and miniaturized counterfeit money detectors – and this is likely to continue!” explains announced Pars Mukish, Technology & Market Analyst, LED, at Yole Développement. “We estimate that if new UV LED applications continue emerging, the associated business could represent nearly $30M by 2017, which would increase the overall UV LED market size to nearly $300M,” he adds.

This market and technology analysis is a comprehensive review of every UV application (including a deep analysis of UV curing and UV disinfection purification), highlighting: UV working principle, market structure, UV LED market drivers and the challenges/characteristics associated, time-to-market, penetration rate & Total Accessible Market (TAM) for UV LEDs, and much more. Additionally, Yole Développement details the market metrics for traditional UV lamps and UV LEDs over the period 2012 – 2017, with splits by application for each technology (volume & market size, etc.).

The report also presents an analysis of emerging UV LED applications, detailing: short-term applications that have already begun emerging, UV LED Concept Knowledge theory, and more.

Once UVC LED performance is sufficient, the supply chain battle will intensify

The booming UVA/UVB market (mostly UV curing) has attracted several new players from different backgrounds over the past few years: traditional UV lamp suppliers, traditional UV system suppliers, pure UV LED system suppliers, and others. Each player employs a different strategy for capturing the maximum value created by this disruptive technology: horizontal integration (from UV lamp to UV LED), vertical integration (from UV LED device to UV LED system and vice-versa) or both (from UV lamp to UV LED system). We should point out that traditional UV lamp manufacturers are under the most pressure since they have to compensate for the waning lamp replacement market by diversifying their activities in higher supply chain levels.

In the end, every UV LED device/system manufacturer faces the same technical issues when it comes to integrating UV LEDs into a system (thermal management, optics, etc.), but experience is gained with each passing year. Once UVC LEDs achieve sufficient performance, there’s no way a manufacturer will allow the opportunity to pass them by. When that moment comes, the whole supply chain will become a mess due to an increasingly competitive environment, and consolidation will be necessary. Yole Développement analysis covers the UV LED industry, detailing: main players & associated strategies/business models, 2012 industrial value & supply chains, key players’ revenue and market share, and much more.

Bulk AlN vs. AlN on sapphire template: no current winner

AlN on sapphire templates are definitely the substrate of choice for UVA applications, as they provide the right mix between cost and performance. However, for UVC applications (and some UVB applications) the competition with bulk AlN substrate is strong, since such material could allow for improvement at the device level in terms of lifetime, efficiency (IQE and EQE) and power output.

Right now, the debate is still on. And even if bulk AlN’s superior performance has been demonstrated by companies such as Crystal-IS and HexaTech, the associated cost (2.5x to 4x more compared to AlN on Sapphire template) still remains an obstacle to developing UVC LEDs at a reasonable price.

Indeed, such a situation has already occurred with GaN substrate for visible LEDs. Bulk GaN was the ideal technical candidate, but cost was too high and sapphire was widely adopted instead. Will UV LEDs meet the same fate?

In addition to substrate issues for UVC LED development, epitaxy represents another challenge for increasing device performance. Such barriers will have to be surpassed before we see commercialized UV LED-based disinfection/purification systems.

graphene collapse observed in berkley labThe first experimental observation of a quantum mechanical phenomenon that was predicted nearly 70 years ago holds important implications for the future of graphene-based electronic devices. Working with microscopic artificial atomic nuclei fabricated on graphene, a collaboration of researchers led by scientists with the U.S. Department of Energy’s Lawrence Berkeley National Laboratory (Berkeley Lab) and the University of California (UC) Berkeley have imaged the “atomic collapse” states theorized to occur around super-large atomic nuclei.

“Atomic collapse is one of the holy grails of graphene research, as well as a holy grail of atomic and nuclear physics,” says Michael Crommie, a physicist who holds joint appointments with Berkeley Lab’s Materials Sciences Division and UC Berkeley’s Physics Department. “While this work represents a very nice confirmation of basic relativistic quantum mechanics predictions made many decades ago, it is also highly relevant for future nanoscale devices where electrical charge is concentrated into very small areas.”

Crommie is the corresponding author of a paper describing this work in the journal Science. The paper is titled “Observing Atomic Collapse Resonances in Artificial Nuclei on Graphene.”  Co-authors are Yang Wang, Dillon Wong, Andrey Shytov, Victor Brar, Sangkook Choi, Qiong Wu, Hsin-Zon Tsai, William Regan, Alex Zettl, Roland Kawakami, Steven Louie, and Leonid Levitov.

Originating from the ideas of quantum mechanics pioneer Paul Dirac, atomic collapse theory holds that when the positive electrical charge of a super-heavy atomic nucleus surpasses a critical threshold, the resulting strong Coulomb field causes a negatively charged electron to populate a state where the electron spirals down to the nucleus and then spirals away again, emitting a positron (a positively–charged electron) in the process. This highly unusual electronic state is a significant departure from what happens in a typical atom, where electrons occupy stable circular orbits around the nucleus.

 “Nuclear physicists have tried to observe atomic collapse for many decades, but they never unambiguously saw the effect because it is so hard to make and maintain the necessary super-large nuclei,” Crommie says. “Graphene has given us the opportunity to see a condensed matter analog of this behavior, since the extraordinary relativistic nature of electrons in graphene yields a much smaller nuclear charge threshold for creating the special supercritical nuclei that will exhibit atomic collapse behavior.”

Perhaps no other material is currently generating as much excitement for new electronic technologies as graphene, sheets of pure carbon just one atom thick through which electrons can freely race 100 times faster than they move through silicon. Electrons moving through graphene’s two-dimensional layer of carbon atoms, which are arranged in a hexagonally patterned honeycomb lattice, perfectly mimic the behavior of highly relativistic charged particles with no mass. Superthin, superstrong, superflexible, and superfast as an electrical conductor, graphene has been touted as a potential wonder material for a host of electronic applications, starting with ultrafast transistors.

In recent years scientists predicted that highly-charged impurities in graphene should exhibit a unique electronic resonance – a build-up of electrons partially localized in space and energy – corresponding to the atomic collapse state of super-large atomic nuclei. Last summer Crommie’s team set the stage for experimentally verifying this prediction by confirming that graphene’s electrons in the vicinity of charged atoms follow the rules of relativistic quantum mechanics. However, the charge on the atoms in that study was not yet large enough to see the elusive atomic collapse.

“Those results, however, were encouraging and indicated that we should be able to see the same atomic physics with highly charged impurities in graphene as the atomic collapse physics predicted for isolated atoms with highly charged nuclei,” Crommie says. “That is to say, we should see an electron exhibiting a semiclassical inward spiral trajectory and a novel quantum mechanical state that is partially electron-like near the nucleus and partially hole-like far from the nucleus. For graphene we talk about ‘holes’ instead of the positrons discussed by nuclear physicists.”

Non-relativistic electrons orbiting a subcritical nucleus exhibit the traditional circular Bohr orbit of atomic physics. But when the charge on a nucleus exceeds the critical value, Zc, the semiclassical electron trajectory is predicted to spiral in toward the nucleus, then spiral away, a novel electronic state known as “atomic collapse.” Artificial nuclei composed of three or more calcium dimers on graphene exhibit this behavior as graphene’s electrons move in the supercritical Coulomb potential.

To test this idea, Crommie and his research group used a specially equipped scanning tunneling microscope (STM) in ultra-high vacuum to construct, via atomic manipulation, artificial  nuclei on the surface of a gated graphene device. The “nuclei” were actually clusters made up of pairs, or dimers, of calcium ions. With the STM, the researchers pushed calcium dimers together into a cluster, one by one, until the total charge in the cluster became supercritical. STM spectroscopy was then used to measure the spatial and energetic characteristics of the resulting atomic collapse electronic state around the supercritical impurity.

“The positively charged calcium dimers at the surface of graphene in our artificial nuclei played the same role that protons play in regular atomic nuclei,” Crommie says. “By squeezing enough positive charge into a sufficiently small area, we were able to directly image how electrons behave around a nucleus as the nuclear charge is methodically increased from below the supercritical charge limit, where there is no atomic collapse, to above the supercritical charge limit, where atomic collapse occurs.”

Observing atomic collapse physics in a condensed matter system is very different from observing it in a particle collider, Crommie says. Whereas in a particle collider the “smoking gun” evidence of atomic collapse is the emission of a positron from the supercritical nucleus, in a condensed matter system the smoking gun is the onset of a signature electronic state in the region nearby the supercritical nucleus. Crommie and his group observed this signature electronic state with artificial nuclei of three or more calcium dimers.

“The way in which we observe the atomic collapse state in condensed matter and think about it is quite different from how the nuclear and high-energy physicists think about it and how they have tried to observe it, but the heart of the physics is essentially the same,” says Crommie.

If the immense promise of graphene-based electronic devices is to be fully realized, scientists and engineers will need to achieve a better understanding of phenomena such as this that involve the interactions of electrons with each other and with impurities in the material.

“Just as donor and acceptor states play a crucial role in understanding the behavior of conventional semiconductors, so too should atomic collapse states play a similar role in understanding the properties of defects and dopants in future graphene devices,” Crommie says. “Because atomic collapse states are the most highly localized electronic states possible in pristine graphene, they also present completely new opportunities for directly exploring and understanding electronic behavior in graphene.”

In addition to Berkeley Lab and UC Berkeley, other institutions represented in this work include UC Riverside, MIT, and the University of Exeter.

Berkeley Lab’s work was supported by DOE’s Office of Science.  Other members of the research team received support from the Office of Naval Research and the National Science Foundation. Computational resources were provided by DOE at Berkeley Lab’s NERSC facility.

MRAM: disruptive technology for storage applicationsEveryone wants faster access to stored data, and the issue is becoming critical with Big Data and cloud initiatives. With the speed of DRAM and the non-volatility of storage, Magnetoresistive Random Access Memory (MRAM) encourages a new way of thinking about storage applications. Storage is associated with longer latencies, but with MRAM storage can have similar latencies to memory. These capabilities and others make MRAM a catalyst for new thinking about how we design storage applications.

MRAM Overview

MRAM stores data using magnetic polarization rather than electric charge. As a result, MRAM stores data for decades while reading and writing at RAM speed without wearing out. MRAM products use an efficient cell with one transistor to deliver the highest density and best price/performance in the non-volatile RAM marketplace.

The first generation of commercial MRAM uses the magnetic field from current pulses in corresponding metal digit lines and bit lines. Toggle MRAM uses a unique sequence of pulses, bit orientation and proprietary layers in the magnetic tunnel junction. Products developed with Toggle MRAM are SRAM compatible in specification and package, filling a need where data persistence is critical.

Prior to MRAM, system designers had to provide a way to protect critical data in the event of power loss. In the case of SRAMs, a battery is required to keep the device powered up to retain critical data, but batteries present a host of issues such as replacement, frequent failures and disposal. Chipmakers have also resorted to integrating both SRAM and non-volatile memory such as EEPROM or Flash in a single chip, commonly called nvSRAM. The complexity of this approach drives up chip cost and adds to system complexity in order to ensure that critical data is backed up when power fails. With the inherent, automatic non-volatility of MRAM, system designers have been utilizing MRAM in a broad base of applications including enterprise storage, industrial automation, smart meters, transportation, and embedded computing. Whenever frequent writing of critical data that must be protected in the event of power loss is a requirement, Toggle MRAM based persistent SRAM is now the preferred choice because of the simplicity of implementation, compatibility with CPU memory busses, and elimination of less reliable, more complex methods to protect the critical data.

Advances in Spin Torque MRAM development expands the market

The introduction of ST-MRAM, the second generation of MRAM technology, with a high bandwidth DDR3 DRAM interface brings MRAM into a category of the memory market with DRAM-like performance, combined with non-volatility, called persistent DRAM. Now MRAM can be utilized in the data path of applications that need extremely low latency, high endurance and, again, protection of data on power loss. Storage devices, appliances and servers will benefit from a persistent DRAM class of product.

Storage servers have resorted to employing large, bulky super capacitors to DRAM modules to provide enough residual energy to capture last written data, or they have employed non-volatile DIMMs (modules), which have both DRAM and non-volatile memory at a significant cost adder. MRAM, with its relatively simple, 1 transistor + 1 magnetic tunnel junction structure, eliminates the need for costly batteries, capacitors or complex mixed technology RAMs to provide the best combination of non-volatile memory and RAM-like performance.

Scaling the MRAM bit cell to allow for higher density in more advanced lithography nodes will require a transition from field switching to spin torque switching. Figure 1 shows a comparison between the two. In spin torque, the free layer is flipped with the angular momentum from the electrons going from one magnetic layer to the other through the tunnel barrier. This approach eliminates the need to generate a magnetic field with current in metal lines as is done in the toggle write technique. The simpler structure has the potential to provide the path to higher densities and lower cost per bit, which are fundamental to becoming a mainstream memory technology.

Although the density of initial spin torque MRAM (ST-MRAM) products will not be as high as the aforementioned DRAM and NAND Flash products, the added benefit of non-volatility at RAM speeds will make ST-MRAM a valuable addition to those memory technologies. This breakthrough approach is leading to new thinking about memory hierarchy as system designers, both hardware and software, start utilizing ST-MRAM as a performance and reliability enhancement in systems such as enterprise storage.

For example, there is a potential to complement and extend the system life of NAND based SSDs by providing a layer of persistent memory that does not have an endurance issue, or to extend the performance of high-end storage appliances that cannot tolerate the longer latency required to program NAND Flash memory. Loss of data on power outages can be addressed by adding a bank of ST-MRAM in a traditional DRAM cache in a server application and protect the last data being written. Making memory controllers, RAID controllers or SSD controllers both aware of and capable of talking to ST-MRAM is part of the ecosystem development in storage that is taking place now.

The longer-term promise of ST-MRAM is that it will rapidly scale down the semiconductor technology feature size roadmap and attain Gigabit densities in the coming years at feature sizes in the 20nm range. This opens up even further market opportunity as ST-MRAM can be thought of as either a DRAM replacement technology or an alternative mass storage technology. In the meantime, MRAM has quickly become the preferred choice for protecting critical data in a wide range of systems and will reach into storage systems as a performance and reliability enhancement as ST-MRAM products move to production.

A New Storage Tier

There is a gap between DRAM and NAND Flash when it comes to performance. MRAM makes it possible to disrupt computer design by adding a new tier of storage between the DRAM and NAND Flash. You have a microprocessor with one, two, or three levels of cache memory so the processor doesn’t wait for data to come to it over a memory bus. The DRAM keeps loading that microprocessor cache with updated information, trying to anticipate what the CPU will want next.

DRAM has a speed on the order of tens of nanoseconds, but DRAM is quite expensive in storage terms. Rather than putting in hundreds of gigabytes of DRAM, designers use data storage. The data still has to go over a storage bus like SATA or SAS, and even though these storage buses are quite fast there’s still a latency getting data from a spinning disk – milliseconds of time. NAND Flash has changed that tremendously, and this is why we see a tremendous adoption of NAND Flash SSDs.

However, NAND Flash has asymmetrical performance. It is very fast when reading data, but the limitation is that it doesn’t write very fast. When it comes time to put data back into storage there’s a latency there that can be measured in microseconds. And what NAND offers in density and cost it lacks in endurance – it wears out quickly. DRAM and MRAM have virtually infinite endurance, on the order of 1015 or more writes, but some of the NAND on the market now has only tens of thousands of wear cycles.

So even with NAND Flash, computer and storage systems are still limited by data storage in terms of performance. In order to increase IOPS, you have to break that bottleneck. That’s where MRAM comes in. MRAM can supplement the cache RAM in a microprocessor as well as buffer data storage.

Because MRAM is persistent and also has the speed of DRAM, system architects can start thinking about where that boundary is between RAM to the processor and storage to the storage system. In an ideal world, you would have MRAM at high enough densities to where it can act as a storage layer. Because it has infinite endurance you no longer care about wear leveling or overprovisioning as you have with NAND Flash. This is not to say that MRAM will take the place of NAND Flash, but it will create a new storage tier that bridges the gap between DRAM and NAND Flash. MRAM would be a faster, solid-state array for very performance-intensive applications, or another caching tier where the NAND Flash is loading into and out of MRAM.

If the operating system is aware that there’s a tier of non-volatile memory out there, it can really begin to take advantage of that from a performance standpoint. The IOPS will go way  up, and performance is greatly enhanced.

 RAM Cache Applications

The other application for MRAM is in the RAM cache itself. While data is in RAM, it’s vulnerable. When there’s a power glitch, the data that’s in RAM may not be stored permanently anywhere yet. For high-reliability storage, system architects jump through hoops to mitigate that problem with supercapacitors or batteries. These provide enough power to the RAM to flush whatever’s in DRAM to NAND Flash in the event of a power disruption. But supercapacitors add tens to even a hundred dollars to the BOM for a DRAM tier, and batteries are notoriously unreliable.

If you use MRAM instead of DRAM, data written to the MRAM cache is permanent. Power losses don’t affect the storage of data in MRAM. So we have an opportunity to simplify system design, enhancing reliability and eliminating the need for these other ways to provide energy to DRAM. In this case, MRAM will replace DDR3 DRAM.

MRAM can sit on the same memory bus as the DDR3 DRAM, and you can have a couple of banks of DRAM and a couple of banks of MRAM. This allows designers to segment the cache between writes and reads. Typically you need a very large read buffer for the amount of data coming off the disk arrays to the CPU, but where you’re writing there’s a relatively small amount of data. The concept is to have the MRAM function as the write cache.

We can also think about MRAM as a new storage tier, where what they’ve done to accelerate storage is to put NAND arrays in front of HDDs on a serial ATA bus. Now we’re proposing that there be a smaller array but with even higher performance in MRAM that can talk to any kind of controller or processor.

As we can see, MRAM presents several different disruptive applications for storage and computer design. As MRAM densities improve and costs decline, it will become a standard part of storage infrastructure.

Joe O’Hare is the director of product marketing at Everspin Technologies.

 

researcher Ma Ming developes brighter, smarter, more efficient LEDsRensselaer Polytechnic Institute student Ming Ma has developed a new method to manufacture light-emitting diodes (LEDs) that are brighter, more energy efficient, and have superior technical properties than those on the market today. His patent-pending invention holds the promise of hastening the global adoption of LEDs and reducing the overall cost and environmental impact of illuminating our homes and businesses.

For this innovation, Ma, a doctoral student in the Department of Materials Science and Engineering, has been named the winner of the prestigious 2013 $30,000 Lemelson-Rensselaer Student Prize. He is among the three 2013 $30,000 Lemelson-MIT Collegiate Student Prize winners announced today.

“For more than 175 years, Rensselaer has produced some of the world’s most successful engineers and scientists, explorers and scholars, innovators and entrepreneurs. Doctoral student Ming Ma, with his groundbreaking invention of GRIN LEDs, honors and continues this tradition of excellence,” said David Rosowsky, dean of the School of Engineering at Rensselaer. “Rensselaer and the School of Engineering offer a hearty congratulations to Ming for his achievement. We also applaud all of the winners, finalists, and entrants of the Lemelson-MIT Collegiate Student Prize for using their talent and passion to engineer a better world and a better tomorrow.”

Ma is the seventh recipient of the Lemelson-Rensselaer Student Prize. First given in 2007, the prize is awarded annually to a Rensselaer senior or graduate student who has created or improved a product or process, applied a technology in a new way, redesigned a system, or demonstrated remarkable inventiveness in other ways.

“Invention is critical to the U.S. economy. It is imperative we instill a passion for invention in today’s youth, while rewarding those who are inspiring role models,” said Joshua Schuler, executive director of the Lemelson-MIT Program. “This year’s Lemelson-MIT Collegiate Student Prize winners and finalists from the Massachusetts Institute of Technology, Rensselaer Polytechnic Institute, and the University of Illinois at Urbana-Champaign prove that inventions and inventive ideas have the power to impact countless individuals and entire industries for the better.”

Seeking Brighter, Smarter LEDs

Conventional incandescent and fluorescent light sources are increasingly being replaced by more energy-efficient, longer-lived, and environmentally friendlier LEDs, but LEDs still suffer from challenges related to brightness, efficiency, and performance  With his project, “Graded-refractive-index (GRIN) Structures for Brighter and Smarter Light-Emitting Diodes,” Ma faced these problems head-on and tackled a fundamental, well-known technical shortcoming of LED materials.

LEDs are hampered by low light-extraction efficiency—or the percentage of produced light that actually escapes from the LED chip. Currently, most unprocessed LEDs have a light-extraction efficiency of only 25 percent, which means 75 percent of light produced gets trapped within the device itself.

One solution that has emerged is to roughen the surface of LEDs, in order to create nanoscale gaps and valleys that enable more light to escape. While surface roughening leads to brighter and more efficient light emission, the roughening process creates random features on the LED’s surface that do not allow for a complete control over other critical device properties such as surface structure and refractive index.

Freeing Trapped Light with GRIN LEDs

Ma’s solution to this problem was to create an LED with well-structured features on the surface to minimize the amount of light that gets reflected back into the device, and thus boost the amount of light emitted. He invented a process for creating LEDs with many tiny star-shaped pillars on the surface. Each pillar is made up of five nanolayers specifically engineered to help “carry” the light out of the LED material and into the surrounding air.

new brighter smart more efficient LEDMa’s patent-pending technology, called GRIN (graded-refractive-index) LEDs, has demonstrated a light-extraction efficiency of 70 percent, meaning 70 percent of light escaped and only 30 percent was left trapped inside the device—a huge improvement over the 25 percent light-extraction efficiency of most of today’s unprocessed LEDs. In addition, GRIN LEDs also have controllable emission patterns, and enable a more uniform illumination than today’s LEDs.

Overall, Ma’s innovation could lead to entirely new methods for manufacturing LEDs with increased light output, greater efficiency, and more controllable properties than both surface-roughened LEDs and the LEDs currently available in the marketplace.