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In 3D integration, wafers are thinned, stacked and connected to one another with through silicon vias (TSVs). The process of wafer thinning and TSV formation typically involves the use of a wafer bonding/debonding technology, where the wafers are bonded onto a carrier substrate – either silicon or glass – processed, and then debonded. The bonding/debonding step can be tricky because the bond has to be strong enough to withstand relatively high temperature processes and polishing steps, but not so strong as to make debonding difficult. It’s also critical that minimal stress be introduced to the device wafer during the debonding step (which can involve sliding or peeling), and that no residue remain. Room temperature debonding is also desirable.  

A variety of techniques and materials have been developed to successfully achieve bonding/debonding, but Tony Flaim, chief technology officer of Brewer Science (Rolla, MO) says they are still too complicated. Brewer Science introduced the ZoneBOND technology in the 2008/2009 timeframe, and it has been implemented by tool suppliers such as EVG and SUSS. In an interview at The ConFab in June, Flaim said: “This is one of the industry’s first methods for separating the carrier from the bonded pair under low stress, low temperature conditions. It can be done at room temperature. We’ve had customers adopt that technology and are using it for some low volume production.”

High volume manufacturing of 3D integration with TSVs might not occur for another two years. To date, TSVs have been primarily used in limited applications such as image sensors where back-to-front contact is required. The first true stacked, 3D integrated device to go into production will likely be the Hybrid Memory Cube sometime next year.

“The industry is at best in low volume production with things like high density interposers and a few stacked devices, but for the most part we really haven’t seen anyone going into high volume manufacturing with the technology,” Flaim said.  “What we’re trying to do, until that time arrives, is move on to a third generation of technology that will basically involve all the steps in the process and simplifying more than they are now.” He said that with ZoneBond and competing technologies, they have six basic process steps, but at a more detailed level, you can see as many as 20-25 steps. “Some of those steps are lengthy, they can be minutes or even up to hours in some cases to perform. We believe that for temporary wafer bonding technology and in fact for 2.5D and 3D integration to occur, we’re going to have to have a much simpler, more reliable, more cost-effective process. That’s really our goal for the next two years,” Flaim said.

In terms of ideal process temperature, Flaim said the bulk of their customers are working in the range of 250-260°C, but it’s clear that they want to go higher. Dielectric cure processes and deposition processes, for example, would yield better material properties when performed at a higher temperature.  “We’re trying to move our whole materials set to have thermal stability at 280, 300°C or maybe even beyond. But the trick is still getting them back apart. That’s where ZoneBond and some of the other release technologies that we’re working on now will really provide the advantage.  You decouple the thermal stability from how you separate from the stack. You can still be operating under a low stress, low temperature condition when you take the bonded structure apart, but the materials within the structure are surviving the high temperature.”

See the video interview of Tony Flaim at The ConFab by clicking here.

Engineering samples of The Hybrid Memory Cube (HMC) are expected this summer, with high volume manufacturing coming next year. It will be one of the first high volume devices employing 3D integration and through silicon vias (TSVs), employing a bottom logic layer and 4-8 stacked DRAM layers.

The HMC is the result of a consortium formed in late 2011 by Micron, Samsung, Altera, Xilinx and Open-Silicon to define an industry interface specification for developers, manufacturers and architects of high-performance memory technology. The consortium has grown to 110 members, including SK Hynix, IBM and ARM. Analysts are projecting the TSV-enabled 3D market to be a $40billion market by 2017, or roughly about 10% of the global chip business.

We caught up with Micron’s Scott Graham, General Manager, Hybrid Memory Cube, at Semicon West. “Today, we’re very close to delivering our engineering samples this summer to our lead customers that are taking the technology into their system designs,” Graham said.  The lead applications are in high performance computing, such as supercomputers, as well as the higher end networking space. “Those will be the early adopters. As we move forward in time, we’ll see that technology evolve as costs come down for TSVs and manufacturing technology, it will enter into future space where traditional DDR type of memory has resided. Beyond DDR4, we can certainly see this of memory technology being a mainstream memory,” Graham said.

Since the HMC is an open specification in terms of the architecture of the device, it will be up to each memory manufacturer to decide how it might be customized and manufactured. “The way it’s done today is we source the substrate, we source the logic layer and then we bring those in-house and we complete the finishing of those logic wafers as well as all the slicing, dicing, stacking, assembly and test,” Graham said. “What we end up providing for the customer is a known good cube, or known good piece of memory, just like we would if it was a DDR device or wide I/O device,” he said. He added that the HMC is designed so that it has not only the repair capability during manufacturing but also out in the field. “It’s very flexible and very robust, so reliability is very high with this device,” he said.

The consortium delivered its first specification earlier this year. “We’ve since extended the consortium to work on both future generations of the HMC technology in both the short-reach and ultra-short reach configurations,” Graham said.

The HMC was designed to get high density and high bandwidth in a relatively small package. The team adopted an off-the-shelf SERDES I/O and that’s based on IBM’s 32nm process. “With that, we can achieve 10 Gbps, 12.5 Gbps, or 15 Gbps for those SERDES links,” Graham said. “If you look at a 2 GByte or a 4GByte HMC device, those first devices will deliver a total aggregate bandwidth of 160GBytes/sec. I want to emphasize those are bytes not bits. It’s a very high bandwidth and low energy per bit device that is something that can be designed into a multitude of systems.”

The consortium has several generations of the HMC device planned (this summer’s engineering samples are Gen2). “As we move forward, you’ll see us moving into the 28 Gbps SERDES as far as the I/O goes,” Graham said. Bandwidths are going to be 320 Gigabytes/sec and higher, and the density will be in 4Gbyte and 8 Gbyte configurations.

Graham said one of the main challenges they had to overcome was the stacking. “We’re stacking a logic layer on top of a substrate and then four to eight DRAM on top of those logic layers,” he said. “We have over 2000 TSVs in this package and it was a challenge to stack these ultrathin die and make sure that what we end up with is a high performance and very reliable package.” Graham declined to comment on the exact TSV process flow used at Micron, saying only that it was leading edge. “We had to make sure our equipment partners were up to speed and could deliver us the technology that would allow us to manufacture this in high volume,” he said.  

Because customer can customize the HMC design, another challenge it to make sure that the design capabilities are available at the foundry for that logic layer, Graham said.  

Heat dissipation in the device is achieved through a metal lid, and through the TSVs which acts as chimneys (in addition to conducting electricity). The photo shows two Gen2 HMC devices. The larger one, in a 31mm x31 mm package, is a 4 link device that will achieve 160 Gig-bytes per second. The smaller one is a two link device capable of 120 Gigabytes/sec, measuring 16mm x 19.5 mm. “Both are being manufactured now in our plant and we’re doing the whole debug phase,” explained Aron Lunde, program manager, DRAM solutions group at Micron in Boise. He said the metal lid was in contact with not only the top layer, but different internal layers. “We call it an integrated heat spreader. It makes contact at more than one level and that’s what really helps,” he said.

Although manufacturers such as Micron, Samsung and SK Hynix must now handle the manufacturing, assembly and test process, Graham believes that it could eventually evolve to the point where select foundry partners would be able to provide volume manufacturing services for these HMC cubes.

Graham said DDR4 will likely be the last DDR device. “Beyond DDR4, you have to move to managed memory like HMC technology,” he said.  “We’re solving the memory wall problem with HMC-like architecture and what’s really going to be happening in the future is that you’ll be running into a CPU wall. That’s going to be the barrier to system progress as we move forward.”

Graham expects some challenges with scaling of conventional memory at sub-20nm process nodes. “We get into physical challenges of meeting the timing requirements and the 12 pages of JEDEC specifications to be able to yield properly and to be able to provide a cost-effective memory device moving forward,” he said.  

Although the HMC is now designed around DRAMs, Graham said it would be possible to use other types of memories, and even a mixed set of memories. He noted Micron is looking at alternatives to the conventional DRAM cell, such as spin torque and resistive memories. “Micron is investing heavily in research in those technologies and of course the HMC team here at Micron is looking at future technologies that we can take HMC architecture and be able to utilize different DRAM or even flash types of memory,” he said. “As the technology matures and it becomes lower cost, we can see this technology certainly evolving into more global applications and utilizing different memory types in that stack – and perhaps even multiple memory types in that stack.”

HMCs could eventually make their way into mobile devices, but Graham said that is likely to be three or four years away. Mobile applications presently employ low power DDR3 solutions, which will be used for several years. “We’ll see quite a few interesting designs start spinning when the mobile folks see they can differentiate with a managed memory solution. It’s not going to be HMC as we know it today, it will have to be optimized for mobile,” Graham said.

In the afternoon of the last day of SEMICON/West 2013, a session was devoted to updates from the International Technology Roadmap for Semiconductors (ITRS) Front End of Line Technologies. Representatives from the different International Technology Working Groups (ITWG) provided highlights from the work now happening on the 2013 update.

Andrew Kahng of U.C. San Diego provided two presentations on challenges associated with future ICs:  System Drivers and the Design. Systems today are clearly driven by System-on-Chip (SoC) and mobile. The size of a typical mobile phone SoC is expected to double from ~50 mm2 to ~100 mm2 due to increased  integration of new functionalities such as Graphics Processing Units (GPU), memory controllers, and input/output (I/O) interfaces. Overall power for such a chip in the distant future would consume >200W of power compared to today’s ~8W unless new technologies are employed. Some future drivers such as medical and defense are now in question; will these segments develop unique devices and processes or will they simply ride on the progress of mainstream commercial IC development.

“The latter scenario is looking more likely now,” said Kahng.

Constant area-factors allowed prior node scaling to be 2x, however since 2009 the real scaling has been 2E(2/3)x or ~1.6x due to an “IC Design Gap.” This gap is due to overheads from non-core blocks and additional overheads from PIDS effects on the area needed for cores. Design cost for a SoC consumer portable chip in 2011 were $40M, helped by commercial EDA software advances over the last decades. Today only at most 2.4 percent of the logic in an SoC is turned on at any time, which is how the power can be kept to ~8W.

Modeling and Process Simulation challenges were covered by Lothar Pfitzner of Fraunhofer IISB, with understanding that the overarching goal of this ITWG is to use virtual cycle-of-learning to lower R&D costs. To do so there are different models needed in different conceptual domains, “based on quantitative physical understanding of processes, devices, circuits, and systems,” explained Pfitzner. “Both short-term and long-term challenges remain in modeling of chemical, thermo-chemical and electrical properties of new materials.”

PIDS updates on logic, DRAM, and Non-Volatile Memory (NVM) were provided by Mustafa Badaroglu of Qualcomm. PIDS mission is to forecast device technologies likely to be used 15 years in the future of main-stream manufacturing. With Denard-scaling now part of history, the specifications for future transistors using either FD-SOI or multi-gate (such as finFET) technologies require TCAD simulations of source-to-drain tunneling, band structure effects due to strong confinement, as well as crystallographic orientation and strain. The current target is an overall eight percent power reduction per year in logic, but parasitics dramatically limit device performance, and gate-length scaling is endangered by increased tunneling.

A 2013 survey recently done by the Japan PIDS regional group provides a consensus on when new devices are expected to reach volume manufacturing. For DRAM cells there has been a slight relaxation of the planned half-pitch, and  the cell size transition from 6F2 to 4F2 planned for 2016 (delayed by two years from the last ITRS update), and vertical transistors are likewise planned for 2016. RRAM is now planned as mainstream technology in 2018, and is projected to catch-up with the bit density of 3D Flash in 2021; however, development of a selector diode in a 3D architecture remains a challenge. The Purdue University TCAD tools (NanoHub) will continue to be developed to better project device characteristics, and new websites within NanoHub will be created to allow free public access to the tools.

Part 2 of this blog will cover ITRS updates on Lithography, Front-End Processing, and Emerging Research Materials/Devices.

Click here for more from SEMICON West.


SEMICON West 2013 included a robust set of technical and marketing presentations on the general theme of developing new semiconductor devices in the session “Lab to Fab: From R&D to High Volume Manufacturing” held 1:30-3:30PM on July 9. Ably moderated by Paula Doe, the session included presentations on modeling, experimenting, and prototyping new materials and structures such that they can profitably moved into high-volume manufacturing (HVM). Two of the presentations that described not just technologies but new fundamental methodologies for R&D came from Coventor and Intermolecular, small innovative companies based in Silicon Valley.

Dr. David Fried, CTO of Coventor, presented how the company’s “SEMulator3D” software modeling product based on “voxels” allows for advanced physics-based modeling of unit-processes, integrated-processes, device structures, and even device electrical parameters. The modeling starts with unit-processes such as depositions, etches, and epitaxial growth at the nanometer-scale. However, unlike TCAD and other device models, this software can also extend across length scales to provide full-wafer maps of physical parameters.

Fried explained how the model is built on data extracted from publicly available leading device information, such as the cross-section SEMs in Intel’s seminal IEDM paper on 22nm finFETs. The model is “behavioral” since it can predict the effects of changes in dynamic process conditions, and can therefore be used to do “virtual fabrication” of targeted devices. “You can do some interesting explorations,” explained Fried, “like what if you had a defect on a fin that was used to grow an epi-layer?” He showed how the complex interactions of different growth rates in different crystalline directions on 3D structures could be predicted by the software, and that the predicted structural shifts  appear to match the SEM cross-sections shown in the literature.

This modeling software can thus be used as a “virtual metrology” tool that can mimic real in-fab metrology. It can replace slow out-of-fab destructive characterization, and can provide local virtual measurements of structural parameters. It can be used to study the effects of incoming geometric parameters as well as process variations on the final structure. For example, the Cu cross-section area of a BEOL interconnect layer can be predicted, in contrast to unit-process models/controls that merely create wafer-uniformity-maps of  Etch, Cu-barrier/seed PVD, Cu-ECD, Cu-CMP, and other process steps.

Combinatorial R&D

Dr. Raj Jammy, Sr. VP & GM Semiconductor Group, Intermolecular, Inc.—most recently a SEMATECH VP—discussed the need for new ways of doing R&D now that the integration of new materials dominates device enhancements. As semiconductor technology has evolved to smaller and smaller device geometries, the number of new materials used on CMOS chips continues to increase. Consequently, the cost of discovering and integrating new materials into complex devices structures continues to increase.

New materials are needed for 3D FinFETs (alternate-channel materials), 3D Flash Memories and ReRAM (storage cells), and 3D packaging (through-silicon vias and through-mold vias), and all  use complex processes with unpredictable interactions. Developing and optimizing these new materials leads to high costs for R&D and even higher costs to integrate into HVM.

Intermolecular has created High Productivity Combinatorial (HPC™) tools for PVD, CVD, ALD, and wet-processing steps that allow for multiple site-isolated experiments to be done on a single 300mm wafer. When combined with throughput-match characterization tools using an automated database into what the company terms an application-specific “HPC workflow,” everything from an initial design-of-experiments (DOE) to full HVM integration can be done in 3-6 months instead of the 3-5 years needed by conventional R&D approaches.

HPC workflows can accelerate R&D in the early stages of materials exploration such that an entire cycle-of-learning can occur in just 4 hours. HPC workflows can also be used with short-loop flows through a customer’s fab to allow for a 3-4 week cycle-of-learning.

As an example of this methodology’s ability to accelerate learning, Jammy showed how hundreds of experimental parameters had to be explored in developing a germanium (Ge) MOS cap for CMOS integration. Variations in the substrate, surface cleaning, High-K stack, metal electrode, and post-treatment all play significant roles in determining the final device parameters. All these factors had to be co-optimized iteratively, and the project was accomplished in <3 months.

IMI started in 2004 with SanDisk and ATMI, and has since added Guardian Corp., Toshiba, IBM, First Solar, GlobalFoundries, Epistar, Micron as customers.


When Ajit Manocha, GlobalFoundries CEO, polled his audience during his keynote address on Tuesday at SEMICON West 2013, nearly 60 percent of the audience believed that the biggest challenge facing the semiconductor industry was the economy. However, during his presentation, Manocha seemed to suggest otherwise.

The technology business is booming, according to Manocha, who shared with SEMICON attendees that the mobile business is forecast to be double the size of the PC market in 2016. The mobile business drives many new requirements, said Manocha, including power, performance and features, higher data rates, high resolution multicore processors and thinner form factors.

This incredible growth is driving new dynamics, said Manocha, and pushing the industry to the new technology node each year, which is presenting the industry with what Manocha deems the Big Five Challenges. Manocha believes these challenges are: cost, device architectures, lithography and EUV, packaging and the 450mm wafer transition.

Cost, said Manocha, continues to be the underlying challenge of the entire industy, because, without focusing on wafer cost, even in good times, a company can enter into what he called “profitless prosperity.” Unfortunately, with the introduction of a new technology node each year, advanced technology costs are rapidly rising.

“Fab cost alone escalates 40 percent year after year,” said Manocha.

To keep wafer costs down, what Manocha believes the industry needs for success is a new foundry model altogether. His model, which he calls Foundry 2.0, hinges on industry collaboration rather than wafer price competition. By encouraging the industry to work together on products and meet the same goals, the industry can see a faster rate of change and tap into global R&D talent.

“The best solutions rarely originate from an insultated team,” he said. “It’s critical that we understand what customers need.”


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The future is bright for the future semiconductor and IT industry, according to Samsung exec Yoon Woo (Y.W.) Lee. In a keynote talk at The ConFab, Mr. Lee described a future with dramatic advances in almost every field, including healthcare, nano, energy and the environment, all powered by semiconductors. The end result:  a smarter, healthier and cleaner planet. Mr. Lee, who is widely credited with the success of Samsung’s semiconductor business, is now an Executive Advisor at Samsung Electronics Co., Ltd. He previously held positions at Vice Chairman and CEO, Chairman of the Board of Directors, and Chief Technology Officer at Samsung Electronics.

Mr. Lee noted two major trends in the world’s population: more people living in cities, and a greater number of elderly. “There will be 500 cities with over 1 million people by 2015,” Mr. Lee said. “Such a trend will stimulate the IT industry.” According to UN projections, more than 400 of these cities will be in developing countries. The number of "megacities" of 10 million people or more also will increase. Worldwide by 2015, 22 cities will be this big, all but five in developing countries. “Asia continues to grow into the largest economy in the world,” Lee said.

By 2020, most of the rich world will be a “super-aged” society, Lee added. A country can be described as an aging society when people aged sixty-five or above make up more than 7% of the total population (as in China). When the elderly make up more than 20% of the population, the country has a super-aging society.

“From a business perspective, bio and healthcare holds great potential,” Lee said. He also spoke on the importance of global sustainability, which he said will face strain. “There are finite reserves of oil. We must also address global warming which is behind extreme weather conditions.”

Lee said much of the remarkable progress in fields such as mobile computing and medicine has been possible due to the advancement of IT, and semiconductors in particular. “The industry strives for greater performance, lower power, and smaller form factor to enable this technology migration,” he said.

He noted that new innovations, such as nanowires and transistors with III-V channels, are being developed for 10nm chips, and said the use of new TSV technology “will raise transfer speed, function less power and reduce size.”

He also predicted that optical interconnects would soon be required. “Exascale computing will require optical interconnection to communicate between the CPU and memory chip,” he said.

He also gave a nod to MEMS devices, saying nanostructures would be used to switch mechanical energy such as background noise and wind into electric energy. “Our movement will be converted into electricity that charges most of our mobile device in the future,” he said.

As part of his presentation, Lee asked the audience to imagine what it would be like in the year 2025, when we will experience a smarter world, a healthier life and a cleaner planet. Among the advances expected:

  • A light field 3D camera that easily captures three dimensional information, color and depth data simultaneously from different viewpoints in order to generate an accurate real-life picture.
  • Tangible interaction technology that will enable the user to directly touch and freely manipulate three dimensional images in open space. One will be able to actually feel the shape, the temperature and even the texture of a real object.
  • Displays in the form of a contact lens. Augmented reality on such lenses will inform you of traffic and weather conditions.
  • With thermochromic materials, it will be easy to check what’s inside the fridge. When exposed to heat, these thermal sensitive molecules lose their alignment and by transmitting light more readily the material becomes semi-transparent.
  • A terahertz medical mirror that exploits terahertz antenna technology to enable real-time medical diagnosis, or remote treatment with nanotechnology allowing the system to be miniaturized for household or portable use.
  • Using intra-operative optical spectroscopic imaging, tissue can be analyzed without waiting for the pathology lab. By 2025, the aggregate medical data from patients worldwide will reach 6 zettabytes (1021 bytes), roughly equivalent to 6 quadrillion books. From the use huge volume of databases, we can find similar cases by analyzing the organ, physiological and molecular level data, using this “big data” to optimize medical diagnoses.
  • Clean and inexhaustible energy based on hydrogen, from sunlight and water will provide electricity and heat without releasing greenhouse gases.
  • Batteries will be entirely redesigned to utilize abundant and affordable substances such as magnesium or sodium, taking increasingly important roles in the future of large scale power storage.
  • Next generation microorganisms can biodegrade waste and transform these products into highly concentrated raw materials. This technology can also be used to inexpensively produce new plastic materials for many applications.

Lee concluded with a call for collaboration, which he said is critical in intra-regional trade and development. “Countries will need to lower risk and boost efficiency through closer cooperation along the supply chain, forging alliances, devising common standards, and undertaking joint R&D,” he said.

Much has been said of the 450mm transition.  But the description of this inflection is something of a misnomer.  Though everyone desires a smooth, coordinated and orderly conversion, it may be a little less placid than the term “transition” implies.  Rather, I suggest calling it the 450mm “transformation.”   Because, even for the segments that continue manufacturing semiconductor devices on 300mm and 200mm silicon wafers, the industry will change dramatically with the introduction of 450mm wafer processing. The 450mm era will impact industry composition, supply chain dynamics, capital spending concentration, future R&D capabilities and many other facets of today’s semiconductor manufacturing industry — not the least of which are the fabs, wafers and tools with which chips are made.

The shift to 450mm will take a several years to manifest and numerous complexities are being skillfully managed by multiple organizations and consortia.   For those reasons, the evolutionary tone of “transition” seems appropriate. However, once the changeover occurs, in hindsight, most in the industry will recognize that they participated in something transformational.

No transformation occurs in isolation and other factors will contribute to the revolutionary qualities of 450mm.  Market factors, new facilities design, next generation processing technology, the changing dynamics of node development and new materials integration will simultaneously affect the industry landscape.

While reading about the implications of 450mm is valuable, I believe that there is much to learn by being a part of the discussion. How is this future transformation being envisioned and acted on today?  I hope that you will join us — at our “live” event, where you will have the opportunity to hear first-hand information… direct from well-informed experts in the industry.

SEMICON West offers this opportunity with “Must See” 450mm events to mark on your calendar…

….450 Consortia plans, timelines and status; equipment development; critical standards; future-looking fab facilities and EHS issues; executive perspective, and vital R&D capabilities will all be covered at SEMICON West.

Wafer Standards

The transition to 450mm manufacturing is accompanied by the development of various standards aimed at achieving cost, efficiency and technology improvements. Some standards are a product of the deliberate consensus-based SEMI International Standards program, which has produced over 15 essential 450mm-specific standards to-date.  Additionally, consortia, customers and suppliers organize complementary efforts to align common approaches to transition solutions.

Potential revisions in the 450mm wafer specification are under consideration.  At least two issues are currently being evaluated by the industry and both portend significant ramifications for wafer suppliers, equipment makers and those technologies that interface with the wafer.

First, the wafer orientation method may be revised to eliminate the orientation “notch” on the perimeter of the substrate. The notch was introduced in the 300mm transition as an alternative to the flat.  However, both equipment suppliers and IC makers, through a constructive and collaborative dialog, have concluded that eliminating the notch can potentially improve the die yield, tool performance and cost.

Secondly, reduction of the wafer edge exclusion area — that peripheral portion of the silicon on which no viable device structure occurs — also offers potential yield advantages.  The current 450mm wafer specification (SEMI E76-0710), originally published in 2010, calls for a 2mm edge exclusion zone.  IC makers believe that reduction of this area to a 1.5mm dimension offers the cost equivalence of a 1 percent yield increase.  Though a percent may sound trivial, it is represents substantial increased value over time.

These and other wafer-related issues will be key topics at SEMICON West and will be thoroughly reviewed on Wednesday, July 10 at the SEMI Standards program entitled “Silicon Wafers — Future Standardization to Enable the Transition.” Materials will be presented by expert speakers including authoritative customers participating in the Global 450 Consortium (G450C), which includes Samsung, TSMC, IBM, Intel and GLOBALFOUNDRIES.

Facilities and EHS

Wafer transitions offer one of the rare periods when new approaches can be developed and integrated into facilities plans.  During the 300mm transition, significant developments occurred in factory automation and wafer handling. Similarly, the 450mm transition is a window to update the industry approach to a number of fab systems. Rising energy costs, water scarcity, and climate change will continue to present both challenges and opportunities for semiconductor manufacturing in the 450mm era. These sustainability concerns are driving demand for tools that can more reliably and cost-effectively achieve a shared vision of resource balance.

Along with cost and efficiency improvements, IC makers and consortia driving the transition to 450mm manufacturing expect to achieve similar or better environmental performance. Larger footprints and resource demands from 450mm facilities in conjunction with mandates for environmentally aware operations are compelling fabs and suppliers to consider sustainability and systems integration at greater levels than ever before. 

Experts in fab facilities, energy, water and equipment engineering will discuss the implications of 450mm to environment, health and safety during the SEMICON West 450mm Manufacturing EHS Forum on Wednesday, July 10.

Included in the presentations are perspectives from the Facility 450 Consortium (F450C) including Ovivo, Edwards and M+W Group.  A holistic Site Resource Model that provides semiconductor manufacturers visibility into effective reduction of total energy and water demands for individual systems, as well as for the entire facility will be reviewed by CH2M Hill. The model is an integrated analytical approach to assess and optimize a semiconductor facility’s thermal energy, electrical energy, and water demand, as well as the cost associated with these resources.

Also, the bigger, heavier and taller equipment envisioned for 450 entails new considerations for installation, movement and maintenance.  Making sure these issues don’t detract from the other cost saving achievements is a key consideration for facilities planning.  G450C representatives will review the status of component lift analysis currently underway. The solutions potentially alter fab facilities dimensions, tool engineering and service regimes.

450 TechXPOT

The SEMICON West 450mm Transition Forum covers the latest updates from those closest to the action.  The event occurs on Thursday, July 11 at the South Hall TechXPOT located in Moscone Center.  Paul Farrar, general manager of Global 450mm Consortium will provide an update and status on G450C. Hamid Zarringhalam, executive vice president, Nikon Precision, will review the challenges and status of 450mm lithography — which is shaping up to be one of the most uncertain yet critical 450mm planning considerations. Chris Richard, a partner at PricewaterhouseCoopers, LLC will talk about “Improving Semiconductor Equipment Vendor Profitability during the 450mm Transition.”

Then, SEMI will host a discussion among the world’s foremost 450mm tool experts from leading equipment companies.  The discussion panel will include: Kirk Hasserjian, corporate vice president, Silicon Systems Group, Applied Materials, Inc., Brian Trafas, Ph.D., chief marketing officer, KLA-Tencor; Mark Fissel, vice president, 450mm Program, Lam Research Corporation; and Akihisa Sekiguchi, Ph.D., vice president and general manager of SPE Marketing, Tokyo Electron Limited.  We have a few provocative topics to review with panel members.  If you have questions or topics you want addressed by those at the front line of the 450mm transformation, feel free to send us your suggestions.

In summary, a transformation will occur in IC manufacturing with the introduction of larger wafers, but it begins with serious engineering that is occurring now.  Attend SEMICON West to learn more about wafer specifications, EHS and facilities— considerations and business strategies for success and be better prepared for the numerous implications of 450mm era.

Learn more about it here: Register now at



Reinventing Intel

April 19, 2013

Intel logoIntel is looking to reinvent itself.

With PC shipments reportedly in free fall, the company reported a sharp decline in its quarterly profits last week, which isn’t surprising, given that the company’s PC chip division accounted for 64 percent of its total revenue and 89 percent of its operating income in 2012. The company reported net income to $2.05 billion, a decline of 25 percent from $2.74 billion in the period last year.  However, analysts at IHS believes Intel has the innovation to stay on top this year, but other reports from decision makers at the semiconductor chip giant have indicated that Intel might have something new up its sleeves.

Uncertain environment at Intel

Intel became the world’s largest semiconductor maker after developing a partnership with Microsoft, and together the two companies have dominated the PC industry for 25 years. But 2013 is proving to be treacherous for the PC industry. The previous IHS forecast predicted global PC shipments would rise by 3.4 percent in 2013. However, given the dismal results in the first quarter, it appears that shipments are unlikely to achieve growth for the year. IHS downgraded its forecast for worldwide PC shipments to be flat at best, but the market is more likely to suffer a 1 percent to 2 percent decline. This follows a dismal 2012, when global PC shipments decreased by 3.3 percent, the first decline in 12 years.

“The PC Industry is facing major challenges as it struggles to find a place in the consumer’s budget amid the rising popularity of the lower-priced media tablet,” said Craig Stice, senior principal analyst for compute platforms at IHS. “Windows 8 has yet to trigger a new PC replacement cycle. While there have been many new product introductions intended to revitalize the market, like the ultrathin mobile PCs and convertibles with touch screens, it seems consumers have yet to discover the return on investment for these higher-priced systems.”

For the most part, Intel reacted with great agility to weakening demand for its products, cutting down its inventories very rapidly in the fourth quarter of 2012 to avoid being stuck with excess stockpiles, according to IHS. The company in the fourth quarter was the most aggressive of all semiconductor suppliers in reducing its inventories, cutting them by 11 percent, or $585 million, compared to the third quarter of 2012—the largest decrease on a dollar basis of any chipmaker during the quarter. Intel’s inventory liquidation partly was due to a reduction in production as the company migrated to a new process technology for manufacturing its chips: 14nm lithography.

Sales of netbooks, a product Intel dominated with its Atom family of low-end processors, have been badly impacted by the downturn in the PC market as well as the growth in the media tablet.  Netbook shipments this year are forecast to amount to just 3.97 million units, down a gut-wrenching 72 percent from 14.1 million units in 2012.

The demand for Intel’s other big source of revenue, chips for computer servers, is evolving, too. Basic servers are relying more and more on cloud computing, creating opportunities for new competitors to develop cheaper designs as the simpler method drives down prices (and, ultimately and unfortunately, profit margins).

Mobile devices and an unexpected move: The surprising bet that could save Intel

Despite Intel’s travails, IHS says the company is expected to continue to maintain its leadership in the global semiconductor market at least through 2013. However, Intel is betting on investments in the mobile market and, surprisingly, pay-TV to carry it even further than that.

According to the New York Times, Intel had been criticized for its lethargic reaction to the rise in the mobile market. Intel in 2012 held a 5 percent share of the market for digital baseband and applications processors used in mobile phones and other mobile devices. Intel is pushing to expand this product line this year. Aside from its legacy Infineon business, Intel had seen some design win activity from its Atom product line in smartphones from Lenovo, Motorola and various Chinese brand OEMs. Furthermore, Intel has introduced its LTE platform.

“IHS expects Intel to continue to attempt to build off these early wins and ramp penetration in the mobile platform market—specifically in smartphones,” said Francis Sideco, senior director for consumer electronics and communications technologies at IHS. “However, even if Intel is successful in this area in 2013, it won’t enjoy rapid growth, but rather slow and steady progress. The company faces significant challenges because of the momentum and positioning of strong incumbents such as Qualcomm, which holds a market share in the mobile-phone semiconductor business that is currently seven times larger than Intel’s.”

However, its greatest departure is its plans for selling a television set-top box and subscription service, which Intel officials say will offer enough regular television content to serve as a substitute for a cable subscription. Variety magazine’s Andrew Wallenstein recently spoke with Erik Huggers, head of Intel Media, the company’s most secretive division, to get the inside scoop on what Intel plans to offer.  Huggers didn’t reveal much to Wallenstein, but here’s what we know:

  • Intel intends to allow subscribers to purchase a package of broadcast and cable channels that will be supplemented by various VOD options. The package will also be available across mobile devices.
  • Intel will not be offering a la carte channels. The programming partners (such as Time Warner, News Corp., Disney, Viacom, etc.) will never go for that. But Intel has also hinted there might be more flexibility in the bundles of channels offered, as opposed to what consumers get with basic cable.
  • Intel has also made clear that its new device is not expected to come in at a lower price point than most other pay-TV services. Instead, what will make Intel’s device unique is a user experience that is “touted as a quantum leap over the traditional multichannel set-ups that have been rendered anachronistic by innovators like Apple and Netflix.”
  • Intel has confirmed that the device will come with a camera that will recognize which viewer in a household is watching so as to personalize the programming (and presumably advertising) to individual tastes. But don’t worry, the company made clear the feature can be turned off.

New Intel leadership could also play a role in its reinvention

And in the midst of the chaotic and uncertain technological revolution, Intel is also scrambling to find a new leader. In November, Paul Otellini, who had been CEO since 2005, caught everyone off guard when he announced his resignation, saying that it is time to transfer Intel’s helm to a new generation of leadership. Otellini declined to provide further information on why he was leaving just three years short of retirement age.

While Intel has yet to indicate a main candidate for the role, Chairman Andy Bryant may offer insight into what Intel is looking for. The New York Times reported that Bryant tells employees at meetings that Intel must fundamentally change, even if the computer chip maker still has what it takes to succeed in engineering and manufacturing.

The fast growing market for sensors for smart phones is re-shuffling the ranks of MEMS suppliers. For the first time, suppliers of inertial sensors have surpassed the major makers of micro mirrors and inkjet heads that have long dominated the industry on Yole Développement’s annual ranking of the Top 30 MEMS companies.

 top 30 MEMS suppliers

STMicroelectronics increased MEMS sales by ~10 percent in 2012, to become the first company with $1 billion in MEMS revenue, moving past Texas Instruments to become the sector’s largest company. Robert Bosch saw 14 percent growth, to ~$842 million in MEMS sales, pushing ahead of both Texas Instruments and Hewlett Packard for the first time to become the second ranking player, according to Yole’s figures. Both ST and Bosch have been aggressively expanding their consumer product lines to offer customers a broad range of sensors, and increasingly also combinations of sensors in a single package for easier integration at lower cost. Their growing volumes also help keep their fabs running more efficiently, for the assured manufacturing capability that volume users demand.  ST, Bosch and other major inertial sensor suppliers saw strong revenue growth despite the 20 percent-30 percent drop in average selling prices for accelerometers and gyroscopes over the year–because of even bigger ramps in unit volume.

“ST increased unit production by 58 percent, to 1.3 billion MEMS devices in 2012, up to some 4 million units a day—not counting its foundry business,” notes Yole Market & Technology Analyst, Laurent Robin. “It’s hard for many companies to match that.”

Yole calculates the MEMS industry overall saw another ~10 percent growth in 2012 to become an ~$11 billion business– in a year when the semiconductor industry saw a ~2 percent decline. The Top 30 companies account for nearly 75 percent of that total MEMS market.

The traditional gap between the big four MEMS makers and the rest of the pack narrowed this year, as strong demand for more MEMS sensors in both consumer and automotive markets drove strong growth across a range of suppliers. Knowles Electronics saw better than 20 percent growth to climb into fourth place with some $440 million in revenues from MEMS microphones, closing in on HP. Panasonic and Denso were close behind with more than $350 million in MEMS sales in their largely automotive markets.

Mobile phones and tablets were the real sweet spot for big growth opportunities, though. Chinese electret microphone supplier AAC made the top companies ranking for the first time as its MEMS microphone sales jumped ~90 percent to ~$65 million, as it became the second source for the iPhone. InvenSense saw some 30 percent growth as it ramped up production of its inertial sensors. Triquint saw a 27% increase in revenues from its BAW filters.

Murata moved sharply up the ranking as its acquisition of VTI created ~$179 million in combined MEMS revenue.

Meanwhile, the traditional major MEMS markets for micromirrors and inkjet heads have matured and slowed, with demand for inkjet heads particularly hit by the consumer printer market’s rapid turn away from replaceable heads to page-wide and fixed-head technologies. That hit revenues at both the inkjet companies and their manufacturing partners.

Yole defines MEMS as three dimensional structures made by semiconductor-like processes, with primarily mechanical, not electronic, function. We also include magnetometers, as they are now so closely integrated with MEMS inertial sensors, and all microfluidics, including those on polymer. Yole figured MEMS units and value at the first level of packaged device. For companies that do not release MEMS revenues, Yole estimate the figures based on data for product market size, market share, product teardowns, reverse costing, and discussions with the companies.

IBM announced plans on Thursday to invest $1 billion in flash memory research and development and launch a series of systems that will use solid state drives.

solid state drives and flash memory IBM

At an event in New York, IBM’s Steve Mills, head of IBM’s software and systems division, said Flash is at a key tipping point and IT will see all-solid state data centers sooner than later. 

Corporate servers have struggled to keep up with the substantial growth in data use from smartphones and tablets. IBM believes there is a solution in flash memory, which is faster, more reliable, and uses less power than a traditional hard disk drive. The $1 billion investment will be put to use in research and development to design, create and integrate new flash-based products in its expanding portfolio of servers, storage systems and middleware.

"The economics and performance of flash are at a point where the technology can have a revolutionary impact on enterprises, especially for transaction-intensive applications," said Ambuj Goyal, IBM’s general manager of systems storage. "The confluence of Big Data, social, mobile and cloud technologies is creating an environment in the enterprise that demands faster, more efficient, access to business insights, and flash can provide that access quickly."

IBM also announced the availability of the FlashSystem line of all-flash storage appliances. Sprint Nextel will be installing nine of these storage systems at its data center, becoming one of the first companies to adopt IBM’s flash-based model.

As part of its commitment to flash development, IBM said it plans to open 12 Centers of Competency around the globe, which will allow customers to run proof-of-concept scenarios with real-world data to measure the projected performance gains that can be achieved with IBM flash products.

"Clients will see first-hand how IBM flash solutions can provide real-time decision support for operational information, and help improve the performance of mission-critical workloads, such as credit card processing, stock exchange transactions, manufacturing and order processing systems," IBM said in a news release.