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November 15, 2012 – The LCD TV panel sector closes 2012 with continued tightness due to new process technologies, capacity conversions, a strong market in China, and growing panel sizes. A number of new sizes (39, 50, 58, 60, and 65-in.) enjoyed success and some broke into the mainstream with wide adoption and volume growth.

Looking ahead to 2013, a number of established LCD panel sizes (26, 32, 37, 40-42, 46-47, and 55-in.) will give way to new sizes as TV brands adjust their product mix, calculates NPD DisplaySearch. In a new report, the analyst firm looks at everyone’s 2013 LCD TV panel product mix, and found some big differences between what suppliers offer and what buyers want:

2013 plans for LCD TV set and panel size mix. (Source:
NPD DisplaySearch Quarterly LCD TV Value Chain Report)

While panel makers want to maximize the efficiency of each fab-generation panel size, TV brands are focused on maximizing their market share and revenue. "As panel makers aggressively expand into new sizes, the mismatch is growing more serious," notes Deborah Yang, research director for monitor & TV at DisplaySearch. When the market tightens and push comes to shove, "the push from panel makers is usually stronger than the pull from LCD TV brands," she writes, and "many LCD TV brands will have to adjust their product mixes accordingly.

Here’s her rundown of factors driving that push-pull and how it’ll shake out:

  • Get bigger faster: Panel makers eager to maintain high capacity utilizations (and thus value) have been racing to adopt larger sizes than the TV brands, especially for the biggest sizes (46-60-in. and above).

  • Make bigger cheaper: The very low priced 60-in. set "has changed the ecosystem," Yang writes. Some Chinese TV brands have introduced 58-in. sets to compete with it, while Korea’s Samsung and LG Display are churning out more 60-in. product to compete with Sharp and Vizio. Gen-8 panels are not optimized for that particular size, though, so panel makers are moving to "multi-model glass" from which they can make 60-in and 32-in panels on the same substrate.

  • A shift in smaller panels: Almost everyone (Taiwan, Japan, Korea suppliers) plan to reduce their 32-in. production, which will open the door for Chinese panel makers to grab design wins with international brands.

  • Give a little extra:Most TV brands selling 46/47-in. panels (Panasonic, Philips, Samsung, Sony, Toshiba, Vizio, LG Electronics, and Chinese brands), anticipating a replacement cycle to bigger 50-in. panels, are now adding 50-in. panels.

  • Plug a midsize shortage: A lack of Gen 7 capacity, especially in China, is creating a shortage of 40/42-in. panels. AUO, LG Display, and Chi-Mei Innolux are planning to ramp up 42-in. production in their Gen-8 lines.

  • Move on up: Samsung can add every new size to its product line; Toshiba recently shifted from current mainstream sizes (40, 46, and 55-in.) to new sizes (39, 50, and 58-in.). Sony is considering 42-in. and 39-in. to avoid concentrating too much on 40-in. TV brands in China are coping with a complicated Chinese TV market in which Chinese consumers tend to prefer new products.

by Paul Feeney, Axus Technology

The International Conference on Planarization/CMP Technology (ICPT) was held Oct 15-17 in Grenoble in southern France. This international event is the world’s largest conference covering chemical mechanical planarization (CMP) and related topics, over a 2.5 day period. Over time, the CMP users groups from around the world that come together to form this event are acting increasingly as one body, and the quality of the information has risen.

ICPT oral and poster presentations can be grouped into a handful of major themes:

  • Integration of new device structures, and the CMP processes and slurries needed to support them;
  • Advances in equipment and in endpoint and control methods;
  • Advanced copper interconnects, and the extension of this to 3D and MEMS technologies;
  • Consumables, with a keen focus on mechanistic understanding; and
  • Alternative planarization methods and the application of CMP to new materials.

CMP and new device structures

Leading off the discussion of the application of CMP for new devices was a plenary talk by Daniel-Camille Bensahel from CEA-Leti. He stressed the parallel paths that exist today for 14nm technology and beyond between fully depleted silicon-on-insulator (FD-SOI) and multi-gate or FinFET devices. As technology goes beyond these two architectures, the future will lie in making the transition from silicon channels to some combination of germanium, nanowires, and graphene. All of this bolsters the effect we have already seen putting more focus on the use of planarization in creating devices rather than solely in making interconnects.

Invited talks from IMEC and GlobalFoundries nicely covered the complexity of CMP steps now being employed to fabricate leading-edge devices. In years past, shallow trench isolation (STI) CMP was the only set of CMP steps in the front-end-of-line (FEOL) process flow. Now, many new CMP applications are being added and each calls for multiple process steps. The special dielectric fill for FinFET’s creates the need for steps very similar to those used for STI, but drives the need for stopping on the extremely small nitride features that cover the fins. The ILD 0 or pre-metal dielectric or poly-open-polish (POP) CMP that exposes the tops of the dummy silicon for metal gates also has similarities to these two. The metal gate CMP that follows was discussed as being implemented with either aluminum (Al) or tungsten (W) as the bulk material. There was also coverage of techniques similar to those of replacement gates for formation of replacement channel materials made from germanium (Ge), indium phosphide (InP), or indium gallium arsenide (InGaAs).

Papers that delved into a portion of these new CMP applications pointed out some of the unique challenges. Catherine Euvrard from CEA-Leti pointed out that POP CMP must not only retain tight control over remaining film thickness, but must do so while simultaneous removing nitride and oxide materials deposited at slightly different heights due to the non-planarity remaining after STI. Another difficulty is that the pattern removal rates of nitride and oxide do not follow what might be expected from blanket rates on each of the films when polished separately. Patrick Ong from IMEC went into the development of a 2-step process for replacement Ge channels. The epitaxial overgrowth of Ge is polished back to oxide and then buffed to produce roughness in the range of 2Å. Ulrich Kuenzelmann from TU Dresden showed results from their implementation of Al CMP. These papers were all geared towards advanced logic. Hynix also contributed with talks on new ceria particles for lower defectivity in STI and CMP for buried gates or wordlines for advanced memory. For buried wordline CMP, the bulk metal includes W and must stop on a nitride layer.

CMP equipment, materials, and methods

On the second theme of equipment, a variety of new hardware and control options were highlighted. Len Borucki from Araca pointed out the slurry flow reduction or oxide removal rate gain with a “slurry injector” apparatus. A second talk from Araca described similarities and differences seen in doing CMP of 300mm vs. 450mm wafers. Polishing of 450mm wafers can generate temperatures a few &degC higher, which is likely to have a noticeable effect on temperature sensitive steps such as Cu CMP. Pusan National University and G&P Technology showed that they were able to achieve a radial non-uniformity (NU) of 3% at 2mm edge exclusion with their wafer carrier that contains an “edge profile ring” between the wafer and the retaining ring.

A number of papers described ideas for metrology. Applied Materials and a few customers covered the application of white light illumination for endpoint control across a range of FEOL CMP applications. Improved results were presented for STI thickness, POP thickness with closed loop control of both profile and polishing time, as well as establishment of endpoint control of a process for replacement SiGe channels. Silvio Del Monaco from STMicroelectronics displayed a technique for in-situ measurement of pad groove depth that could be used in characterizing the pad cutting rate of conditioner disks. Florent Dettoni from CEA-Leti described a technique they developed to stitch together interferometric scans to create accurate maps of topography both for whole dies as well as across wafers. Those results were correlated to profilometer scan data, but measurements can be done much quicker. Chandar Palamadai laid out the process that KLA-Tencor has created for quantification of scratching through analysis of blanket wafer haze maps.

CMP and Cu interconnects

The next major theme regarding copper (Cu) included advanced interconnects both for wafers as well as quite a bit on 3D interconnects. Olivier Robin from STMicroelectronics taught us how sheet resistance control mean and variation can be improved by switching to a barrier process with higher selectivity between the dual hardmask and the dense ultralow-k material just below them. Jie Lin from Fujimi described work to develop a slurry for Cu that can get good planarization efficiency despite being used with a pad of moderate hardness. Contributors from Fudan University and from DuPont covered work studying the corrosion and removal rate behavior of the cobalt and molybdenum materials being investigated as part of new barrier material stacks.

ICPT has given increased attention to 3D interconnects and the formation of through-silicon-vias (TSVs) over the last few years. This year included an overview by Viorel Balan from CEA-Leti of some of the issues that need to be addressed in order to do Cu-to-Cu direct bonding. A key to success was identifying and improving topography across several length scales. Both he and Benjamin Steible from ISIT gave evidence that new generations of abrasive-free slurries provide a nice advantage in controlling the dishing of especially larger structures. Jinhai Xu talked about his work at SMIC demonstrating that rings of corrosion at the edges of vias can be seen as a recessed area when there is still about a micron of bulk copper left on the wafer. Rob Rhoades showed two different processes for the TSV nail expose process depending on whether it is an active wafer or an interposer. Catharina Rudolph from Fraunhofer presented a story showing that the combination of high-density TSVs and a higher-temperature anneal actually leads to enough stress that the wafer can explode.

CMP consumables

Over time, consumables for CMP have become more specialized to fit the needs of individual process steps for each application. Consumable topics have always been a popular topic at ICPT and this year was no exception. In the area of pad conditioning, there were two topics that received the most attention. One was applying conditioning techniques to the double-sided polishers used in wafer polishing. Jorn Kanzow from Peter Wolters reported that conditioning provided edge control for the double-sided polishing that is now necessary for achieving flatness for 300mm wafers. The second was the study of pad debris that is generated during pad conditioning and how it leads to an increase in scratch defects. Scratching was shown to be best when doing excitu conditioning or when vacuuming the debris off the pad. A relatively recent style of conditioner uses diamond coating over an engineered surface. 3M presented a summary of their efforts to do that utilizing some of their micro-replication methods.

Keiichi Kimura from Kyushu Institute of Technology presented some very exciting concepts surrounding research done to identify individual removal events during CMP. Through the use of evanescent light, where laser light is bounced off a prism surface, individual slurry particles that come in contact with the prism are illuminated. Their findings put forth the idea that pad asperities and the fluid around them cause adhered particles to be pulled off the polished surface. This happens at velocities much slower than what the pad achieves across the wafer — which rebukes a standard theory that removal is from 3-body contact of a pad asperity pushing a slurry particle into the film being polished. Greg Gaudet from Cabot Microelectronics provided an argument for removal rate with softer pads being driven more by the number of contact points between the pad and wafer rather than the total area of contact. This data seems to back up the concepts presented by Kimura.

For slurries, Intel together with Bradley University and MIT had a few talks outlining the outcome of fundamental studies. Alex Tregub made the point that the characterization of particle size is often overly simplified into a mono-modal distribution. Those tests also often use highly diluted slurry that may not be behaving as it would in its normal state. Mansour Moinpour went over results showing how desorption of additives from particle surfaces can be characterized. Joy Johnson from MIT reviewed a collection of literature surrounding particle agglomeration and added some work showing the role additives can play in agglomerate formation. Along somewhat similar lines, Pall got together with Lewis University to characterize the interaction that slurry particles have with the fibers inside of slurry filters, which may lead someday to the use of novel fibers.

New and improved CMP materials, processes

The remaining major theme is the extension of CMP to new materials and other types of removal processes besides CMP that are also being improved upon. Talks covered new materials such as carbon nanotubes with titanium (Ti) for vias, potassium dihydrogen phosphate (KDP) crystals for optics, GST for phase change memory, SiC for hardmask removal, and Ti and Ti02 for biomedical applications. It turns out that lowering surface roughness of Ti02 improves the biocompatibility of surgically implanted materials.

Though there does not appear to be any technology that is threatening the continued adoption of CMP for many applications, there are also other types of processes that have their place. Hyuk-Min Kim from Hanyang University taught us how lapping results could be improved by switching to a fixed abrasive system. Chuljin Park from KIIT showed a multistep process where diamond mechanical polishing was useful followed by CMP for sapphire substrates. Paul Feeney from Axus Technology demonstrated that improvements in grinding technology can make the CMP of Si after grinding much easier and produce better results. Grinding of Si can be done two-orders-of-magnitude faster than CMP and with within wafer non-uniformity unheard of in CMP. Adding CMP afterwards then produces the best possible surface.

Overall, the technical content of this event was very good. Clearly a lot of energy is being applied around the world to make advances on a wide variety of planarization applications. A high bar has been set for next year’s ICPT in Taiwan!

Paul Feeney ([email protected]) is director of process technology at polishing and thinning company Axus Technology. He started his involvement in CMP at IBM in 1989, holding both process and equipment responsibilities there, including doing pioneering module process and integration work on copper and barrier CMP for the world’s first commercial copper chips. He spent many years at Cabot Microelectronics; as a CMP Fellow there, he led development of a wide range of materials for leading-edge CMP applications. He is also a co-leader for planarization topics for the ITRS.

by Paula Doe, SEMI Emerging Markets

Materials experts from across the supply chain who gathered at the Strategic Materials Conference 2012 in San Jose in October discussed key materials needs for micromanufacturing outside the CMOS mainstream, as OLEDs and GaN-on-silicon power semiconductors come to market, and alternatives like graphene, CNTs, and self-assembling polymers get closer to commercial application.

Large OLED displays are coming, and counting on materials breakthroughs

OLED adoption in larger displays is surely coming, driven by business necessity, argued James Dietz of Plextronics. Most of the major display makers are seeing operating losses from their LCD business, and OLEDs look like the best option for higher-value, differentiated products to improve margins. The OLED displays look significantly better, and they may potentially open new markets for lighter or flexible or more rugged displays, or for dual-view products. OLEDs’ ultra-fast switching speeds could allow different viewers with different glasses to watch different programs at the same time on the same screen. Moreover, though OLEDs are more expensive now, the variable costs for a 55-in. OLED TV made on an 8G line will be quite comparable to those for a similar LCD. And the OLED costs have far more potential to come down further, by developments like simplifying the layer stack and introducing wet processes that use lower cost equipment with higher utilization of the expensive materials.

But the nature of the market also means new challenges for suppliers. Anxious to avoid another experience like the commoditization of the LCD sector, display makers intend to keep their processes and complex OLEDs materials stacks to themselves this time, which makes process integration of different materials and equipment difficult. The device makers are investing in developing their own materials, making exclusive contracts with equipment and materials suppliers, and doing their own process integration. Integration is also being driven by some materials suppliers like DuPont Displays. But the familiar semiconductor model of the material and tool supplier working together to deliver a process to the customer is not the rule. "We see a gradual transition from all vapor to more solution layers," says Dietz. "OLEDs will enter the TV market in the next three years, and will have solution process steps by 2015."

The 55-in. OLED TVs announced for 2012 now look more likely to come out in only very small volume — a few thousand units in 2012 — and initial prices of ~$9000 will limit sales. But OLED TVs will start to see real growth by 2014-2015, helping to push OLED displays to a $25 billion market by 2017, reports Jennifer Colegrove, VP of emerging display technology at NPD DisplaySearch. She says ten new AMOLED fabs are planned to be built or updated in the next three years. OLED materials, now about a ~$350 million market (include the OLED organic materials but not substrates), should grow at close to the same 40% CAGR of the overall market, to reach $1-2 billion in 2014. But breakthroughs are still needed in oxide and amorphous silicon backplanes, color patterning technology, lifetime of blue materials, encapsulation materials, reduction of materials usage, and of course integration, uniformity and yields of all these things.

OLED display revenues will grow to about $35B in 2019, up from $4B in 2011, with CAGR ~40%. (Source: NPD DisplaySearch, Q3’12 Quarterly OLED Shipment and Forecast Report)

Solution processing is critically important to bringing down the cost of large screen OLEDs, argued John Richard, president, DuPont Displays, as the current production methods which rely on thermal evaporation with fine metal masks are proving costly to scale to 8G substrates. "We developed an alternative process using soluable materials to bring down cost," he notes. Wet processes reduce capital needs and cut material waste to reduce costs significantly, but still need ever better lifetimes and efficiencies of the OLED materials, particularly for blue. A major Asian display maker has licensed the DuPont technology, and plans to scale it up to 8G. The process uses largely pre-existing tools to slot coat the hole injection and transport layers, and pattern the surface with wetting and non-wetting lanes, before nozzle printing stripes of red, green and blue emitters using custom tool developed with Dai Nippon Screen.

The rest of the stack — the electron transfer layer, the electron injection layer, and the metal cathode — is then deposited by thermal evaporation. Richard says coating and printing processes can use significantly less material than vapor deposition, as it avoids losses in the chamber, on the mask, and during alignment and idling. DuPont reports printed blue emitter lifetime is up to 30,000 hours — or 8 hours a day of video for 15 years — before degrading to half brightness. Next issues include optimizing the cost of synthesis and starting materials, and reducing operating voltage for better device efficiency.

Graphene and carbon nanotubes get closer to commercial applications

Next-generation energy storage presents materials opportunities as well. One key enabler for improving both supercapacitors and batteries could be graphene, especially with better sources for consistent quality material at reasonable cost. Bor Jang, CEO of Angstron Materials, reported that his company has engaged a contract manufacturer in Asia to start volume production of as much as 30 tons of graphene next year, using Angstron’s technology that claims good control of structure and properties. "That will bring down costs by an order of magnitude," says Jang. First application will likely be performance enhancers for lithium-ion battery electrode materials, and then for improved electrodes for supercapacitors. Angstron has announced demonstration of a graphene-based supercapacitor with energy density comparable to a nickel hydride battery.

"We think supercapacitors is a market to invest in," said Chris Erickson, general partner at Pangaea Ventures, a somewhat unusual venture fund that invests particularly in materials and green technologies. "We think it will reach $1 billion in the near future." Erickson is also enthusiastic about the potential for dynamic window glazing using vapor-deposited coatings and ITO to adjust to control the shading on windows, for dramatic energy savings of up to 30% in energy consumption in a building, according to NREL — and buildings reportedly use 49% of total energy in the US.

Nantero reported major progress from its long effort in controlled processing and performance for its carbon nanotube thin film, targeting low-cost, low-power non-volatile memory. CTO and co-founder Thomas Reuckes said the company is now lithographically patterning films of its spin-coated aqueous solution of carbon nanotubes, as roughness, adhesion and defectivity are now suitable for semiconductor processing. Metal impurities are down to <1ppb in liquid form, wafer-level trace metals to <1E11 atoms/cm2 . Reuckes reported production of working and yielding 4Mbit CNT memory arrays, and showed results of reliability data. The company just announced a joint development program with imec to manufacture, test, and characterize the CNT memory arrays in imec’s facilities for applications in next generation <20nm memories.

GaN for power semiconductors needs higher purities than LED market

Power semiconductors made on GaN on silicon are being released to the market now, and, given time, could potentially address some 90% of the what IMS Research projects will be a $25 billion (silicon-based) power semiconductor market for MOSFET and IBGTs by 2016, suggested Tim McDonald, VP for emerging technologies at International Rectifier Corp. GaN theoretically offers much better specific on-resistance to breakdown voltage tradeoff than Si or SiC. The key to wide adoption is for GaN on Si based solutions to achieve 2-4× performance/cost compared to silicon.

To achieve the necessary low costs, IR uses compositionally graded layers of AlyGaxN grown on the silicon to ease the thermal and lattice mismatch of the GaN film to the silicon wafer. IR claims 80% yields, with warp and bow controlled enough to run on a standard 150mm CMOS line. GaN on silicon is moving more quickly to market for power semiconductors than for LEDs, as it brings better performance, not just potentially lower prices. It also helps that threading defects do not have the same impact on performance–plus IR has been developing the technology for six or seven years already.

The power market needs higher purity materials and cleaner tools for better yields on its larger die, compared to the LED market. It also prefers larger diameter wafers for lower costs. Demand for gas sources and MOCVD tools should scale with volume, and the tools need to be optimized for larger wafers and become more automated, with perhaps some 2,000-3,000 tools needed for the whole market over the next two decades. Packaging may move from wire bonding to soldered or sintered contacts, and will adopt other means of reducing stray packaging-related inductance and resistance.

The LED market will see only a few more years of significant growth, argued Jamie Fox, lighting and LEDs manager for IMS Research-IHS. Revenues from displays including TVs are leveling off from their fast ramp, as the markets mature, and as LEDs get both brighter and cheaper, driving down both units needed and cost per unit. The LED lighting market will continue its fast climb to near ~$6 billion over the next several years, but then as more lamp sockets are replaced by the longer lasting LEDs (and CFLs), there will be less need for replacements, and the market will slow. Slower adoption near term, however, would mean less saturation later.

Cree’s Mike Watson, senior director of marketing and product applications, countered by pointing out the potential for innovation that solid state technology brings to lighting, noting how digital technology has transformed markets like telephones and cameras into new industries for digital communications and digital imaging. "Semiconductor technology keeps changing industries by innovation," he noted. "Why do we keep thinking of it as just replacement?

Directed self-assembly for higher resolution lines and holes

Another of the more innovative materials alternatives on the CMOS side is directed self-assembly for next-generation patterning, which seems to be making rapid progress. AZ Electronic Materials CTO Ralph Dammel reported that block copolymers, with similar molecules together in blocks instead of randomly dispersed, tended to arrange themselves with the similar chain sections together, conveniently lining up into cylinders that look similar to lithographic contact holes, or into lines similar to lithographic lines and spaces. Wafer surface patterning with topography or chemicals can control the placement of these self-assembled patterns, on top of standard 193nm immersion lithography. Work with IBM Almaden suggests the process can provide better CD uniformity for quadruple patterning at lower cost than the spacer pitch division process. Other work shrinks contact holes, while improving the CD variation compared to the resist prepatterns. The company is now providing large-scale samples for in-fab process learning, with implementation perhaps as early as 2014, though design for self-assembly needs further development work.

November 8, 2012 – Growing use of disposable devices and respiratory monitoring are underpinning growing use of microelectromechanical systems (MEMS) used as pressure sensors in medical electronics, according to IHS iSuppli.

Medical electronics is a relatively small slice of the overall market for MEMS pressure sensors. Sales of such devices are seen rising 6%-7% this year to $137.6M, with steady growth continuing through 2016. But they’re in the "high-value" category where suppliers can command much higher average selling prices, so it’s a more profitable and attractive market, points out Richard Dixon, principal analyst for MEMS & sensors at IHS. (Another high-value MEMS category, industrial and military/aerospace, will rake in about $283M this year.)

Worldwide high-value MEMS pressure sensor revenue forecast, in US $M. (Source: IHS iSuppli)

Pressure sensors are poised to become the leading type of MEMS device, generating $1.5B in revenue. In medical applications the technology is found in accurate low-pressure measurement devices. They are particularly seen as a low-cost consumable for invasive applications such as the monitoring of blood pressure. The most common medical pressure sensor is the disposable catheter to monitor blood pressure and micro vascular resistance in the vicinity of the heart. Another type of disposable (and low-cost) MEMS pressure sensor is the infusion pump, used to introduce fluids, medication, or nutrients into a patient’s circulatory system — 60M units of these devices were shipped in 2011.

MEMS pressure sensors also have use in non-invasive applications where they are reusable and cost considerably more. The biggest category in this segment is respiratory monitoring, such as the Continuous Positive Air Pressure (CPAP), used mainly to treat sleep apnea at home. (The US is the main market for such devices, since the treatment is included in healthcare programs, iSuppli notes.) Another application is in oxygen therapy machines, incorporating both a low-pressure and high-pressure sensor, to administer or increase the amount of oxygen in a patient’s blood. This application is growing given the aging population and increase in chronic obstructive pulmonary disease. Another respiratory-use market, though currently small, is in ventilators to treat lung injuries, asthma, and adult or acute respiratory distress syndrome.

Yet another medical market for MEMS pressure sensors is in measuring vital signs: benchtop or mounted-central-station patient monitors, and multiparameter monitoring devices. Low-end instruments include at least one non-invasive pressure sensor; midrange counterparts comprise one or two such devices, and high-end devices have both non-invasive and invasive pressure sensing, as well as additional respiratory pressure sensing.

One market "in its infancy today" but with high promise is implantable devices such as cardiac monitors, glaucoma monitors, and cranial pressure monitors, iSuppli notes. With a cardiac sensor a patient can be monitored from his/her home, eliminating repeat hospital visits for tests — which would realize huge savings in healthcare costs.

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November 8, 2012 – Researchers from IBM and Georgia Tech have disclosed significant progress in manipulating carbon nanotubes in transistors and interconnects, in ways compatible with traditional fabrication techniques, advancing toward using the materials for next-generation devices.

Connecting nanotubes to semiconducting substrate

Researchers from Georgia Tech say they have achieved a first: connecting multiple shells of a multiwalled carbon nanotube (MWCNT) to a semiconducting substrate without the high interface resistance produced by traditional fabrication technique — showing a way, they say, to facilitate integration of CNTs as interconnects in next-generation circuitry using both silicon and carbon components.

The work, reported online by the journal IEEE Transactions on Nanotechnology, uses electron beam-induced deposition (EBID), develops graphitic nanojoints on both ends of the MWCNTs, yielding a 10-fold decrease in resistivity in the connection to metal junctions. The technique "is amenable to integration with conventional integrated circuit microfabrication processes," explained prof. Andrei Fedorov. "Connecting to multiple shells allows us to dramatically reduce the resistance and move to the next level of device performance."

The low-temperature EBID process takes place in a scanning electron microscope (SEM) modified for material deposition — the vacuum chamber is altered to introduce materials precursors and the electron gun generates low-energy secondary electrons when the high-energy primary electrons impinge on the substrate at specific locations. When the secondary electrons interact with hydrocarbon precursor molecules, carbon is deposited with a strong, chemically-bonded connection to the ends of the carbon nanotubes, unlike the weakly-coupled physical interface made in traditional techniques based on metal evaporation, the researchers say. Prior to deposition, the ends of the nanotubes are etched opened so the deposited carbon grows into the open end of the nanotube to electronically connect multiple shells. Thermal annealing of the carbon after deposition converts it to a crystalline graphitic form that significantly improves electrical conductivity.

"Atom-by-atom, we can build the connection where the electron beam strikes right near the open end of the carbon nanotubes," Fedorov explained. "The highest rate of deposition occurs where the concentration of precursor is high and there are a lot of secondary electrons. This provides a nanoscale sculpturing tool with three-dimensional control for connecting the open ends of carbon nanotubes on any desired substrate."

The technique produces record low resistivity at the connection between the carbon nanotube and the metal pad — the researchers have measured resistance as low as ~100 Ohms, a factor of ten lower than the best that had been measured with other connection techniques.

This is still very early work, though. The researchers don’t know exactly how many of the CNT shells are connected (they think at least 10 out of 30 "are contributing to electrical conduction). And converting the birds’ nest of tangled CNTs of different lengths, properties and defectivity into a pattern for reliable interconnects is a challenge. The team says it has developed a method to align the MWCNTs across electrical contacts using focused electrical fields in combination with a substrate template created through electron beam lithography, which has "significantly improved yield of properly aligned carbon nanotubes." But much work needs to be done to improve CNT alignment, and perfect EBID systems to deposit connectors on multiple devices simultaneously (parallel electron beam systems might help here).

"A major amount of work remains to be done in this area, but we believe this is possible if industry becomes interested," Federov said. "This is really a critical step for making many different kinds of devices using carbon nanotubes or graphene."

 


Two SEM images showing a carbon nanotube interconnect done with the EBID process.
(Source: Georgia Tech)

Precisely placed, high-density CNT transistors

IBM, meanwhile, says it’s made a leap toward viability of carbon nanotube (CNT) transistors, by precisely placing and testing thousands of CNTs in a single chip using standard semiconductor processes.

The ability to isolate semiconducting nanotubes and precisely place them in high density on predetermined positions on a wafer is critical to assessing their suitability. So far scientists have only placed a few hundred CNT devices at a time, not enough to assess key issues for commercial application — and far below the millions or even billions of transistors eventually needed for future chips.

Earlier this year IBM showed a sub-10 nm CNT transistor showing 5-10× better performance than silicon circuits. The group’s newest work, detailed in the journal Nature Nanotechnology, describes an ion-exchange chemistry that allows precise, controlled placement of aligned carbon nanotubes on a substrate, with a high density (109/cm2) that’s 2 orders-of-magnitude greater than previous experiments.

The process involves mixing the CNTs with a surfactant to make them soluble in water. A substrate with trenches of chemically-modified HfO2 (and SiO2 everywhere else) is immersed in the solution, and the CNTs attach via chemical bond to the HfO2 regions; the rest of the surface remains clean. The new placement technique can be readily implemented since it involves common chemicals and existing semiconductor fabrication, IBM says, and compatibility with standard commercial processes also means rapid testing with high-volume characterization tools.

Carbon nanotubes "have largely been laboratory curiosities as far as microelectronic applications are concerned," acknowledged Supratik Guha, director of physical sciences at IBM Research. This new IBM work makes "significant strides" in solving two key challenges of ultrahigh-purity CNTs and their deliberate nanoscale placement, and thus represents "the first steps towards a technology by fabricating carbon nanotube transistors within a conventional wafer fabrication infrastructure."

SEM image of carbon nanotubes deposited on a trench coated in hafnium oxide (HfO2) showing extremely high density and excellent selectivity. Scale bar: 2μm. (Credit: IBM)

November 7, 2012 – Deca Technologies has introduced a new chip-scale packaging (CSP) product line offering a rugged, fully molded packaging technology in ball-grid array (BGA) style formats that eliminate the need for laminate substrates.

A year ago Deca launched its inaugural wafer-level chip-scale packaging (WLCSP) technology "derivatives," developed with help from solar tech firm SunPower, promising a combination of speed, low cost, and flexibility. Much of the technology behind its work, though, was customized and deeply proprietary, with few details made available.

Nonetheless, industry response to the WLCSP offering "has been very strong," with multiple customers now in production and many more undergoing qualification, claims Tim Olson, Deca president/CEO.

The company’s new M-Series CSP line, geared for applications where the WLCSP option isn’t a good fit, features an "Adaptive Patterning" design/patterning process that allows features such as vias and redistribution traces to dynamically align to shifting die within an embedded device structure — creating a unique design for each device during the manufacturing process. The company says the methodology integrates a fixed design pattern with an adaptive region to resemble classic wirebond, but realized through a wafer-level build-up flow. With an additional "dimensional inspection" step and processing through an automated design software, a unique design is created for every device within a molded panel, removing the barrier of a cost-effective embedded flow, the company claims.

The M-Series CSP is now sampling "to a limited set of customers," with broader availability planned for 2013, the company says.

Dr. Phil Garrou, SST‘s resident expert and blogger about all things advanced packaging, is digging into the details of Deca’s new CSP and "adaptive patterning" offering — look to his Insights from the Leading Edge (IFTLE) blog for an analysis in the coming days.

November 6, 2012 – A big boost in demand in the US helped ratchet up chip sales growth in September to its highest month-vs.-month rise in over two years, according to the latest data from the Semiconductor Industry Association (SIA).

After being essentially flat in August, global semiconductor sales rose to $24.79 billion in September, up nearly 2% from August. (The gap continues to widen vs. a year ago, though, now at nearly -4%). Sales in the third quarter totaled $74.4B, also up nearly 2% from 2Q12, but down -4.7% from 3Q11.

By regions, growth was most significant in the Americas, which posted its largest M-M increase since May 2010; sales increased across all other regions as well: Asia-Pacific (1.6%), Europe (0.7%), and Japan (0.2%). Compared with a year ago, though, all regions are still underwater, and in fact outside the Americas region the Y/Y decline is widening. On the bright side, the moving three-month average picked up nicely in September, from a minor decline in August to nearly 2% growth in September.

Brian Toohey, SIA president/CEO, credited the semiconductor industry’s "relative steadiness in a choppy global economy," but cautioned that lingering economic headwinds continue to pressure demand.

Barclays analyst CJ Muse notes that month-to-month semi growth flipped back into positive territory for the first time since June — but "all eyes remain on the trajectory for 4Q and outlook for 2013." Chip vendors’ current 4Q guidance is a decline of -1% to -8%, which would wrap up 2012 IC sales at around a -4% decline. "We continue to see a more modest recovery than what we had modeled at the outset of the year," he writes.

Tracking IC demand by application, Muse finds the automotive sector continuing to thin out — revenues up 4% Y/Y, vs. 11%/14%/19% in August/July/June, and unit shipments slowing to just 5% Y/Y vs. 22% in August — though ASPs are stabilizing (-1% Y/Y vs. -9% in August and -17% in July). The communications sector improved (11% Y/Y IC sales, 12% increase in unit shipments) as infrastructure spending seems to be rebounding. Computing continues to be "lackluster" with another -20% decline in revenues and -18% unit sales, though there was a M/M bump partly attributed to the Windows 8 launch. And the Consumer sector rebounded somewhat from a soft back-to-school season with 6% Y/Y sales and 10% higher unit shipments.

November 6, 2012 – Concern over a worrisome trend of underinvestment in semiconductor startups has prompted the Global Semiconductor Alliance (GSA) to form a new working group. Its inaugural mission: identify various alternatives to encourage startups to innovate, woo investors, generate returns, and keep generating sustainable industry M&A.

Investors are getting spooked from injecting capital into emerging semiconductor companies where the rate of return is becoming a longer-shot target. Complex digital IC products can require $100 million or more to develop and a decade or more to ramp-up with revenues; the GSA quotes analyst Andy Rappaport suggesting a semiconductor startup needs to hit $1B in a 5-10 year window off a $100M investment. Meanwhile, the semiconductor sector leads all industries in terms of R&D as a percentage of sales (24% for the 12 months 1Q11-1Q12), says the GSA. Besides the design and mask costs, there’s another $20M-$30M needed just for embedded software to make the design work, "an investment that is not easily recovered in the semiconductor business model where the price is often expected by the market to reflect silicon size," the GSA notes.

As a result, seed/Series A fundings have plummeted over the past decade, from several dozen annually averaging $9M-$10M in the 2000s to now just a handful averaging around $6M-$7M (and just $4.7M in 2011). That’s creating a major "innovation gap" in which there are fewer high-growth startup opportunities available, to be harvested by larger semiconductor firms seeking to bolster their position, leading to a longer-term move away from M&A as a viable strategy to achieve innovation and growth.

Total semiconductor Series A/seed funding, 2000-2011. (Source: GSA)

To address this widening gulf, the GSA has initiated a new "Capital Lite" working group populated with leaders from VCs, fabless firms and IDMs, semiconductor suppliers, and execs from finance, banking, and M&A interests. The group’s first official act is a white paper, "A Startup’s Guide to Surviving an Investment Drought," aimed to help inform and "invigorate" investment activity around semiconductor startups. Assisting this effort is a new resource portal in conjunction with IPextreme as a centralized location for tools and services from the entire semiconductor supply chain.

In the white paper, the group advocates for a "capital-lite" approach: a semiconductor startup sources services (e.g. IP, sales/marketing, SG&A, engineering, shuttle runs, etc.) from a larger semiconductor partner, which in turn reaps the benefits of another revenue source. The group puts out three types of hybrid financing models emphasizing different areas: low ASPs and high-volume markets i.e. consumer; higher ASPs/mid-volume markets i.e. enterprise; and IP-sharing/joint R&D. The group also advocates for a recently formed VC fund, "Silicon Ventures," which proposes to balance the risks between the startup, strategic partner/acquirer, and investors. It also points to the "Lean Startup" approach championed by entrepreneur Eric Ries, visualized as a "distributed startup" ecosystem here third-party technical activities are parceled out. (Adapteva is listed as a success story for this model.)

"We are looking to reverse the current decline in venture capital investment in the industry by re-balancing the risks associated with semiconductor start-ups," stated Silicon Ventures co-founder Ken Lawler. "Our model does this through active collaboration from inception between a start-up, a strategic partner/acquirer, and the investors, which will reduce product development costs, speed time to market, and provide compelling acquisition opportunities for the strategic partners."

November 5, 2012 – In early January of this year, both Samsung and LG showed off 55-in. versions of their organic light-emitting diode (OLED) TVs at the Consumer Electronics Show (CES) in Las Vegas. Commercial volumes were expected on shelves by the time of the 2012 Summer Olympics (which didn’t happen); they were again showed this fall at IFA in Germany.

Unfortunately, still struggling with low manufacturing yields and high prices, the two giants recently admitted the delivery of those technologies will be pushed out into 2013. NPD DisplaySearch now projects only 500 OLED TVs will ship in 2012.

Still, one must crawl before taking first steps and eventually running with the pack. Actually getting products out into the market is an important move, even as LCD TVs continue to get bigger and with higher resolutions. "4K × 2K LCD TVs have has become a focus and are currently available, and OLED TV needs to demonstrate its technical superiority," points out David Hsieh, VP at NPD DisplaySearch. "If we do see OLED TVs hit the market within 2012, the shipments will be used primarily for retail demonstrations in developed regions like North America and Europe."

OLED TV technology still has to overcome a number of obstacles, explained by the research firm:

  • Technical challenges: Making and scaling up large OLED panels (e.g. 55-in.) is a different animal vs. the smaller ones (e.g. 5-in.) now at high-volume output for smart phones.

  • Manufacturing limitations: Only two Gen-8 OLED lines are in place for TV panels, still in pilot mode and with low manufacturing yields which is keeping costs high and limiting the ability to address demand.

  • High price: Initial retail price for a 55-in. OLED will be around $10,000 — that’s not going to cut it when 60-in. LCD TVs sell for under $1000.

  • New high-definition competition: While the two Korean suppliers focus on OLEDs TVs, competitors in Taiwan, China, and Japan are developing LCD TVs with ultrahigh definition (4K × 2K).

  • Market timing: How much advantage do Samsung and LG have from their early adoption of OLED; will competitors quickly close that gap?

NPD DisplaySearch is still bullish on OLED’s longer-term competitiveness, though, expecting that suppliers in Taiwan, China, and Japan will indeed pick up the mantle of AMOLED TV panel production. The firm projects over one million unit shipments in 2014, and a 3% market penetration by 2016.

Forecasted shipments (in millions) and penetration rates for OLED TVs. (Source: NPD DisplaySearch)

 

November 5, 2012 – The US semiconductor industry now employs almost a quarter of a million workers and added jobs three times faster than the rest of the US economy, according to an analysis of government data by the Semiconductor Industry Association (SIA). Total direct US semiconductor employment is estimated at 244,800.

"Semiconductor workers — a quarter of a million strong and growing — are creating the technology breakthroughs that improve our lives, strengthen our country, and build our future," stated Brian Toohey, SIA president and CEO. "Through their hard work, the US semiconductor industry continues to create jobs and spur growth despite a challenging national economy."

According to the US Bureau of Labor Statistics (BLS), the semiconductor industry’s manufacturing workforce grew by 3.7% over the previous year, while jobs throughout the broader US economy increased by 1.2%. (It’s worth mentioning that the nation’s employers added 171,000 positions in October, according to just-published data from the US Labor Department.)

All employment figures reflect recently-released 2011 BLS data. Total semiconductor employment data is based on the number of semiconductor employees in the US manufacturing sector as reported by BLS, plus an estimate for the number of semiconductor workers employed by semiconductor fabless firms, which BLS currently counts in the wholesale trade sector. More detailed information is available in the SIA’s Employment Issue Paper.