Category Archives: Semicon West

August 9, 2011 – Robert Newcomb from Qcept Technologies explains his company’s nonvisual defect inspection technology for logic and IC manufacturers, speaking at SEMICON West 2011.

In today’s advanced manufacturing nodes, leading-edge wafer fabs are focused on yields and integrating new materials successfully. Customers in mainstream 200mm/300mm semiconductor fabs are more focused on cost reduction and environmental friendliness. Yield is still important, but the aim is a balance of cost savings, high yields, and other factors.

Ultrathin low-k dielectrics, high-k metal gate (HKMG) processes, and other technologies are creating new defectivity issues at 22nm. In some cases, Newcomb says, optical inspection will catch these, but other non-visual defects are becoming more prominent. Below 22nm, partnerships will be key, Newcomb expects. Fab customers are valuable in metrology research, as are wafer processing equipment companies.

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August 8, 2011 – Leti’s Serge Tedesco, lithography program manager, provides an update on the research group’s 193 optical lithography program for 22nm and below: processes and materials development. The group is also looking into multi e-beam lithography techniques for flexibility and cost effectiveness. The goal is 10 WPH on one module, then 100 WPH on a cluster tool (in 2017, Tedesco expects).

Tedesco speaks with Debra Vogler at SEMICON West 2011.

EUV will not be ready before the 16nm node; for NAND flash, not until 12nm. While EUV has many potential benefits, another technology will need to fill the gap. 193 immersion lithography (193i) is a viable option, for example, Tedesco explains.

Tedesco points out that the end-user perspective is always critical with new technologies. The tool is not enough — infrastructure must be ready for adoption as well.

Also watch Leti’s video updates from SEMICON West 2010 here.

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August 4, 2011 — Ludo Deferm, IMEC, came to SEMICON West with several major announcements, from the system level to the layers of semiconductors. IMEC’s major interests include scaling with 3D technologies, selective epitaxy, RRAM, lithography, and more.

 

Hot spots create charge losses in stacked chips. Stacking is nice, but if it creates memory losses, it cannot serve the industry, Deferm points out. Heat-spreading through silicon vias may be the answer to this problem. SEMICON West allows imec to bring problem resolutions like this to the design community.

For semiconductor device structures, scaling always has its limits. To get around that, imec developed an implant-free silicon germanium (SiGe) quantum well device. Selective epitaxial growth allows reduced lateral resistance. The channel control is much better, and the structure is scalable, but developments are still ongoing, especially on the PMOS/NMOS interaction.

In memory activities, imec is working on resistive RAM (RRAM) endurance (number of cycles) and materials, and new materials for the metal insulator/metal capacitor for DRAM to reduce leakage. The goal is smaller, denser memory with the same kind of capacity as larger generations.

Deferm also speaks about the lithography tool ASML delivered to imec in Marchl. They are using it for EUV litho exposures and a laser-assisted discharge plasma (LDP) source. These trials are headed for 60 WPH on the tool by 2012. Imec also is working on mask cleaning for EUV.

Wrapping up his talk, Deferm covers industry collaborations in 450mm production tool development, 3D integration, and new devices. Big equipment suppliers having to "do it all" in areas of new technologies, such as EUV and 450mm, want help from IDMs sharing the burden. Collaborations in 3D packaging is more related to applications than economics, and therefore collaborations are different. FinFETs and other new device architectures are only going to be used if neccessary, Deferm predicts, so it will come later than expected.

August 4, 2011 — Light emitting diodes (LEDs), silicon germanium (SiGe) semiconductors, and wafer-level packaging (WLP) bumps each present their own challenges to metrology systems, says Alon Kapel, Jordan Valley Semiconductor. He speaks with Debra Vogler at SEMICON West 2011.


LEDs are growing very fast, and the metal-organic MOCVD tool is the heart of the process, says Kapel. For about every 10 MOCVD tools, users need 1 metrology tool. Every MOCVD batch takes 12 hours, so measurement needs to be very fast, allowing the next substrate to begin processing.

Other areas where metrology is helping advance semiconductor technology include the move to triple-layer SiGe on the front-end, and wafer-level packaging on the back-end. Metrology tools must keep up with the pace of production and still offer the highest level of accuracy possible. (Last year Jordan Valley debuted the JVX7200 HRXRD/XRR for in-line SiGe process monitoring.) In wafer-level packaging, silver/tin bumps must be measured on-wafer and on-line.

Jordan Valley is collaborating on 450mm projects and participates in consortia, but Kapel noted that 450mm is a burden on vendors and the question still being asked is, "where

July 29, 2011 — "More than Moore" means growth in various sectors. At SEMICON West 2011, Ricky Jackson, Texas Instruments (TI), discusses analog IC developments.

TI builds analog devices on a high-speed platform (Example: hard-disk drive power amps); precision platform for low-noise devices (touchscreen controllers); high-power platform (controller ICs and power management chips); and high-density for integrating memory with analog.

At SEMICON West, Jackson addressed digital and analog pursuits of Moore’s Law. In digital CMOS, scaling down lithography nodes is the major enabler. Analog is different, with differentiation in design and precision.

Precision performance is critical at each node that the semiconductor industry acheives, Jackson adds, and new technologies will be a big part of that. TI’s infrared temperature sensor (made on the high-precision line) is 95% smaller and lower-power than conventional temperature sensors, providing one example of scaling and new technologies.

Jackson also discusses new capacity: since 2009, TI has added about $5 billion of potential revenue growth with added wafer fab capacity. It started with a Qimonda bankrupcy sale, the equipment from which is ramping to volume now. TI also bought some fabs in Japan from Spansion (2010) and added China fabs as well. The company launched its Clark packaging house in 2009.

Also read:
TI acheives volume production with stacked clip-bonded QFN

 

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July 27, 2011 – In case you missed it, SEMICON West is still the annual flagship show semiconductor industry, and even though it’s not the big-iron displayfest it used to be, there are still plenty of new product introductions to go around. Here’s just a brief rundown of some of the ones we tracked from this year’s show.


Aeroflex
The AX Series for RFIC and mixed-signal semiconductor test are modular, standards-based AXIe and PXI products, available as turnkey integrated systems or as configurable subsystem modules.

Alchimer
The AquiVantage wet-deposition process grows interconnect layers for interposer redistribution layers (RDLs) with cost savings of 50% vs. dry processes, the company claims, and significantly enhances the via-last backside wafer interconnect process. Using the same cost-saving technology as Alchimer

July 26, 2011 – Based on meetings and observations from this year’s SEMICON West, analysts Satya Kumar (Credit Suisse), Tim Arcuri (Citi), and CJ Muse (Barclays) — all panelists from the Thursday morning Bulls/Bears session — have some top-takeaways list for the industry: why WFE spending is slow, why it’s only a short pause, and which will comes first, EUV or 450mm.

The correction’s worse than thought… The consensus is that order pushouts are significant, causing caution among suppliers and weakness in 2Q11 and especially 3Q11. Kumar now projects 3Q11 orders will be below $30B-$34B (normalized) to $23B (annualized). Citi’s Tim Arcuri sees the "run rate" at around $20B, well below the $29B he deems "normalized." Wafer fab orders are down nearly -50% from peak levels in 4Q10, similar to the 2004 correction, he notes.

Kumar is lowering his full-year semi capex outlook again, just weeks after dropping his view to 7% growth (~$31B) from 15%-20%; now he’s thinking more like flat to up 10% to $29B-$32B. Likewise, Barclays’ CJ Muse is lowering its 2011 wafer-fab equipment outlook to $31B (7% growth), down from $33B. He’s maintaining his 2012 outlook of a "muted decline" of -3% to $30B.

Who’s to blame for the softness? Foundry spending is slowing and even pushing out orders, everyone seems to agree (analysts and suppliers). Arcuri points specifically to 28nm yield problems encountered by key foundry customers (QCOM, XLNX, NVDA) and delay of TSMC’s Fab 15, though he thinks "most of these issues could be resolved quickly, and we could see fab projects resuming soon" if end demand keeps up. Muse calls out TSMC and UMC for 2Q11 pushouts, and GlobalFoundries "and others" in 3Q11; GloFo’s problems extend beyond yield issues to its management uncertainty, he adds, and there’s confusion about investing in both Dresden and Malta operations. And there’s "no sign of life yet in DRAM spending" thanks to sluggish PC unit growth and ratcheted-down bit growth estimates, notes Muse: "any hope for DRAM recovery in 2H11 (as hoped for by AMAT, LRCX, etc. as of a few months ago) has evaporated, we believe, driving a more subdued 2H11 outlook."

Kumar, meanwhile, says weakness "is across the board," including not just foundry and DRAM but even NAND, all with softening orders over a six-month period (March-Sept.), and with all top equipment purchasers "showing signs of caution."

…But it’s just a pause. While all signs point to a soft 3Q for suppliers, this could only be a short-term correction. Total fab capacity is still -6% lower than 2008’s peak, while IC units are 33% higher, and only ~25% of announced new fab capacity has been equipped so far, Arcuri points out. That aforementioned run-rate gap (~$20B vs. $29B normalized) "is clearly unsustainable," he says, so he predicts a bottoming-out in 4Q11.

Muse too believes in a short-term "pause" in semicap, though his window of inflection for an orders rebound is a little wider, possibly leaking into 1Q12. The $40B WFE order runrate in 4Q10 was clearly a peak; today’s ~$22B runrate (by his calcs) is similarly too low, so there’ll be a ramp-up to get to $30B WFE in 2012.

Everyone’s seeing softness. ASML’s 2Q11 orders were

July 25, 2011 – At this year’s SEMICON West, 100+ attendees gathered at the Suss MicroTec workshop "3D Integration: Are we there yet?" to hear technical experts from around the globe to present updates on the status of 3D technology.

Eric Beyne of IMEC addressed the technical issues of carrier systems for 3D through-silicon via (TSV) thinning and backside processing, pointing out that right now silicon carriers are favored over glass because: (1) the glass must be CTE matched to silicon over a large temperature range, (2) the high cost of ground to tight TTV specification, and (3) a negative effect on plasma-based post-grinding backside processes due to its low thermal conductivity. After alignment and temporary bonding, Beyne recommends the use of use of in-line metrology to insure bonding integrity before grinding occurs.

Rama Puligadda, division manager for advanced materials R&D for Brewer Science, indicated that their Zonebond room-temperature debonding process is meeting all customer requirements and is moving towards full commercial introduction. The Zonebond process basically uses a 2.5mm ring of adhesive to hold the wafer in place for grinding and backside processing. This allows for easier subsequent debonding. The thin wafers are released from the carrier at room temperature after mounting on a film frame.

Stephen Pateras, product marketing director at Mentor Graphics, pointed out that TSVs can be used to create test access paths so that all BIST resources can be accessed on any device. Pateras also concludes that all EDA players need to support common test access infrastructures since this will be required to stack die from difference sources.

Eric Strid of Cascade Microtech revealed that the company is producing lithographically printed probe cards by MEMS techniques capable of 6

3 450mm cost challenges


July 25, 2011

July 25, 2011 — Bob MacKnight, president and CEO of Crossing Automation, says that the semiconductor industry