Category Archives: Semicon West

by Sarah Fister Gale, contributing editor, Solid State Technology

July 15, 2008 – Entegris is introducing two new filters to its Impact and Torrento product lines this week at SEMICON West to help fight the battle against smaller or more difficult to control contaminants in the fab.

“Every time you move to a smaller node you have to revisit contamination control requirements,” says Walter Plante, Entegris’ director of product management and marketing, liquid filtration products, contamination control solutions. “We are matching our technology with the [ITRS] Roadmap for defect reductions.”

Among the new crop of products is the Impact filter which enables retention of hard particles and gels for advanced processing nodes. Its asymmetric ultra-high polyethelene (UPE) membrane design places larger pores upstream in the filter with progressively tighter pores downstream, which lowers the device resistance (pressure drop) to maintain high-flow rates for point-of-use and bulk filtration of photochemicals. According to Plante, it is the first 5nm rated filter for point-of-use chemical filtration, “the tightest filtration technology available.” That means for a technology node migration a user can drop from a 20nm to a 5nm filter without losing flow rate. A Japanese IC manufacturer has already seen reductions of microbridge defects using the 5nm filters, the company claims.

For advanced wet etch and clean manufacturing processes (notably aggressive SPM, SC1, and SC2 chemistries), Entegris has added a 15nm PTFE membrane to its Torrento line. The Torrento filter features low pressure drop and a proprietary non-dewetting surface modification to ensure stability and extended performance.

Entegris also is introducing a new Scanner pre-filter system to extend the organic life of integral scanner filters, by better protecting against lens contamination from airborne low-molecular-weight silicon-containing (LMWS) and condensable organic species. This reduces lens-cleaning downtime and replacement delays, saving as much as millions of dollars, the company claims. “It’s a straightforward retrofit that is compliant with all manufacturers’ specs,” and requires no hardware changes, according to Jitze Stienstra, Entegris’ director of product marketing, gas filtration products, contamination control solutions.

Lastly, Entegris is rolling out a SiLVERSET chemical air filtration system for its E2600 filter cabinet, specifically to control trimethylsilanol (TMS) and related LMWS organics. “Over the years we’ve removed many contaminants from the fab, but the focus now is on increasingly difficult to remove contaminants” such as TMS, Stienstra said. — S.F.G.

(July 14, 2008) SAN FRANCISCO &#151 Urging presidential candidates to make technology policy a top priority, SEMI North America voiced their agenda for Washington at the SEMI Press Conference, held July 14 during SEMICON West. The agenda zeroed in on four critical areas: technology, tax, talent, and trade.

Victoria Hadfield, president, SEMI North America, outlined agenda details. “The industry cannot afford to finance R&D alone, which is the way its been.” noted Hadfield, calling for candidates to support a doubling of the current budget. She said SEMI also is stressing the need to bolster the US education system, encouraging Americans to pursue science and math degrees, while at the same time streamlining the path to citizenship for those with advanced degrees to keep talent local.

Panelist member, Bob Aken, chairman and CEO of CYMER, added his two cents, saying that “every Ph.D. in technology should come with a green card clipped to it.” Hans Stork, CTO Silicon Systems Group, Applied Materials, commented that doubling the R&D budget is “a marginally acceptable position that barely keeps up with inflation.”

Other laundry list items include a permanent and strengthened R&D tax credit, accelerated depreciation of equipment, and support for free trade agreements and open markets.

(July 14, 2008) SAN FRANCISCO &#151 Setting the tone for the week’s events, Stan Myers lead off SEMICON West’s opening press conference, presenting the latest trends worldwide, midyear equipment forecast by market segment, and reporting the findings of the SEMI equipment productivity working group’s (EPWG).

In the assembly and packaging sector, Myers pointed to a 14% decline in equipment revenue from 2007 to 2008; a smaller percentage in comparison with the overall equipment forcast, which declined 20% overall. Additionally, forecast statistics indicate a rebound in the packaging sector slightly above 2007 numbers by 2010. Test and wafer processing will rebound at a slower pace.

On the materials side, Myers noted the slow but steady growth of the past few years will continue, but is entering a critical period. “The oil and energy crisis is affecting the chemical producers, hitting raw material prices for semi and solar suppliers.”

Myers also discussed the controversial topic of the industry’s eventual transition to 450-mm wafers, reporting findings of the EPWG. “The semiconductor industry is at a critical and important point in time,” he noted. “The decisions we make now will impact the future.”

The EPWG examined facts and myths surrounding the implication that the transition is necessary for the continuation of Moore’s Law, and cost of transistors. After conducting studies industry wide, the group determined that change to a larger wafer size in itself does not lead to significantly reduced costs, and that cost reductions for 300 mm were the result of other factors, such as the use of factory automation and ceasing to make improvements at 200 mm. Ultimately, the group recommends holding off on the transition for the time being.

“Sometime it might make sense,” said Myers, “Now is not the time. The industry should stay focused on smaller, cheaper, faster.” He added that as there are limited R&D funds available, focus should be on where those dollars can be best invested. Myers pointed to final manufacturing and materials as areas of concern that should be addressed first.

by Sarah Fister Gale, contributing editor, Solid State Technology

July 14, 2008 – Despite projections about the future popularity of the “mini fab” model of ≤10,000 wafer starts/month (WSPM), what the semiconductor industry has seen is economies-of-scale pushing in the other direction, as big fab facilities with 60,000 WSPM are becoming the norm, observes Asyst Technologies CEO John Swenson. He’s got a front-row seat to this trend — the company claims to automate materials handling for >50% of all 300mm silicon wafer production, and worked directly with Toshiba on its behemoth gigafab project with Sandisk that can handle up to 200,000 WSPM.

But with scale comes a much greater order of complexity necessary to automate these massive facilities, and as fabs get bigger and the number of process steps increase there are greater risks for bottlenecks, slowdowns, and delays that can impact yield. “Some of these fabs have multi-million dollar tools that sit idle 10%-20% of the time. That’s wasted capital,” Swenson told SST, in an interview before SEMICON West.

To combat those slowdowns, Asyst has developed several solutions that can reduce process time and improve flow, which it will be showcasing at this year’s show.

The company’s newest Agile Automation family is an automated lifting load port, with the conveyor mounted on the floor under the load port shelf and a mini stocker at either end to improve throughput and reduce idle time, and added automation software that enables the stocker to load itself whenever space becomes available. When the load port needs more wafers, it can automatically lower the shelf to the ministocker and load up with more wafers on-demand without calling on the vehicle, Swenson explained.

Asyst says the system can reduce wait timed between wafer pick-up and drop-off from four minutes to 15 seconds. For short term process steps that can handle 150 wafers per hour, Swenson predicts a 30% improvement in production capability, which means 30% more throughput for those applications. “That’s based on real world simulations using actual customer data,” he said. And eliminating idle times means eliminating idle times and ultimately fewer tool investments, he added.

Asyst also is showcasing its new Visual Analysis and Optimization (VAO) software, which gives fab managers a bird’s-eye view of what’s going on in the fab even from hundreds of miles away. The software creates an animated visualization of real-time data generated from the fab (e.g., process steps and material movement) and highlights problem areas such as bottlenecks or idle tools to give viewers an instant understanding of what areas require attention.

“No-one ever knows what to do with all of the data generated from the fab each day,” noted Swenson. “This tool takes all of that information and creates a visual image of it so you can see in an instant what’s going on.” — S.F.G.

Asyst’s Agile Automation solution, demonstrated in an integrated wafer sorter application. Wafers are buffered locally in satellite stockers and shuttled to the tool through a floor-based conveyor; from which FOUPs are lifted directly by direct load lifting loadports. (Source: Business Wire)

by Debra Vogler, Senior Technical Editor, Solid State Technology

July 14, 2008 – Kicking off SEMICON West, IMEC says it has been able to achieve electrically functional 32nm SRAM cells (FinFETs). The fin and gate levels were prepared using immersion lithography, but the contact hole level was exposed using EUV lithography (hole size 50nm). The work was done on ASML’s alpha tool installed at IMEC.

Although this work was done at 32nm (back in Feb. IBM and AMD announced a working 45nm test chip using EUV lithography for the first critical layer of metal interconnects), the ultimate target is for a production-worthy EUV tool at 22nm. In the PR announcing this latest EUV work, IMEC optimistically said it is “stimulated” by such milestones and “a concerted effort” from all EUV parties, and is “determined to advance EUV full-speed toward the 22nm node.”

“Memory companies will most likely insert EUV at 22nm to obtain the required half-pitch, while many logic manufacturers will be able to delay EUV insertion until the 16nm node, which for them corresponds to a 22nm half-pitch,” explained Kurt Ronse, program director, advanced lithography, at IMEC, in an interview with SST.

The consortia also is studying which layers can be exposed using EUV beyond the contact layer, and which would be exposed using immersion lithography. “We are looking at 3-4 layers or more using EUV at 22nm half-pitch,” Ronse said.

ASML’s roadmap still calls for a high-volume EUV tool to be ready by the end of 2009 or the beginning of 2010, according to Ron Kool, VP of ASML’s EUV business unit. “We expect a source will be ready in time, and overlay numbers between EUV layers and immersion layers will be ready as well,” he said. The most important task now, he noted, is achieving high throughput — which translates to getting a source that supports that capability.

Stimulated by these milestones and with a concerted effort from all actors involved in EUV research, IMEC is determined to advance EUV full speed towards the 22nm node. — D.V.

32nm SRAM device after EUV ADT exposures with various doses and after oxide etch. (Source: IMEC)

Test Measurement Unit


July 2, 2008

The ITC59200 test measurement unit (TMU), from Integrated Technology Corp. is designed to provide two test functions: die attach and forward bias safe operating area (FBSOA). Die attach testing is performed to detect voids under the die and other types of device construction flaws that could affect the lifetime and safe operating area SOA of the device. The FBSOA non-destructive test is used to determine the SOA of the device, which is defined as the voltage and current conditions at which the device is expected to operate without damaging it.

The ITC59200 TMU is the second in a series of measurement units that run in the ITC59000 test platform. Up to four TMU’s can be installed in the ITC59000 for true parallel device testing and these can be a combination of the new ITC59200 and the ITC59100 Gate Charge/Gate Resistance TMU introduced in 2007.

The ITC59200 ITC will be introduced at Semicon West, Booth #7137. West Hall, Level 1.

Integrated Technology Corp. Tempe, AZ www.inttechcorp.com

The Quick View CT inspection system from Dage allows users to obtain initial computerized tomography (CT) reconstructions within 5 minutes, compared to previous times of over 20 minutes. This quick view CT software makes CT a more viable process tool for production and failure analysis applications.

The Quick View CT software is available for Dage’s x-ray inspection systems that combine digital acquisition technology and ImageWizard software. Combined with the advanced technology Dage NT x-ray tube, these systems are said to provide sub-micron feature recognition with the added benefit of a sealed tube for minimal maintenance

Quick View CT will be showcased at SEMICON West, Booth # 7401 West Hall, Level 1
Dage Precision Industries, A Nordson Company Fremont, CA. www.dage-group.com

The BONDJET BJ820, from Hesse & Knipps, is a high-speed, fully automatic wedge bonder for both high-speed round wire and deep access ribbon and wire bonding. It handles all challenging fine pitch wire bonding applications in a single platform &#151 including RF and microwave devices, COB, MCM and hybrids, fiber optics and automotive &#151 using aluminum or gold wire or ribbon. It reportedly offers bond speeds up to 7 wires-per-second.

With axis repeatability of 1&#181m at a balanced encoder resolution of 20 nm, the BONDJET BJ820 provides increased process stability for reportedly reliable bonding of extremely small bond pads with a larger wire diameter. A 12″ x 16.1″ work area can double as two or more smaller stations to accommodate smaller products or substrates. Additionally, its 720 x 1250 mm footprint allows for easy integration into existing floor plan configurations or new concepts. Other capabilities include:

  • 12.5 &#181m to 85 &#181m diameter wire bonding.
  • Ribbon bonding from 6 x 35&#181m to 25 x 250 &#181m.
  • Constant loop height and wire length.
  • Maintains parallel loops within mixed reference system.
  • Auto-teach for linear applications, reducing programming time.

    The BONDJET BJ820 will be showcased at SEMICON West. Booth 7357, West Hall Level 1.
    Hesse & Knipps Paderborn, Germany www.hesse-knipps.com

    • QFN Test Socket


    July 2, 2008

    The Z-Socket, or impedance socket, from Antares, is an RF QFN test socket developed to combine the reliability of traditional spring-probe technology with the impedance-matching functionality of shorter interconnects at higher price points. The Z-Socket uses spring probes to accommodate variable or warped packages better than shorter interconnects that generally can’t establish co-planarity with warped packages. By combining spring probes with an impedance-matching system, signal-integrity performance equal to that of sockets with conductive elastomer or offset stamping contactors has reportedly been achieved.

    The Z-Socket is said to achieve impedance of 50 Ohms via a proprietary impedance-matching system that optimizes the diameter, length, and material properties of the spring-probe contacts and composition and location of the ground block in ceramic PEEK housing. Antares’ patent-pending system centers on embedding the spring probes into the copper ground block to connect the ground pad of the QFN package to the PCB. The impedance-matching system can reportedly be fine-tuned to meet various impedance requirements, including 75 Ohms.

    The Z-Socket will be showcased at SEMICON West, booth #7211, West Hall, Level 1. Antares Advanced Test Technologies Vancouver, WA, www.antares-att.com

    (July 2, 2008) CHANDLER, AZ &#151 Amkor Technology, Inc. announced the introduction of a high-performance flip chip packaging technology using an advanced molding process technology that is expected to provide a number of design, cost and performance advantages for field programmable gate arrays (FPGAs), CPUs, graphics processors, and ASICs. The company plans to feature this technology during SEMICON West 2008, July 15 – 17, in San Jose, CA.

    According to Amkor, this novel molding process establishes a platform technology, with the first package offering for flip chip (over) molded ball grid array called FCMBGA. The process underfills flip chip die with molding compound to provide both mechanical and electrical performance advantages such as:

  • Larger die-to-package ratios that reduce package footprints.
  • Reduced package warpage for tighter coplanarity control.
  • Reduced material stresses.
  • Additional mechanical support for heat sink attachment and multi-die designs.
  • Improved signal integrity for noise-sensitive high speed signals through the placement of surface mounted passive devices (like decoupling capacitors) closer to the die.
  • Reduced signal lengths and power distribution for challenging signal and power integrity requirements by enabling use of coreless or thin core substrates.

    “Amkor developed this technology as a cost and performance enhancement to our industry leading SuperFC® package family. The molded structure improves coplanarity without requiring a stiffener, yet offers flexibility for lid attach in large package or high power applications,” said Miguel Jimarez, vice president of advanced process development at Amkor.

    This is the second package platform introduced by Amkor this year. FusionQuad, a novel lead-frame based package platform, was introduced in February 2008.