November 29, 2007 – Nikon is uncrating a new i-line stepper that it says exceeds 200 wafers/hr throughput, targeting use in sub-critical layers in volume production of memory and microprocessor devices.

The NSR-SF155, an upgrade from the NSR-SF150, boasts 200 WPH “or greater” with <25nm overlay accuracy, achieving the same wide exposure field as DUV scanners, the company says. It incorporates the company's "Skyhook" technology to eliminate effects of ground and stage vibrations, as well as new stage countermasses and improved temperature stabilization in the chamber.

The NSR-SF150 previously was touted as able to print 180 300mm wafers/hr, according to a Nikon exec speaking this year’s SEMICON West.

By Phil LoPiccolo, Editor-in-Chief

The promise of photovoltaics (PV)—to solve the world’s energy problems as well as fuel semiconductor industry growth)—drew overflow crowds to presentations on anything solar at SEMICON West 2007. This two-part series reports on a pair of keynotes headlining the conference that described opportunities and challenges for semiconductor manufacturers and suppliers in the solar market.

Part One, “High time for solar power,” explores the bright future for expanding the adoption of PV technology in the US, as envisioned by Rhone Resch, president of the Solar Energy Industries Association.

Part Two, “Making solar cells: This IS your father’s fab,” examines the fundamental differences between making solar cells and integrated circuits, from the perspective of T.J. Rodgers, who serves as both chairman of solar panel maker SunPower and president and CEO of IC manufacturer Cypress Semiconductor.

by M. David Levenson, Editor-In-Chief, Microlithography World

The 2007 edition of SEMICON West (July 17-19, San Francisco, CA) wasn’t what it used to be. Semiconductor manufacturing equipment customers did not seem to be thronging the booths as in the legendary past, and neither were the venture capitalists or security analysts. Few vendors brought complete processing tools — or even mock-ups — to the Moscone Center floor. The days when demo tools could run wafers from potential customers are long gone. Except possibly for the very biggest companies, the booths seemed small but uncrowded. A few companies declined to participate in the exposition at all, doing business instead from nearby hotels. SEMICON West is about networking, and corporate image, today, not technology demonstrations. The exhibition acts mainly as an anchor for the networking,” observed Gerhard Ruppik, GM of Vistec’s semiconductor systems division (which itself is undergoing a transition).

Technology concerns

As usual, much of the technology discussion focused on the next shrink, either 45nm or 32nm half-pitch. However, the industry is at an inflection point, with reduced dimensions not actually increasing performance, according to Mukesh Khare of IBM. Instead, that burden must be carried by materials innovation, with geometrical shrink perhaps lowering costs.

The innovation du jour is high-k gate dielectric with metal gates (HK+MG), but there are several flavors of it, with two metals or two dielectrics (one for p- and the other for n-gates), the final gate patterned first or last, etc. according to Raj Jammy, IBM assignee to SEMATECH. Different schemes will be used for logic and memory, with flash employing a unique charge-trap stack. Whatever deposition and etch systems is used to create the final structure, it must achieve the same carrier mobility enjoyed by traditionally grown SiO₂, while reducing power consumption and leakage. Implementing the new materials technology in a year’s chip production will directly save 10GW of electricity through reduced leakage, according to Tom St. Dennis, SVP of silicon systems at Applied Materials.

Other materials issues involve the resistance of vias and the capacitance of tall poly stacks. Tungsten plugs can be used at 50nm but not 40nm, Khare predicted, suggesting copper be employed instead. Contact resistance might be reduced by substituting ErSi or YbSi for NiSi. Further along, new device structures such as ultrathin SOI gates with 10-15nm thick bodies may be required.

Alliances of companies will seek to drive performance by innovating and transferring materials technologies to manufacturing, despite their complexity, opined Bob Villetto, also of IBM, at KLA-Tencor’s “Future Technology and Challenges” forum. He noted that 32nm process manufacturing will need nine new metrology and inspection techniques, and he quoted no less than 72 issues to be addressed. IBM and its partners are relying on a 300mm R&D fab in Albany to prove the innovations before their release to scale up, he said, though it does not appear that the various alliances are likely to take risks or find unobvious approaches.

Around and about Moscone

There were few actual pieces of semiconductor processing equipment at the equipment show this year. The largest was probably the 12 chamber Raider frontend clean system shown by Semitool; it was roughly 6m long x 2m wide by 2m high. According to Jim Garstka of Semitool, the Raider system is the successor to the conventional wet bench and is available with as few as 2 chambers. BlueShift Technologies showed a 5m x 2m linked vacuum robot system in a vacuum chamber system mock-up. The Applied Materials booth had six individual chambers and various displays set up, but no complete cluster tool.

The most interesting working apparatus on the floor was the FEI Phenom, a table-top SEM with an intuitive touch-screen display interface and one knob (which did different things) for fine control. The SEM with backscatter detection could accept samples as large as 1″ in diameter in a sample holder that allowed an adjustable working distance. Even the vacuum pump was in the table-top SEM console, which was about the size of a standard desk-top PC. The sample chosen to be shown by FEI was a mosquito, which could be zoomed in and out, its image rotated, defocused and automatically re-acquired. The Phenom seemed easier to use than a light microscope, but there was no color in the images.

The Coherent booth had the most lasers, 11 of them, with eight up and running at various colors from violet to yellow in a single display. The flashiest booth, though, was Patlite’s, a company that makes LED warning lights, some with air horns and rotating mirrors.

The wildest keynote was by T.J. Rogers of SunPower and Cypress Semiconductor. He described the motivation for and founding of SunPower, whose first fab has 32 million wafers/year throughput. To lower cost, the solar power industry needs new high volume low cost equipment such as a continuous doping machine, capable of 800 WPH that costs less than $400k, according Rogers. Historically, solar power in the US grows at 20%/year, but the German subsidy model would result in 67%/year growth. Rogers’ goal for the industry is to install 800MW every year for 10 years (last year it installed 150MW). Most polysilicon is now going to solar power, he reported, and that will continue even if cells become thinner (SunPower’s single crystal wafers are at 0.16mm now) unless the efficiency of thin film solar cells improves dramatically. With a Tesla electric car and a modest solar installation, Rogers claims most Californians can avoid net consumption of oil. The car and solar panels cost $100k today, though, but Rogers anticipates that falling to $30k or so as economies of scale kick in.

Thin wafers will be coming, and not just for solar cells, but also for stacked chip packages. The thinnest 300mm was Accretech’s, 5µm thick with chips in place. It was held squeezed between two class plates to keep it flat. Otherwise, it would have bent like potato chip. A white light behind showed red on the other side, with some circuit features dark and others golden.
–M.D.L.