Category Archives: Semicon West

8:30 a.m.-4:30 p.m.
SECS/GEM Maps and Trace Standards for Assembly Test (Day 2)
San Jose Marriott Hotel, San Jose

9:00 a.m.-3:00 p.m.
How to Succeed in the China Market
San Jose Marriott Hotel, San Jose

9:00 a.m.-12:00 p.m.
STS: IEMT (Day 3)
San Jose Marriott Hotel, San Jose

Asymtek Awarded Patents for Underfill Dispensing and Conformal Coating Techniques
BY RYAN CLICHE

Visit Synergetix at Booth #11411 to learn more.

The following are press conferences and educational sessions that will be held at SEMICON West in San Jose, Calif. on July 16, 2003. To check for availability of these courses or others, or to register online at SEMI’s Web site. Registration for programs/events includes free admission to the exposition.

8:00 a.m.-5:00 p.m.
Semiconductor Processing Technology (Day 2)
San Jose Marriott Hotel, San Jose

Bond Tester
Designed to meet the demands of testing ultra-fine-pitch wire-bonded devices, the Series 5000 Bondtester is said to be capable of testing bonds at pitches of 50 micron and below. An advance from the company’s Series 4000 Bondtester, the upgraded model reportedly includes numerous advantages, including optical systems to help operators align and grade the bonds, ultra-low force transducer systems and shear-and-pull tooling to minimize lead and ball damage.
Dage Precision Industries Inc.

3M
McEnery Hall – Booth #10232

The following are press conferences and educational sessions that will be held at SEMICON West in San Jose, Calif. on July 17, 2003. To check for availability of these courses or others, or to register online at SEMI’s Web site. Registration for programs/events includes free admission to the exposition.

When:

Welcome to Day 1 of From the SEMICON West Tradeshow Floor, your e-show daily for the backend of SEMICON West in San Jose.

APEX EXTRAVAGANZA


March 28, 2003

Semi-automatic Screen Printers
The Viking-class Horizon 05 platform featuring fully automatic vision alignment has adjustable stencil mount and extensive networking capabilities. Viking-class machines will accept stencils up to 29 x 29″, and reportedly can be upgraded to pass-thru capability as business requirements evolve. Advanced options are said to include automatic paste dispensing, ProFlow, 2-D inspection with advanced optics and lighting. Vortex underscreen cleaning may be specified at manufacture or added later as machine performance upgrades. DEK, Zurich, Switzerland Booth 2225

Tessera Announces Symposium on 3D Packaging, Advanced Packaging Media Sponsor
SAN JOSE, CALIF.
As part of its ongoing efforts to educate and elevate awareness of advanced packaging technologies, Tessera Inc., a premier technology developer and services provider for chip-scale and multi-chip packages (CSPs and MCPs), announced it will host a half-day symposium on 3D packaging technologies during the week of SEMICON West 2003. Speakers and panelists will include a number of leading technologists from premier companies throughout the electronics manufacturing, assembly, and packaging supply chain.

Calendar of 2003 Events


January 1, 2003

JANUARY

SEMICON Korea,
21-23, Seoul, Korea, www.semikorea.org

INTERNEPCON Japan,
22-24, Tokyo, www.reedexpo.co.jp/inj/english

Photonics West,
25-31, San Jose, Calif.,

February

Pan Pacific Microelectronics Symposium & Exhibit,
18-20, Kohala Coast, Hawaii, www.smta.org


MARCH

SEMI-THERM,
11-13, San Jose, Calif., www.semi-therm.org

SEMICON China,
12-14, Pudong, Shanghai, www.semi.org

Optical Fiber Communication (OFC) Conference & Exhibit,
23-28, Atlanta, www.ofcconference.com

APEX ,
31-2, Anaheim, Calif., www.goapex.org


APRIL

SEMICON Europa,
1-3, Munich, Germany, www.semi.org

IMAPS Ceramic Interconnect Technology,
8-9, Denver, www.imaps.org

International Conference on Electronics Packaging (ICEP),
16-18, Tokyo, www.imaps.org


MAY

SEMICON Singapore,
6-8, Singapore, www.semi.org

SMT/Hybrid/Packaging,
6-8, Nuremberg, Germany, www.mesago.de

Electronic Components & Technology Conference (ECTC),
27-30, New Orleans, www.ectc.net


JUNE

NEPCON East,
10-11, Boston, www.nepcon.com

European Microelectronics and Packaging Conference (EMPC) & Exhibit,
23-25, Friedrichshafen, Germany, www.empc2003.de


JULY

SEMICON West (Wafer Processing),
14 – 16, San Francisco, www.semi.org

SEMICON West (Final Manufacturing),
16-18 San Jose, Calif., www.semi.org


SEPTEMBER

International KGD Packaging and Test Workshop,
7-10, Napa, Calif., www.napakgd.com

National Fiber Optic Engineers Conference (NFOEC),
7-11, Orlando, Fla., www.nfoec.com

SEMICON Taiwan,
15-17, Taipei, Taiwan, www.semi.org


OCTOBER

SEMICON Southwest,
14-15, Austin, Texas, www.semi.org


NOVEMBER

Productronica,
11-14, Munich, Germany, www.productronica.de

International Microelectronics And Packaging Society (IMAPS),
16-20, Boston, www.imaps2003.org


DECEMBER

SEMICON Japan,
3-5, Tokyo, www.semi.org

By Debra Vogler
WaferNews Technical Editor

“Another major initiative is getting a common highway to the customer base,” says Zafiropoulo. “Especially since utilization in factories is typically less than 50%. We need to find a better way to get data from machines to people with security.”

Zafiropoulo describes a possible approach as a kind of pay-as-you-go service similar to a phone line – one accessible to any SEMI member. “Other information such as technical data, marketing information, updates, etc., could also be transmitted rapidly and ultimately improve access to information, increasing factory utilization and feedback.”

If this year’s SEMICON West was any indication, the ATE sector of the industry appears to have a proliferation of standards and open architecture activities with no end in sight – Zafiropoulo has his work cut out for him. Toshio Maruyama, president and COO of Advantest Corp., and Nicholas Konidaris, president and CEO of Advantest America, chaired a press conference introducing the Semiconductor Test Consortium.

The consortium, open to all in the semiconductor industry with a vested interest in the test sector, seeks to simplify and reduce the cost of testing complex logic devices. A list of members was not disclosed but representatives of Intel and Wavecrest participated in the announcement. Konidaris characterized the activity by noting, “You can have a bold move by a major supplier and a major customer, or you can wait longer for a standard.” Intel attendees noted that the IC manufacturer wants a common infrastructure – they don’t believe the current situation in the industry is workable. The white paper upon which the consortium is based was authored by Intel and covers general attributes and capabilities for ATE platforms including flexibility, modularity, scalability, efficiency, and the computing environment.

Even before SEMICON West, Teradyne announced its open architecture initiative, which is used in its Integra FLEX test system. According to Mark Kohalmy, business development manager of the initiative, the idea is to enable a broader array of third party instrumentation suppliers the ability to provide instruments that work with Teradyne’s platform. But an open architecture isn’t the same as a standard, cautions Kohalmy, and likened the activity in the ATE sector to the beginnings of the Internet.

Noting that Teradyne has almost 40% of the market share for SoC testers, Kohalmy believes that is one reason the company will be successful in its open architecture strategy. In this respect, the situation may be similar to that concerning Applied Materials, which has such a large market share that it has led to a number of communications protocols becoming de facto standards.

Other reasons Kohalmy gave for believing in Teradyne’s open architecture: “It’s available now and we’ve already shown that it can be used by disparate design teams. Teradyne has development centers worldwide so we needed a standard interface. FLEX was designed to have an open architecture.”

Agilent’s Tom Newsom, VP and GM of the SoC business unit, says the company is a big believer in standards and supports the major ones already in use. So far, the company is not a part of a specific open architecture, preferring to stick with its 93000 SoC tester strategy. When asked how anyone could ignore the fact that Intel is working with Advantest on its Semiconductor Test Consortium, Newsom acknowledges that no one can ignore Intel, but he frames the issue around the question, “What does Intel want?”

“It wants fewer platforms with longer life and more capabilities on a single platform,” he answers.

He offered that Intel most likely believes in an open architecture because it worked for the PC industry.

Newsom brought up the ATE industry’s experience with the VXI standard as a learning experience. Based on the VME architecture, VXI is a backplane interface standard driven by the military. According to Newsom, although the original thought was that a standard open architecture would result in less costly cards, that was not the case.

“A lot of overhead was designed into the instrumentation cards, making them more expensive because you never really know what card would be next to what [in the test rack],” he explains.

Asked to comment on VXI, Kolhamy explains that, because of its military application – testing at avionics maintenance depots – the test volume was very low and throughput was not a requirement. The semiconductor industry has a large test volume and requires high throughout.

“The requirement for VXI was one of complexity, not throughput,” states Kolhamy.

NPTest, the wholly owned subsidiary of Schlumberger Ltd., has also been working on a strategy – the company will have more to say at the International Test Conference in October, according to Burnie West, technical advisor to the company.

Regarding the open architecture efforts currently being undertaken in the industry, West states that obtaining an open architecture is a complex undertaking with respect to the high volume test arena and thinks one question should be asked: “Did you think about these things [e.g., plug ‘n’ play instrumentation, massively multi-site test execution, consistent high-speed system communication] within the context of enabling effective participation without extensive collaboration with the platform owner?”

Explaining the difference between a standard and open architecture, West states, “If an architecture is sufficiently open and accessible and technically sound, it can become a de facto standard.” He further made a distinction between standards that become barriers vs. those that promote innovation.

“If a standard gets adopted too early, it tends to stifle innovation,” explaines West. “A standard promotes innovation if it’s a platform that innovators can stand upon instead of a barrier that they have to punch through.”

WaferNews

SEMICON West Headlines


September 1, 2002

SAN JOSE, CALIF. – Below are some of the many press releases announced during SEMICON West. Visit the Advanced Packaging Web site at www.apmag.com to find links to all these and other stories from SEMICON West.

  • Adept Technology Chosen as New Automation Member of APiA
  • Advantest Driving Formation of Industry-wide Consortium Aimed at Establishing First Truly Open Test Architecture
  • Agilent Technologies, ACCRETECH and Cascade Microtech to Provide New Cost-saving Parametric Test Solution
  • Amkor and Unitive Form Manufacturing Alliance for Asian Supply Chain
  • August Technology Enhances Wafer Bump Inspection Product Family
  • ChipPAC Engineers System Package for High-performance Applications
  • Cookson ElectronicsSemiconductor Products Introduces No-Flow Underfill for Flip Chip Applications
  • Coreco Imaging Announces High-performance, 64-bit Camera Link Frame Grabbers
  • ESEC Introduces Revolutionary Bondhead Technology at SEMICON West
  • Fujitsu Microelectronics Introduces Industry's Smallest Chip-size Module with Advanced System-in-Package Technology for Mobile Systems and Consumer Electronics Products
  • IMEC Sets up New Center of Excellence in Reliability
  • KINESYS Announces Latest Version of Assembly Line Production Supervisor (ALPS) Software for Back-end Process Automation
  • Kulicke & Soffa Announces D2I2, A Coreless, High-density, High-frequency Substrate
  • Mühlbauer Showcases Successful High-speed Die Sorter at SEMICON West
  • n&k Technology Inc. Announces Metrology Tool for Characterizing Ultra-thick Photoresists
  • Newport Corp. to Introduce New MRSI-375FC Flip Chip Bonder at SEMICON West
  • Palomar Technologies Introduces the Gold Connection for Gold Ball Bump and Flip Chip Thermocompression Bonding
  • phoenix|x-ray Unveils Industry's First Back-end Inspection Roadmap
  • SECAP to Install 300 mm Bumping Line in Asia Open to the Industry
  • SEMI Announces Mid-year Consensus Forecast for Chip Equipment Industry
  • SUSS MicroTec Introduces Mask Aligner for 300 mm Packaging Applications at SEMICON West
  • Tegal Joins APiA, The Advanced Packaging and Interconnect Alliance
  • Tessera Introduces µZ-Ball Stacked Memory Package for Computing and Portable Electronic Products
  • Ultratech CEO Arthur W. Zafiropoulo Elected SEMI Chairman
  • Universal Reveals New Flip Chip Capabilities

AP