Category Archives: Semicon West

Much has been said of the 450mm transition.  But the description of this inflection is something of a misnomer.  Though everyone desires a smooth, coordinated and orderly conversion, it may be a little less placid than the term “transition” implies.  Rather, I suggest calling it the 450mm “transformation.”   Because, even for the segments that continue manufacturing semiconductor devices on 300mm and 200mm silicon wafers, the industry will change dramatically with the introduction of 450mm wafer processing. The 450mm era will impact industry composition, supply chain dynamics, capital spending concentration, future R&D capabilities and many other facets of today’s semiconductor manufacturing industry — not the least of which are the fabs, wafers and tools with which chips are made.

The shift to 450mm will take a several years to manifest and numerous complexities are being skillfully managed by multiple organizations and consortia.   For those reasons, the evolutionary tone of “transition” seems appropriate. However, once the changeover occurs, in hindsight, most in the industry will recognize that they participated in something transformational.

No transformation occurs in isolation and other factors will contribute to the revolutionary qualities of 450mm.  Market factors, new facilities design, next generation processing technology, the changing dynamics of node development and new materials integration will simultaneously affect the industry landscape.

While reading about the implications of 450mm is valuable, I believe that there is much to learn by being a part of the discussion. How is this future transformation being envisioned and acted on today?  I hope that you will join us — at our “live” event, where you will have the opportunity to hear first-hand information… direct from well-informed experts in the industry.

SEMICON West offers this opportunity with “Must See” 450mm events to mark on your calendar…

….450 Consortia plans, timelines and status; equipment development; critical standards; future-looking fab facilities and EHS issues; executive perspective, and vital R&D capabilities will all be covered at SEMICON West.

Wafer Standards

The transition to 450mm manufacturing is accompanied by the development of various standards aimed at achieving cost, efficiency and technology improvements. Some standards are a product of the deliberate consensus-based SEMI International Standards program, which has produced over 15 essential 450mm-specific standards to-date.  Additionally, consortia, customers and suppliers organize complementary efforts to align common approaches to transition solutions.

Potential revisions in the 450mm wafer specification are under consideration.  At least two issues are currently being evaluated by the industry and both portend significant ramifications for wafer suppliers, equipment makers and those technologies that interface with the wafer.

First, the wafer orientation method may be revised to eliminate the orientation “notch” on the perimeter of the substrate. The notch was introduced in the 300mm transition as an alternative to the flat.  However, both equipment suppliers and IC makers, through a constructive and collaborative dialog, have concluded that eliminating the notch can potentially improve the die yield, tool performance and cost.

Secondly, reduction of the wafer edge exclusion area — that peripheral portion of the silicon on which no viable device structure occurs — also offers potential yield advantages.  The current 450mm wafer specification (SEMI E76-0710), originally published in 2010, calls for a 2mm edge exclusion zone.  IC makers believe that reduction of this area to a 1.5mm dimension offers the cost equivalence of a 1 percent yield increase.  Though a percent may sound trivial, it is represents substantial increased value over time.

These and other wafer-related issues will be key topics at SEMICON West and will be thoroughly reviewed on Wednesday, July 10 at the SEMI Standards program entitled “Silicon Wafers — Future Standardization to Enable the Transition.” Materials will be presented by expert speakers including authoritative customers participating in the Global 450 Consortium (G450C), which includes Samsung, TSMC, IBM, Intel and GLOBALFOUNDRIES.

Facilities and EHS

Wafer transitions offer one of the rare periods when new approaches can be developed and integrated into facilities plans.  During the 300mm transition, significant developments occurred in factory automation and wafer handling. Similarly, the 450mm transition is a window to update the industry approach to a number of fab systems. Rising energy costs, water scarcity, and climate change will continue to present both challenges and opportunities for semiconductor manufacturing in the 450mm era. These sustainability concerns are driving demand for tools that can more reliably and cost-effectively achieve a shared vision of resource balance.

Along with cost and efficiency improvements, IC makers and consortia driving the transition to 450mm manufacturing expect to achieve similar or better environmental performance. Larger footprints and resource demands from 450mm facilities in conjunction with mandates for environmentally aware operations are compelling fabs and suppliers to consider sustainability and systems integration at greater levels than ever before. 

Experts in fab facilities, energy, water and equipment engineering will discuss the implications of 450mm to environment, health and safety during the SEMICON West 450mm Manufacturing EHS Forum on Wednesday, July 10.

Included in the presentations are perspectives from the Facility 450 Consortium (F450C) including Ovivo, Edwards and M+W Group.  A holistic Site Resource Model that provides semiconductor manufacturers visibility into effective reduction of total energy and water demands for individual systems, as well as for the entire facility will be reviewed by CH2M Hill. The model is an integrated analytical approach to assess and optimize a semiconductor facility’s thermal energy, electrical energy, and water demand, as well as the cost associated with these resources.

Also, the bigger, heavier and taller equipment envisioned for 450 entails new considerations for installation, movement and maintenance.  Making sure these issues don’t detract from the other cost saving achievements is a key consideration for facilities planning.  G450C representatives will review the status of component lift analysis currently underway. The solutions potentially alter fab facilities dimensions, tool engineering and service regimes.

450 TechXPOT

The SEMICON West 450mm Transition Forum covers the latest updates from those closest to the action.  The event occurs on Thursday, July 11 at the South Hall TechXPOT located in Moscone Center.  Paul Farrar, general manager of Global 450mm Consortium will provide an update and status on G450C. Hamid Zarringhalam, executive vice president, Nikon Precision, will review the challenges and status of 450mm lithography — which is shaping up to be one of the most uncertain yet critical 450mm planning considerations. Chris Richard, a partner at PricewaterhouseCoopers, LLC will talk about “Improving Semiconductor Equipment Vendor Profitability during the 450mm Transition.”

Then, SEMI will host a discussion among the world’s foremost 450mm tool experts from leading equipment companies.  The discussion panel will include: Kirk Hasserjian, corporate vice president, Silicon Systems Group, Applied Materials, Inc., Brian Trafas, Ph.D., chief marketing officer, KLA-Tencor; Mark Fissel, vice president, 450mm Program, Lam Research Corporation; and Akihisa Sekiguchi, Ph.D., vice president and general manager of SPE Marketing, Tokyo Electron Limited.  We have a few provocative topics to review with panel members.  If you have questions or topics you want addressed by those at the front line of the 450mm transformation, feel free to send us your suggestions.

In summary, a transformation will occur in IC manufacturing with the introduction of larger wafers, but it begins with serious engineering that is occurring now.  Attend SEMICON West to learn more about wafer specifications, EHS and facilities— considerations and business strategies for success and be better prepared for the numerous implications of 450mm era.

Learn more about it here: www.semiconwest.org. Register now at www.semiconwest.org/registration.

 

 

by Debra Vogler, SEMI

In advance of the 2013 SEMICON West TechXPOTs on lithography and nonplanar transistors beyond 20nm, SEMI asked some of the speakers and industry experts to comment on the challenges they wanted to highlight. Many of the inputs focused on the need for precision in the processes used to form transistors, as well as how EDA can contribute to mitigating variability.

Likely enhancements on the logic roadmap below 20nm are a move to FinFET, improved FinFET implementation, high mobility channel, and gate all around (GAA) structures, noted Adam Brand, senior director, Transistor Technology Group at Applied Materials. He told SEMI that, “The increased complexity of the FinFET, high mobility channel, and GAA devices in combination with continued scaling requires more precision in structure formation and improved materials to address structure formation and parasitic effects.”

The key steps for maintaining the structural integrity of the fin are precision etch, void-free STI fill, recess, and precisely tailored corner rounding through dummy gate oxidation. Dummy gate oxidation addresses the challenge of ensuring that electric fields can be avoided in the corner explained Brand, who will present at SEMICON West 2013 (http://www.semiconwest.org). “The dummy gate serves two purposes,” said Brand. “It’s a structural element and it’s there when you do the transistor formation so it can serve roles such as being the etch stop for the gate etch. It’s also able to play a role in shaping the fin.” The fin can be shaped by changing the oxidation rate depending on the amount of oxidation needed for the side vs. for the corner.

Precision again comes into play when forming the gate — precision CMP is required to control the dummy gate and replacement metal gate height. The dummy gate material must also be easily removed. “Advanced CVD materials offer more choices in materials for differentiating selective removal,” said Brand. “Implant-based precision material modification (PMM) has been effective in changing selectivity to obtain better structure control.” He noted that in the past, CMP had not played a role in directly affecting the geometry of the transistor, but now, it is playing a much more direct role in determining the size of the transistor features. For example, in the replacement metal gate step, CMP is used to polish the metals used for the replacement gate structure and it’s also used for the self-aligned contact polish. “So now, you’re polishing the gate at least three times in order to form it, and you need very precise gate height control because it affects the overall stack height and contact height.”

Further complicating transistor scaling is that the 3-D structure adds complexity in strain-related mobility enhancement. “Source/drain stressor shaping is needed to optimize strain and control unwanted increase in the Miller capacitance,” said Brand.  “Lower k dielectrics are also needed to manage the Miller capacitance.” He further explained that when strain is implemented in a FinFET, each source/drain area is a separate fin — as opposed to when strain is being implemented on planar devices. “When you grow the source/drain [in a FinFET], it grows both horizontally and vertically, so when you scale the pitch of the fins, there’s the challenge that eventually those source/drain stressors come very close to each other and they might merge.” The solution, therefore, has to allow the stressors to grow without having them merge between the transistors and still obtain the amount of strain that is wanted. The solution must also address the Miller capacitance. 

The SOI value proposition changes below 20nm

Gary Patton, VP at IBM’s Semiconductor Research and Development Center, told SEMI that in order for the full benefit of the FinFET to be realized below 20nm, a dielectric isolation scheme is necessary to counter the uniformity and variability challenges. “The arrival of the FinFET era has brought about a fundamental paradigm shift in the SOI value proposition such that the advantages of SOI-based innovation now extend well beyond just device performance as in the planar case,” said Patton.  Indeed, Soitec, and others, such as STMicroelectronics, are betting that SOI-based technology will be used as a bridge enabling the industry to get the performance benefits of a fully-depleted transistor while staying with a planar transistor all the way from 28nm down to 14nm, or perhaps even sub-14nm.

To those who question the added cost of going with an SOI-based platform, Patton said that the cost of dealing with the isolation challenge offsets the cost of using SOI substrates. “Offset costs are due to both additional process steps required for bulk, and increases to die area,” said Patton. “An STI isolation module must be added for bulk FinFETs, as well as a series of masking steps and implants for isolation-leakage control and latch-up avoidance. Estimated additional processing costs of bulk isolation offsets the cost advantage of bulk substrates over SOI.” He also pointed out that die area increases are driven by the need for well contacts, and I/O guard-rings (latch-up avoidance). “We also anticipate the overall die yield to be challenging for the bulk FinFET process due to variability and the need for matching performance of critical circuit paths in a chip.”

Another consideration for proponents of SOI-based technology is the issue of process variability. “A buried oxide layer (BOX) in SOI fins is responsible for three areas of improvement in variability over bulk-isolated FinFETs,” Patton told SEMI. “First, the top silicon layer is terminated by the buried oxide, is proven to be extremely uniform in thickness, and defines the height of the fin both physically and electrically, since any fin over etch does not contribute to the fin height.” He further explained that the source and drain are completely separated by the gated channel, unlike in a bulk FinFET, where there is a continuous path for leakage, requiring a highly doped punch-through stop.

“The non-abrupt nature of doping introduces a non-uniform doping profile, and hence, turn-on current, between the top and bottom of the fin, further eroding the FinFET advantage.” Patton noted that a more practical consideration is the slope or taper of the fin itself. “From an electrical point of view, the ideal fin would be perfectly vertical and of uniform thickness from top to bottom. In a bulk fin process, a degree of taper must allow for the subsequent oxide fill and etch-back, and also to accommodate a reduced spacer over-etch budget (vs. an SOI fin). The fin taper introduces further non-uniformity to the FinFET, which reduces switching speed.”

EDA tackles variability

Reducing/mitigating process variability is ever more critical to yield as the industry scales transistors below 20nm, and much can be done in the design arena to help. For example, EDA considerations can mitigate “noise” in the optical system [lithography] that is a source of variability.

Mike Rieger, group director, R&D, Silicon Engineering Group at Synopsys, uses communication theory to analyze certain aspects of a lithographic system. He told SEMI that when there are optical systems [lithography] without tuning, i.e., a “plain vanilla” system — all the spatial frequencies in the visible limit are present. Conversely, when the design is friendly to specific spatial frequencies and you then try to print that design with an optical system that is friendly to all spatial frequencies, there are other frequencies that leak through. This “leakage” causes a lowering of the contrast in the optical image. “With the lower contrast, the image is more susceptible to other sources of variation like defocused variation, or dose variation, and that translates into your printed features having more variation in their dimensions,” said Rieger, another speaker at the upcoming SEMICON West (http://www.semiconwest.org).

Rieger added that, if you can prevent the unwanted frequencies from even being passed through the optical system, the net result is that the contrast is improved. Additionally, by tuning these frequencies, the diffraction orders in the stepper (the rays of light used to form the image) are manipulated. “You can eliminate the zero order ray. This zero order ray reduces contrast and it also limits the maximum frequency that you can image.” The tuning process – also known as source mask optimization (SMO) – really isn’t the end game, noted Rieger. “It’s source design optimization that is the end game. You tune the configuration of your design to be consistent with the optimization of the source.”

Regarding the parallel paths the industry is taking – extending optical lithography while developing EUVL — Rieger is realistic in his assessment of what EDA can bring to the table. “We’re going to be using 193i for the foreseeable future — it will be years before 193i is replaced,” said Rieger. But, “Optical lithography on a single exposure is maxed out in terms of the density it can print, so if you want to get more transistors per chip or more details per chip, you must do a couple of things.” Those are: tuning the optics, which comes at a cost, and using multiple exposures. “To get an effective result, the whole process of the tuned optics and the multiple exposures must be comprehended in the physical layout software, and some of the things that need to be done go beyond what you can accomplish with the traditional rule-based constraint that you put on the layout.”

For more information on SEMICON West 2013, visit http://www.semiconwest.org. To view all the TechXPOT info, visit http://www.semiconwest.org/SessionsEvents/TechXPOTs.

Register through June 7 at only $50 here: http://www.semiconwest.org/registration. Note that registration fees increase on June 8.

 

Critical trends and developments in the technologies, methodologies, and applications challenges in semiconductor test will be presented at the 6th annual IEEE Test Vision 2020 Workshop held in conjunction with SEMICON West 2013, on July 10-11 at the San Francisco Marriot Marquis Hotel. The one and one-half day workshop will feature speakers from Flextronics, Broadcom, Qualcomm, Texas Instruments, AMD, ON Semiconductor, Mentor Graphics, Micron, along with those from key semiconductor test industry suppliers. Organized by SEMI and sponsored by the IEEE Instrumentation and Measurement Society, Test Vision 2020 is a two-time winner of the ATE Test Technology Technical Council’s “Most Successful Event” Award.  Registration for Test Vision 2020 is now open at www.testvision2020.com, and includes free admission to SEMICON West.

Test Vision 2020’s purpose is to facilitate learning, forecasting and debate on the future of semiconductor test and serves as a valuable platform where leading foundries, IDMs and fabless companies discuss their critical test requirements with leading test equipment and solution providers.  This year’s program will feature panel discussions and leading industry experts that focus on the following key questions:

  • How can we achieve faster time to market with lower product costs?
  • What are the Test challenges in emerging technologies?
  • How much Test is enough?
  • What are the possible paths to economical high-speed test?
  • What are the next big innovations in Semiconductor Test?
  • What will be the new skills and competencies needed by future test engineers?

The keynote speaker for Test Vision 2020 will be Dr. Erik Volkerink, chief technology officer at leading end-to-end supply chain powerhouse, Flextronics.  He will present on the topic, “Product Foundry: Next Paradigm in Product Design and Engineering.” Featured speaker will be Sri Jandhyala, Strategic Marketing Director for ON Semiconductor, whose presentation will be, “LED Lighting — Opportunities, Challenges and the Future.”  Leading test equipment and solution providers will also highlight the latest test developments and trends, including speakers from Advantest, LTX-Credence, Roos Instruments, and Teradyne.

Starting at 3:00 p.m. on Wednesday, July 10 and concluding at 4:45pm on Thursday, July 11, Test Vision 2020 will also include a networking and casual social event on Wednesday evening.

Several years ago when the challenges to 450mm wafer processing, EUV development and novel transistor designs were first being discussed, SEMI commissioned a study that predicted the industry could face an R&D funding gap that could exceed $9 billion if current technology and economic trends continue. At the time, SEMI issued a statement saying the industry was at a “crossroads” and “without significant attention to the R&D gap, the semiconductor equipment and materials industry will not be able to afford to keep up with Moore’s Law.”

technology forum

Much has happened since that report was issued: 450mm development was delayed, but now is ramping at G450C; Intel, Samsung and TSMC have invested over one billion dollars in ASML; cost targets have been missed at 28nm; and 3D-ICs have emerged as an alternative development path for leading-edge chip solutions.  But the R&D challenges remain.   The industry has responded in unexpected and unique ways, including new funding models, new consortia programs, increasing joint development agreements, and other mechanisms.  How R&D processes and strategies have evolved, and will probably continue to evolve, will be the subject of several programs at SEMICON West.

The most significant trend in R&D in the industry, and increasingly important to the supply chain, is the growth and changing role of R&D consortia.  Not long ago, the top research organizations served the advanced research needs of IDMs.  Today, equipment and material suppliers, EDA software providers, fabless chip companies, and other diverse organizations participate in consortia initiatives.  In the near future, there may be increasing involvement from system companies like Apple, Cisco, and Google.  Along with changes in participation, the types of research conducted by consortia have also evolved, many directly involving component and subsystem suppliers. Today, there are consortia that specialize in key areas like wafer size transition and lithography, but also many of their programs seem to overlap, potentially creating inefficiencies and redundancies in R&D efforts that consortia were supposed to eliminate.

Many of these issues will be discussed in a special executive panel on semiconductor R&D at SEMICON West.  On Wednesday, July 10, I will be joined on stage by Daniel Armbrust, president and CEO of SEMATECH; Michael Liehr, executive VP at CNSE; Dr. Laurent Malier, CEO of CEA-Leti; and Dr. Luc Van den hove, president and CEO of imec to discuss the critical trends and developments in R&D and how they will affect SEMI members.  We will discuss the important role of consortia and what’s new at their organizations, but also share our perspectives on the changing role of the R&D engineer and scientist in the industry today.  Increasingly, R&D is becoming more about managing complex multi-organization processes and innovation platforms than it is about pure research looking for the next “ah-ha” discovery.

Another critical R&D issue is the changing innovation pipeline delivered by technology start-ups.  In the past, the industry enjoyed a healthy ecosystem of emerging companies funded by venture capital that were ripe candidates for merger and acquisition.  Today, VC venture funding in the semiconductor industry is down nearly 50 percent from 2009 levels.  To help address this problem, SEMICON West will feature the first Silicon Innovation Forum (SIF) focused on new and emerging companies in the industry.  Organized by Applied Ventures, Dow Chemical Company, Intel Capital, Micron Ventures, TEL Venture Capital, and Samsung Ventures, SIF is designed to bridge funding gaps for new and early-stage companies by providing a platform to showcase new ideas to potential partners and investors.  SIF will consist of an open conference program on July 9 which is free to all SEMICON West attendees, followed by a reception and showcase for qualified investors.

The International Technology Roadmap for Semiconductors (ITRS) has been a critical component in the R&D planning process and SEMICON West will again feature presentations and discussions on the latest version.  The ITRS is undergoing a major change this year to reflect the market evolution towards highly-flexible mobile devices. Presentations include topics on system drivers, design, modeling and simulation, process integration, devices, and structures (PIDS), lithography, front-end processes (FEP), and emerging research devices (ERD). Back-end-of-line working groups will present challenges for future interconnects — such as through silicon vias (TSVs); the latest roadmaps for semiconductor assembly; systems packaging applications, “More than Moore,” and the testing considerations for these quickly changing technologies.  They will also discuss roadmap developments in micro-electro-mechanical systems (MEMS) and radio frequency and analog/mixed-signal technologies (RFAMS).  Look for these report-out sessions on the SEMICON West TechXpots on Thursday, July 11.

Other critical R&D topics that will be discussed at the SEMICON TechXPOT sessions are the latest developments in  lithography, processing requirements for non-planar transistors, 450mm wafer processing, advanced materials, and nano-defect metrology.  Unlike a conference with a variety of academic and special-interest topics, the SEMICON TechXPOT sessions quickly and succinctly provide the latest news and status from leading experts in the field, including “in the know” executives from organizations like ASML, Intel, GF, SEMATECH, G450C, ASE, ST Microelectronics and many more. In addition to their public presentations, TechXPOT speakers often make themselves readily available, providing suppliers and other stakeholders critical information on technology requirements and opportunities.

R&D engineers and scientists remain one of the most important audiences at SEMICON West.  Through private meetings with their top customers and suppliers, and through TechXPOT and other programs that deliver the latest developments in key areas of industry development, we think SEMICON West provides the most cost-effective and time-efficient value in the industry.  I hope you can join us.

For more information on SEMICON West and to register, visit www.semiconwest.org (free registration ends on May 10)

Dynamic changes to R&D processes, tools, technical challenges, and funding/business models will be highlighted at SEMICON West 2013, along with product displays of the latest semiconductor manufacturing technology, components and subsystems. SEMICON West, the Western Hemisphere’s largest micro- and nano-electronics exhibition and conference, will be held July 9-11 at the Moscone Center in San Francisco. The event will feature over 500 exhibitors, 50 hours of conference programs and more than 30,000 industry attendees.  Registration is now open at www.semiconwest.org without charge until May 15; registration fees apply starting May 16.

The semiconductor industry is simultaneously addressing the most complex challenges in its history: EUV lithography, new transistor architectures, stacked 3D-ICs, and 450mm wafer transition.  At the same time, adjacent markets in LED, MEMS and printed/flexible electronics are approaching technology crossroads — and new, post-CMOS alternatives to extend Moore’s Law are in the early stages of development.  Reconciling these multiple R&D demands are transforming old R&D strategies and accelerating new organizational models, skill set requirements, consortia options, partnership strategies, global sourcing tactics, and other approaches to managed innovation.

SEMICON West addresses these new R&D approaches through a variety of keynote presentations, panel discussions, technical presentations, and collaboration sessions including:

  • Silicon Innovation Forum: Organized by the industry’s leading strategic investment groups, this first-time forum provides a platform to connect new and emerging companies with strategic investors, venture capitalists and industry leaders.
  • Consortia Views:  For the first time anywhere, leaders from the industry’s top consortia — SEMATECH, imec and CEA-Leti — will share their views on collaborative R&D and the future of semiconductor technology.
  • Keynote Perspectives:  Ajit Manocha, CEO, GLOBALFOUNDRIES
  • Essential R&D Process Sessions:  Nano-Defect Detection and Lab-to-Fab Solutions
  • Latest Technology Updates:  Industry leaders will share the latest updates on lithography scaling and productivity, processing requirements for nonplanar transistors, 2.5/3D stacked ICs, and 450mm wafer processing.
  • ITRS Public Sessions:  The most critical technology innovation targets as identified the International Technology Roadmap for Semiconductors.
  • New Technology Sessions:  Learn about the latest R&D opportunities and challenges in LEDs, MEMS, printed/flexible electronics, silicon photonics, and more.

SEMICON West is the annual tradeshow for the micro- and nano-electronics manufacturing industries. Last year, over 30,000 attended the event and over 500 companies exhibited the latest innovations and solutions for advanced manufacturing.  For the sixth year, SEMICON West will be co-located with Intersolar North America, the leading solar technology conference and exhibition in the U.S. Every major semiconductor manufacturer, foundry, fabless company, equipment and materials supplier — plus leading companies in LEDs, MEMS, displays, printed/flexible electronics, PV, and other emerging technologies — attend SEMICON West.

SEMI is the global industry association serving the nano- and microelectronics manufacturing supply chains.  SEMI maintains offices in Beijing, Bengaluru, Berlin, Brussels, Grenoble, Hsinchu, Moscow, San Jose, Seoul, Shanghai, Singapore, Tokyo, and Washington, D.C. 

Karen Savala, president, SEMI Americas

August 10, 2012 — This year at the SEMICON West press conference, I presented on “Supply Chain Readiness in an Era of Accelerated Change” and I’d like to summarize that presentation for you.  The talk centered on the increasing capital and technology requirements of advanced semiconductor production and the pressures this creates on the supply chain. The structure of the industry is rapidly changing — and how it will respond to the simultaneous challenges of Moore’s Law scaling, 450mm wafer production, 3D-ICs, and industry consolidation is very much unknown.   Much of this uncertainty is reflected in what we call “supply chain readiness.”

Never before has the industry faced greater economic and technological uncertainty. The industry is consolidating, with fewer leading edge chip makers and fewer leading edge suppliers.  The technical challenges are increasing as geometric scaling and Moore’s Law now must be accomplished with rising process engineering complexity — particularly in the areas of EUV lithography, 3D-IC chip packages and 450mm wafers.

The economic and technical challenges of today’s environment will have an impact on supply chain readiness.  In the past, the size and scope of the industry supported a vibrant supply chain of start-ups, innovators at the leading edge, brilliant fast-followers, and a variety of technology and process specialists. 

Today, the supply chain is dominated by several large OEM companies who rely upon a global ecosystem of technology subsystem and component firms.  As process engineering becomes more complex at leading-edge nodes, the readiness of the supply chain to deliver advanced, integrated solutions becomes less certain.

 

EUV Lithography

Photolithography systems are among the most complex and expensive machines on the planet.  They are also the most important tool to maintain the pace of Moore’s Law.  From advanced light sources from Cymer to highly engineered optics and lenses from Carl Zeiss, approximately 90% of an ASML lithography system comes from external suppliers. EUV systems are currently shipping, but as you know, they do not meet the required wafers-per-hour throughout for high-volume production.  Consequently, EUV is being deployed in conjunction with immersion lithography, directed assembly and other options. The node at which EUV fully enters mass production is still uncertain — certainly below 20nm, perhaps at the 16 nm node, possibly at 8nm.

To alleviate some of this uncertainty, both Intel and TSMC have made significant investments in ASML to support EUV development and help accelerate the introduction of 450mm systems.  While this massive infusion of cash will assure a common mission between these key industry players, how it will impact next generation mask infrastructure has yet to be seen.

In mask readiness, EUV mask blanks are an order of magnitude more complex than today’s conventional mask blanks.  Spectacular work has been accomplished to improve yield and reduce defects on these new systems.

Today, according to SEMATECH, mask performance is sufficient to meet the needs of memory, but still short on meeting the requirements for logic.  More importantly, as this chart shows, you’ll see that a significant gap between EUV mask blank demand and supply capacity currently exists.  Uncertain EUV insertion will make investment difficult for suppliers to address this capacity shortfall before full production is assured.  This uncertainty may also threaten production volume availability for EUV resists.

 

 

3D-IC

3D-IC is another area of dramatic and uncertain change lies in the area of 3D-IC stacked chips.  Given their potential for smaller form factors, increased performance, and reduced cost and power consumption, 3D-IC technologies are now enabling the next generation of advanced semiconductor packaging.  Already, 2.5D approaches using silicon interposers to provide wide IO bandwidth and denser packaging have been introduced, but many manufacturing and collaboration barriers remain before widespread commercialization. 

3D integration using through-silicon vias promise a fundamental shift for current multi-chip integration and packaging approaches.  But cost-effective, high-volume manufacturing will be difficult to achieve without standardized equipment, mat䁥rials, and processes.

With many advanced packaging processes taking place on the semiconductor wafer, the traditional supply chain of “front-end fab at the foundry” and “back-end fab at the packaging and test house” is at risk of falling apart. TSMC has been clear about their vision. They want an   expanded role in the industry to implement — not just wafer foundry services — but 3D integration as well, including thinning, bumping and assembly.

While the business models sort themselves out, there remain technology challenges and process flow uncertainty.  Chips-on-substrate, chips-on-wafer and chip-on-chip all remain viable options. 

Currently, there are no collaboration models to solve this foundry-OSAT-IDM and fabless chip matrix for complex, multi-chip packages.  SEMI standards are addressing many supply chain, equipment and materials issues. However, market demand and business models must continue to sort themselves out before 3D chip stacking can widely penetrate the industry.

 

450mm Wafer Transition

The most expensive semiconductor industry technology transition in history will occur with the transition to 450mm wafers.  R&D costs alone are estimated to rise between $8 and $40 billion, depending on the efficiency with which the transition is coordinated.  The high end of this estimate represents a level of investment that is equivalent to what the entire industry spent on advanced process development over the past five years.  These costs will be incurred concurrently with other major technical challenges in the industry, including the move to 3D transistor structures, and EUV and 3D stacked chips already mentioned. The recent investments in ASML by Intel and TSMC reflect just how much the industry will be changed by 450mm development requirements. 

Currently, the Global 450 Consortium, or G450C, with members from Intel, IBM, Global Foundries, TSMC, and Samsung, is in the process of constructing and equipping a 450 pilot line in New York.  G450C has said that it expects the line to complete by mid- 2013 to early 2014. The business model to equip this pilot line is unlike anything we’ve seen before — in this industry or elsewhere!  The pilot line will feature approximately 50 tool types, most if not all, from no more than two vendors.  Performance data from this pilot line will be used to qualify equipment purchases for high-volume production equipment.  To many, it is clear that to participate in future 450mm production, equipment suppliers must participate in the pilot line.

However, not all vendors are being asked to participate, and for those that do, the terms for participation in the pilot line are daunting.  How the industry will pay for and recover the massive R&D cost has not been resolved.  Suppliers must weigh a decision to participate in pilot line development in conjunction with the possibility of not being qualified for production equipment orders from the world’s top chip manufacturers.  The timing and quantity of these of these potential future orders are also not known. 

These are difficult and complicated negotiations and decisions for the industry’s leading OEMs.  They are even more complicated and difficult for the remainder of the supply chain. 

While our leading equipment suppliers must sell products and services to chip manufacturers, many of the component and subsystem suppliers do not; they often serve multiple industries. 

As the current collaboration model unfolds for 450mm development, its impact on a variety of technology suppliers — many of them exhibitors at SEMICON West — is uncertain. Approximately 90% of ASML’s components and subsystems are provided by outside suppliers.  Another example, Applied Materials is dependent on 800 suppliers worldwide, with 75 prime strategic suppliers representing 80 percent of their annual procurement allocation. 

On the transition of the industry to 450mm wafers — it is certain that the impact on the supply chain will be disruptive and significant. While it appears that G450C may be the primary path of coordination for the scale-up of wafer process tools, it is the OEMs that will be coordinating a complex multi-layered supply chain of component and sub-assembly providers.  At SEMICON West for the first time, the major process tool makers communicated requirements and expectations to the larger group of supply chain participants that may not have direct access to the consortia pilot line.

 

SEMICON West 2012

At SEMICON West, the most knowledgeable and authoritative voices in the industry discussed these tough issues.  Our objective is advance the dialog — to convey useful information to our attendees — and to serve as a platform for productive collaboration on these and other industry issues.  All of the events at SEMICON West (keynotes, partner events, TechXPOTs, and technical presentations) allow key industry stakeholders to discuss where it makes sense to collaborate — and where it’s best to compete.

 

Please let me know if you have comments or questions at [email protected].

 

Karen Savala

SEMI

www.semi.org

July 16, 2012 — SEMICON West kicked off with a surprise announcement regarding Intel’s strategic investment into ASML, but generally the event highlighted trends “as expected” in the semiconductor manufacturing supply chain, say Barclays Capital analysts.

Most semiconductor production equipment makers are seeing an order/shipment pull-back in Q3. Rising capital intensity, chip manufacturing complexities, Intel’s march to 14nm, and foundry’s 20nm investments contribute toward Q4 and 2013 capex optimism. Barclays investigates this trend further in Q3 semiconductor tool capex pull-back: Seasonal, expect Q4 uptick

Seasonality is now indeed winning over cyclicality, with Q3 drifting into a lull as it did in 2011 and 2010. Consensus estimates clearly are going to move lower given the cautious tone and the expectations for a near term pause in order.

Barclays is maintaining its wafer fab equipment capex estimate for 2012 at $31.5 billion (flattish over 2011) and for 2013 at $31.5 billion to 34.5 billion (flat to +10% over 2012).

Barclays is also keeping its lithography tool forecast for 2012 intact: immersion lithography demand is holding up with the lack of extreme ultraviolet (EUV) availability. Expect KrF lithography spending to taper in H2 2012.

SOC test is also going to taper in H2, but still tracking to be about $2.6 billion capex in 2012.

The surprise 450mm/EUV lithography tie up between ASML and Intel made a splash at SEMICON West. According to Bloomberg, sources reported that Samsung Electronics Co., Ltd. and TSMC are in talks to acquire about 10% stake in ASML as well. Look for more analysis on blogger Dick James’ page, in The Elephant Has Left the Room — 450 mm is a Go!

Intel continues to be the main driver of 450mm adoption, which could benefit more than ASML (look for Edwards Vacuum to also support the 450mm transisiton at Intel sometime in the 2018/2019 timeframe).

Cymer continues to the leader within the group of lithography light-source contenders, with Extreme/Ushio still experiencing reliability issues with its IMEC source and Gigaphoton yet to assemble an integrated source, Barclays concludes.

Read the full report at http://live.barcap.com/PRC/servlets/dv.search?contentPubID=FC1838914&bcllink=decode

Visit the Semiconductors Channel of Solid State Technology!

July 13, 2012 — Terry Brewer, one of the newest members of SEMI’s North American advisory board, talks about semiconductor industry consolidation, as well as new technologies and materials in the industry. He shares how SEMI is reacting to this evolution.

Brewer, president and founder of Brewer Science, speaks with Pete Singer, chief editor, Solid State Technology, at SEMICON West 2012 in San Francisco. See all the news and interviews from SEMICON West here!

 

July 13, 2012 — Barclays Capital Inc. analysts held conversations with the light-emitting diode (LED) supply chain at SEMICON West, this week in San Francisco, CA. The show confirmed for Barclays that Q2 2012 orders for metal organic chemical vapor deposition (MOCVD) tools remained flattish with the trough-like Q1 numbers.

Top MOCVD suppliers Veeco and Aixtron confirm that activity is picking up into H2 2012. Sub-component suppliers to the MOCVD makers, as well as adjacent LED equipment suppliers, are anticipating gradual order growth in Q3 and Q4 2012.

Key accounts that are in the process or on the cusp of placing orders in the remainder of 2012  include Sanan and 3E in China, Toyoda Gosei and Showa Denko in Japan, a little bit of Epistar in Taiwan exiting the year, and likely Samsung in Q4 for equipment installation in 2013. Additionally, Nichia also appears to be actively ramping capacity, though this will not benefit Veeco or Aixtron, given Nichia’s internal tool production.

Barclays Capital estimates that MOCVD chamber shipments will pick up from 67 in H1 2012 to 80 in H2. The risk to MOCVD orders comes from the hard disk drive (HDD) sector, and how much it decelerates in H2, though service should provide a buffer here.

Get the full report from Barclays at http://live.barcap.com/PRC/servlets/dv.search?contentPubID=FC1838394&bcllink=decode

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