Category Archives: Semiconductors

North America-based manufacturers of semiconductor equipment posted $1.33 billion in orders worldwide in June 2013 (three-month average basis) and a book-to-bill ratio of 1.10, according to the June EMDS Book-to-Bill Report published today by SEMI.   A book-to-bill of 1.10 means that $110 worth of orders were received for every $100 of product billed for the month.

The three-month average of worldwide bookings in June 2013 was $1.33 billion. The bookings figure is 0.7 percent higher than the final May 2013 level of $1.32 billion, and is 6.6 percent lower than the June 2012 order level of $1.42 billion.

The three-month average of worldwide billings in June 2013 was $1.21 billion. The billings figure is 1.4 percent lower than the final May 2013 level of $1.22 billion, and is 21.4 percent lower than the June 2012 billings level of $1.54 billion.

“The SEMI book-to-bill ratio has been above parity for six consecutive months and bookings in the quarter ending in June are 20 percent above the quarter ending in March,” said Denny McGuirk, president and CEO of SEMI.  "As recently announced, we anticipate that total worldwide equipment spending will decline by low single-digits this year and rebound with a double-digit growth rate in 2014.”

The SEMI book-to-bill is a ratio of three-month moving averages of worldwide bookings and billings for North American-based semiconductor equipment manufacturers. Billings and bookings figures are in millions of U.S. dollars.

 

Billings 
(3-mo. avg)

Bookings
 (3-mo. avg)

Book-to-Bill

January 2013

968.0

1,076.0

1.11

February 2013

974.7

1,073.5

1.10

March 2013

991.0

1,103.3

1.11

April 2013

1,086.3

1,173.9

1.08

May 2013 (final)

1,223.4

1,321.3

1.08

June 2013 (prelim)

1,206.8

1,329.9

1.10

Source: SEMI, July 2013


The data contained in this release were compiled by David Powell, Inc., an independent financial services firm, without audit, from data submitted directly by the participants. SEMI and David Powell, Inc. assume no responsibility for the accuracy of the underlying data.

SEMI is the global industry association serving the nano- and micro-electronic manufacturing supply chains.. SEMI maintains offices in Bangalore, Beijing, Berlin, Brussels, Grenoble, Hsinchu, Moscow, San Jose, Seoul, Shanghai, Singapore, Tokyo, and Washington, D.C. For more information, visit www.semi.org.

A new generation of thin hard disk drives (HDD) only 5.0 and 7.0mm thick are expected to enjoy fast sales growth in coming years, as mobile computers including ultrathin PCs and PC tablets drive up demand by a factor of more than 25 from 2012 to 2017.

The combined shipments of 5.0- and 7.0-millimeter HDDs used in mobile PCs will reach 133 million units by 2017, up from just 5 million last year, according to a Storage Space Brief from information and analytics provider IHS (NYSE: IHS).

Lighter in weight and thinner in breadth, the 5.0- and 7.0mm models will form a new class of ultraslim HDDs that are forecast to eventually displace the much thicker 9.5-mm drives that currently rule the industry. Shipments of the thicker 9.5-mm HDDs for mobile PCs will deteriorate to 79 million in 2017, down from 245 million units in 2012.

Both the 5.0- and 7.0-mm HDD products will see increasing adoption starting this year, along with another form of storage device known as the hybrid HDD, in which a NAND flash component or so-called cache solid-state drive (SSD) is joined with the hard drive within a single storage enclosure.

“Use of these new thin HDDs and hybrid HDDs will proliferate because these devices are smaller in size and have the capability to improve overall storage performance— important variables in an age that emphasizes smaller form factors as well as optimal speed at affordable prices,” said Fang Zhang, storage systems analyst at IHS. “Both the thinner HDDs along with hybrid HDDs could even start finding acceptance in ultrathin PCs and tablet PCs—two products that now mostly use solid-state drives as their storage element. Hard disks have lost market share to SSDs, which offer better performance and can be more easily used to achieve a thinner and lighter form factor crucial to tablets and ultrathin PCs.”

This year, for instance, the total SSD shipments will climb nearly 90 percent to 64.6 million units, while HDD shipments will decline 5 percent to 545.8 million units. However, the new and thinner HDDs eventually could stem losses of the hard disk space, especially if their costs can fall to 10-15 percent of a tablet or to 10-20 percent of an ultrathin PC, IHS believes.

These cost thresholds are important because they could be instrumental in persuading tablet and ultrathin PC brands to consider 5.0- and 7.0-mm. hard disks as possible alternatives to the SSDs now used as the predominant storage element. Solid-state drives are relatively expensive at present compared to other storage types and cut into the overall margins of computer and tablet makers, so the use of more economical storage alternatives that boost the bottom line of makers would make a persuasive argument to undertake a switch.

HDD manufacturers jump into the fray

All three manufacturers of hard disk drives—U.S.-based Western Digital Corp. and Seagate Technology, as well as Toshiba of Japan—will have their own product offerings for the new and thinner HDDs.

Western Digital fired the opening salvo in April, announcing it had started shipping the 5.0-mm WD Blue ultraslim HDD and the Black SSHD—a solid-state hybrid drive with a hard drive component alongside the cache SSD—to select industry distributors as well as original equipment manufacturer customers.

Western Digital claims that the 500-gigabyte capacities of the two models will reduce weight by as much as 30 percent compared to a 9.5-mm HDD, with a circuit board utilizing cellphone miniaturization technology able to maximize the mechanical sway space in the hard drive to ensure shock resistance.

Western Digital then announced in June shipments of the world’s currently thinnest 1-terabyte drive—the 7.0-mm. WD Blue—with both Acer and Asus likely to use the product in their upcoming ultrathin PCs.

For its part, Western Digital archrival Seagate announced also in June it had shipped 5.0-mm HDDs to Asus, Dell and Lenovo for their ultrathin PCs for the second half of 2013. Seagate says its 500-gigabyte hard drive occupies 25 percent less space than the company’s 7.0-mm HDD.

Reacting to the developments from Western Digital and Seagate, Toshiba said it would ship a 7.0-mm solid-state hybrid drive (SSHD) in 320- and 500-gigabyte configurations, likewise by the end of June.

Previously, Toshiba only had a 9.5-mm SSHD of up to 750 gigabytes.

In 3D integration, wafers are thinned, stacked and connected to one another with through silicon vias (TSVs). The process of wafer thinning and TSV formation typically involves the use of a wafer bonding/debonding technology, where the wafers are bonded onto a carrier substrate – either silicon or glass – processed, and then debonded. The bonding/debonding step can be tricky because the bond has to be strong enough to withstand relatively high temperature processes and polishing steps, but not so strong as to make debonding difficult. It’s also critical that minimal stress be introduced to the device wafer during the debonding step (which can involve sliding or peeling), and that no residue remain. Room temperature debonding is also desirable.  

A variety of techniques and materials have been developed to successfully achieve bonding/debonding, but Tony Flaim, chief technology officer of Brewer Science (Rolla, MO) says they are still too complicated. Brewer Science introduced the ZoneBOND technology in the 2008/2009 timeframe, and it has been implemented by tool suppliers such as EVG and SUSS. In an interview at The ConFab in June, Flaim said: “This is one of the industry’s first methods for separating the carrier from the bonded pair under low stress, low temperature conditions. It can be done at room temperature. We’ve had customers adopt that technology and are using it for some low volume production.”

High volume manufacturing of 3D integration with TSVs might not occur for another two years. To date, TSVs have been primarily used in limited applications such as image sensors where back-to-front contact is required. The first true stacked, 3D integrated device to go into production will likely be the Hybrid Memory Cube sometime next year.

“The industry is at best in low volume production with things like high density interposers and a few stacked devices, but for the most part we really haven’t seen anyone going into high volume manufacturing with the technology,” Flaim said.  “What we’re trying to do, until that time arrives, is move on to a third generation of technology that will basically involve all the steps in the process and simplifying more than they are now.” He said that with ZoneBond and competing technologies, they have six basic process steps, but at a more detailed level, you can see as many as 20-25 steps. “Some of those steps are lengthy, they can be minutes or even up to hours in some cases to perform. We believe that for temporary wafer bonding technology and in fact for 2.5D and 3D integration to occur, we’re going to have to have a much simpler, more reliable, more cost-effective process. That’s really our goal for the next two years,” Flaim said.

In terms of ideal process temperature, Flaim said the bulk of their customers are working in the range of 250-260°C, but it’s clear that they want to go higher. Dielectric cure processes and deposition processes, for example, would yield better material properties when performed at a higher temperature.  “We’re trying to move our whole materials set to have thermal stability at 280, 300°C or maybe even beyond. But the trick is still getting them back apart. That’s where ZoneBond and some of the other release technologies that we’re working on now will really provide the advantage.  You decouple the thermal stability from how you separate from the stack. You can still be operating under a low stress, low temperature condition when you take the bonded structure apart, but the materials within the structure are surviving the high temperature.”

See the video interview of Tony Flaim at The ConFab by clicking here.

Zvi Or-Bach, President & CEO of MonolithIC 3D Inc. blogs about an ASML presentation from Semicon West. This is a follow up to a previous post: "Dimensional Scaling and the SRAM Bit-Cell."

I just downloaded the ASML presentation from Semicon West2013 site – ASML’s NXE Platform Performance and Volume Introduction. Slide #5  – IC manufacture’s road maps – says it all.

Embedded SRAM will scale from 0.09µm² at 22-20nm node to 0.06µm² at 11-10nm node. In other words only 30% reduction instead of the 4x reduction expected of historical dimension scaling, to roughly 0.02µm² !!!

In our previous blog that followed ISSCC 2013 we saw some early indication of this slowdown.  Yet we were still surprised to realize how bad it really is. This might explain why after resisting IBM and other pushes for embedded DRAM, Intel announced few month ago that its Haswell processor will incorporate embedded DRAM after all.

Another point from this ASML slide is the adaption of monolithic 3D by the NAND Flash vendors. We believe this is a start of a trend, and that logic vendors has now one more reason to follow it.

DAS Environmental Expert GmbH of Dresden, Germany, has developed SALIX, a point-of-use system for removing waste gas pollutants in semiconductor wafer manufacturing wet bench applications. This solves a common problem where gases from the solvents, acids and alkaline materials used in wet processing combine to form a powder in the exhaust line. This powder can be a “toxic bomb” according to Dr. Horst Reichardt, CEO and president of DAS, or at least cause throughput and cost issues since the exhaust may have to be cleaned every one to two days.

The single-wafer cleaning process widely used for cleaning 300-millimeter wafers in wet benches distributes cleaning agents onto rapidly spinning single wafers and spins them off at the edge where baffle plates within the system collect the water, acidic and alkaline chemicals, and volatile solvents (the process for cleaning 200-millimeter wafers immerses the entire cassette). A large fab may have 20-30 such wet benches. With up to 12 stations per wet bench and exhaust from each chamber requiring several exhaust systems, the SALIX scrubber eliminates the need for elaborate change-over modules to avoid deposition in the pipes. It is more cost-effective and efficient at preventing clogging than conventional approaches used to separate and extract the acids, alkalines and solvents in the exhausts which require separate suction to prevent particle buildup and condensation within the pipes.

In contrast, SALIX removes the harmful substances from the gas stream directly at their point of origin using a two-stage scrubber process of chemical and physical absorption, and can treat up to 3600 m3/h of raw gas. Separate inlets feed the harmful gases from the wet bench process chambers into a SALIX pre-scrubber that pre-cleans the gas using spray nozzles. Next the waste gases pass into the first scrubber stage and then a second stage that uses a different scrubbing liquid. The remaining clean gas then can be released safely into the air without any danger to the technology or the environment. Because the SALIX system does not require any air dilution, the clean air remains in the clean room, further reducing cost.

Dr. Guy Davies, director of the Waste Gas Abatement business unit at DAS Environmental Expert explained, “When a global foundry based in Taiwan came to us seeking a better solution to treat water-soluble exhaust gases from a wet bench application, we installed SALIX as a first-of-its-kind point-of-use system. It has been running there since January of this year and, after six months of operation, emissions measurements show zero harmful substances in the exhaust. One SALIX system per wet bench is all that’s needed, and just one pipe for the cleaned exhaust. Salix “offers a smaller footprint with no switching boxes needed, and is far more cost-effective and efficient than central scrubbers for treating processes that create water-soluble waste gases. We believe our proven SALIX solution, which is SEMI S2 international and German TA-Luft standards compliant, opens new markets for point-of-use scrubbers in the semiconductor, LED, PV and FPD industries. In fact, we have seen increasing interest in SALIX and already have received multiple inquiries from U.S. customers. In addition, we are using the evaluation results for further process-based optimization and have developed a custom fit bypass function that will enable production to continue with no interruption.

DAS also announced it has added Technica, U.S.A. as a new local service partner to deliver faster response time for service and maintenance for U.S. customers.

Engineering samples of The Hybrid Memory Cube (HMC) are expected this summer, with high volume manufacturing coming next year. It will be one of the first high volume devices employing 3D integration and through silicon vias (TSVs), employing a bottom logic layer and 4-8 stacked DRAM layers.

The HMC is the result of a consortium formed in late 2011 by Micron, Samsung, Altera, Xilinx and Open-Silicon to define an industry interface specification for developers, manufacturers and architects of high-performance memory technology. The consortium has grown to 110 members, including SK Hynix, IBM and ARM. Analysts are projecting the TSV-enabled 3D market to be a $40billion market by 2017, or roughly about 10% of the global chip business.

We caught up with Micron’s Scott Graham, General Manager, Hybrid Memory Cube, at Semicon West. “Today, we’re very close to delivering our engineering samples this summer to our lead customers that are taking the technology into their system designs,” Graham said.  The lead applications are in high performance computing, such as supercomputers, as well as the higher end networking space. “Those will be the early adopters. As we move forward in time, we’ll see that technology evolve as costs come down for TSVs and manufacturing technology, it will enter into future space where traditional DDR type of memory has resided. Beyond DDR4, we can certainly see this of memory technology being a mainstream memory,” Graham said.

Since the HMC is an open specification in terms of the architecture of the device, it will be up to each memory manufacturer to decide how it might be customized and manufactured. “The way it’s done today is we source the substrate, we source the logic layer and then we bring those in-house and we complete the finishing of those logic wafers as well as all the slicing, dicing, stacking, assembly and test,” Graham said. “What we end up providing for the customer is a known good cube, or known good piece of memory, just like we would if it was a DDR device or wide I/O device,” he said. He added that the HMC is designed so that it has not only the repair capability during manufacturing but also out in the field. “It’s very flexible and very robust, so reliability is very high with this device,” he said.

The consortium delivered its first specification earlier this year. “We’ve since extended the consortium to work on both future generations of the HMC technology in both the short-reach and ultra-short reach configurations,” Graham said.

The HMC was designed to get high density and high bandwidth in a relatively small package. The team adopted an off-the-shelf SERDES I/O and that’s based on IBM’s 32nm process. “With that, we can achieve 10 Gbps, 12.5 Gbps, or 15 Gbps for those SERDES links,” Graham said. “If you look at a 2 GByte or a 4GByte HMC device, those first devices will deliver a total aggregate bandwidth of 160GBytes/sec. I want to emphasize those are bytes not bits. It’s a very high bandwidth and low energy per bit device that is something that can be designed into a multitude of systems.”

The consortium has several generations of the HMC device planned (this summer’s engineering samples are Gen2). “As we move forward, you’ll see us moving into the 28 Gbps SERDES as far as the I/O goes,” Graham said. Bandwidths are going to be 320 Gigabytes/sec and higher, and the density will be in 4Gbyte and 8 Gbyte configurations.

Graham said one of the main challenges they had to overcome was the stacking. “We’re stacking a logic layer on top of a substrate and then four to eight DRAM on top of those logic layers,” he said. “We have over 2000 TSVs in this package and it was a challenge to stack these ultrathin die and make sure that what we end up with is a high performance and very reliable package.” Graham declined to comment on the exact TSV process flow used at Micron, saying only that it was leading edge. “We had to make sure our equipment partners were up to speed and could deliver us the technology that would allow us to manufacture this in high volume,” he said.  

Because customer can customize the HMC design, another challenge it to make sure that the design capabilities are available at the foundry for that logic layer, Graham said.  

Heat dissipation in the device is achieved through a metal lid, and through the TSVs which acts as chimneys (in addition to conducting electricity). The photo shows two Gen2 HMC devices. The larger one, in a 31mm x31 mm package, is a 4 link device that will achieve 160 Gig-bytes per second. The smaller one is a two link device capable of 120 Gigabytes/sec, measuring 16mm x 19.5 mm. “Both are being manufactured now in our plant and we’re doing the whole debug phase,” explained Aron Lunde, program manager, DRAM solutions group at Micron in Boise. He said the metal lid was in contact with not only the top layer, but different internal layers. “We call it an integrated heat spreader. It makes contact at more than one level and that’s what really helps,” he said.

Although manufacturers such as Micron, Samsung and SK Hynix must now handle the manufacturing, assembly and test process, Graham believes that it could eventually evolve to the point where select foundry partners would be able to provide volume manufacturing services for these HMC cubes.

Graham said DDR4 will likely be the last DDR device. “Beyond DDR4, you have to move to managed memory like HMC technology,” he said.  “We’re solving the memory wall problem with HMC-like architecture and what’s really going to be happening in the future is that you’ll be running into a CPU wall. That’s going to be the barrier to system progress as we move forward.”

Graham expects some challenges with scaling of conventional memory at sub-20nm process nodes. “We get into physical challenges of meeting the timing requirements and the 12 pages of JEDEC specifications to be able to yield properly and to be able to provide a cost-effective memory device moving forward,” he said.  

Although the HMC is now designed around DRAMs, Graham said it would be possible to use other types of memories, and even a mixed set of memories. He noted Micron is looking at alternatives to the conventional DRAM cell, such as spin torque and resistive memories. “Micron is investing heavily in research in those technologies and of course the HMC team here at Micron is looking at future technologies that we can take HMC architecture and be able to utilize different DRAM or even flash types of memory,” he said. “As the technology matures and it becomes lower cost, we can see this technology certainly evolving into more global applications and utilizing different memory types in that stack – and perhaps even multiple memory types in that stack.”

HMCs could eventually make their way into mobile devices, but Graham said that is likely to be three or four years away. Mobile applications presently employ low power DDR3 solutions, which will be used for several years. “We’ll see quite a few interesting designs start spinning when the mobile folks see they can differentiate with a managed memory solution. It’s not going to be HMC as we know it today, it will have to be optimized for mobile,” Graham said.

Executives from the world’s leading microelectronics companies will meet with delegates representing Vietnamese government, academia, research, and industry to explore and discuss the key strategies and opportunities in the growing Vietnam semiconductor industry at the SEMI Vietnam Semiconductor Strategy Summit. The Summit will be held on September 9-10 at the InterContinental Asiana Hotel in Ho Chi Minh City. The event includes an optional tour of the Saigon Hi-Tech Park where Intel’s assembly and packaging plant is located, followed by a one-day executive conference and networking event.

Following Intel’s successful $1 billion in manufacturing investment in Ho Chi Minh City, and the government’s recent decision to invest in a 200mm/0.18 micron front-end fab, Vietnam will become an alternative design and production location for electronics and semiconductor manufacturers in Southeast Asia.  The executive event will bring together the key decision-makers shaping the future of the industry in Vietnam and help forge the connections and relationships that will drive further growth over the next decade and beyond.  A featured presentation will provide perspectives on infrastructure and technology requirements for the new 200mm fab presented by executives from M+W and FabMax.

While both the Vietnamese and Ho Chi Minh City governments have made investments in both front-end and back-end semiconductor manufacturing a priority, advancing the semiconductor industry in Vietnam will also require development of the local supply chain, allocation of water and energy resources, a growing skilled workforce, partnerships with established microelectronic markets, and other infrastructure needs.

The SEMI Vietnam Semiconductor Strategy Summit is organized by SEMI and co-organized by the Saigon Hi-Tech Park (SHTP) and the Ho Chi Minh City Semiconductor Industry Association (HSIA). Participation in the SEMI Vietnam Semiconductor Strategy Summit is available exclusively through corporate sponsorship or by invitation.

Current sponsors include Kulicke & Soffa, Millice, KLA-Tencor, Disco, Advantest, and FabMax.  Several sponsorship categories are provided that offer different levels exposure and benefits.  For additional information on corporate sponsorships and to inquire about an invitation, please contact [email protected] or visit www.semi.org/vietnam

Smart lighting is an advance technology in lighting that makes use of intelligent lighting control systems to intelligently control light based on various parameters like occupancy, movement, color temperature, amount of natural/daylight etc. Smart lighting market is growing at a phenomenal way and main drivers for this growth are energy efficiency, development in electronics and sensor technology, eradication of incandescent lamps, favorable government policies and evolution of novel wireless technology. Entry barriers are low for this market and many new players are arriving in this market. For example: the smart lighting market in the U.S. is being dominated by start-ups that are just three years old. In the present scenario, many companies are launching new products in the market. It can be observed that LED-based products which are based on wireless technology are being launched at a large scale at present.

At present, Europe has the largest market for smart lighting especially in commercial industrial buildings, outdoor lighting, and automobiles applications. The presence of lighting giants like Philips (The Netherlands), Osram Gmbh (Germany) and Zumtobel AG (Austria) is an important reason behind the implementation of smart lighting system in this region. Smart lighting has the second largest market in North America. Several new players have emerged in this region, especially in the U.S., who has developed breakthrough products related to smart lighting. APAC is the emerging market for smart lighting. It is believed that market will grow at an exponential rate of 37.7 percent between 2013 and 2018.

Commercial and industrial buildings are the most prominent application of smart lighting. In commercial buildings, lighting adds up to 40 percent of total energy cost. Deployment of intelligent lighting control is being supported by building owners, governments, utilities, and many other stakeholders as it helps to drastically reduce energy consumption. Public and government building have the second largest share among all application in the smart lighting market. As smart lighting projects for public and government buildings are government-funded projects, the growth of this application area will be stable as it would be given priority in every economy. Residential buildings application has largest growth potential and will grow at the highest CAGR of 87.5 percent from 2013 to 2108 when compared with other application. Initial investment will pose as a restraint initially, however it is predicted that once the customers become aware of the energy savings benefits of intelligent lighting system in the long run, it will grow exponentially. Outdoor lighting application is another promising application. The greatest opportunity area in this market is the prospect of its integration with other important systems in the city like traffic signals, energy meters, pollution sensors, parking-lot lights, and traffic sensors to form a smart city. Smart lighting systems are mainly employed by high end cars. Companies like Mercedes-Benz and Audi have already incorporated the systems in their luxury cars.

 

With most of the top brands introducing new flagship models in the first half of 2013, smartphone buyers now have more choices than ever, a phenomenon that will contribute to an expected doubling in market shipments from 2012 to 2017.

Worldwide smartphone shipments will reach 1.5 billion units in 2017, up from 712 million in 2012, according to a new Mobile & Wireless Communications Report from information and analytics provider IHS Inc. Shipments this year are set to rise to 897 million units, up from 712 million in 2012, as shown in this figure.

In the years that follow, shipments of smartphones will expand at a compound annual growth rate (CAGR) of 15.8 percent, reaching 1.1 billion units in 2014, followed by 1.2 billion in 2015, and 1.4 billion in 2016.

“The volume of new flagship smartphone releases from top original equipment manufacturers (OEM) this year has been astounding,” said Wayne Lam, senior analyst for consumer and communications at IHS. “These include the new BlackBerry Z10, the aluminum uni-body HTC One, and an update to the Samsung Galaxy S4 featuring a Full HD 5-inch active matrix organic light emitting diode (AMOLED) display.”

On the other hand, Apple’s iPhone franchise appears to be stalling as first-quarter shipments of 37.4 million fell below expectations. With the next iPhone model not expected until the second half of the year, there is a real possibility that the full-year 2013 sales volume of the iPhone may be essentially flat at around 150 million units, compared to 134 million units in 2012.

“The possible slowing growth of the iPhone and the rapid pace of competitive smartphones releases speak to the ferocious nature of the handset business, especially now as the market continues to pivot from a market dominated by lower-end handsets known as feature phones to one that is increasingly smartphone-centric,” Lam said.

Outshipped

The trend of deeper smartphone penetration continued in the fourth quarter of 2012 and the first quarter this year, as smartphones outshipped feature phones in the overall branded cellphone market.

After a seasonally high fourth quarter, which saw total mobile handset shipments topping 400 million units for the first time, handset shipments in the first quarter of 2013 contracted by nearly 50 million units quarter-over-quarter, keeping with seasonal sales trends.

Samsung continued its strong growth in the first quarter with a sequential increase of 9 million units, while  brands such as Coolpad and Gionee outshipping the likes of HTC and Motorola in the first quarter.

Chinese smartphone OEMs were able to accomplish such growth on the back of a catalog of largely affordable smartphones, while Samsung rolled out a number of low-cost variants to its high-end flagship products.

These competitive forces, as well as changing consumer demand, will place pressures not only on Apple but also on other OEMs, IHS believes, forcing players to innovate and diversify smartphone offerings in order to continue growing.

Just innovate

Innovation in smartphone design is becoming a necessity for OEMs as consumers demand more immersive user experiences and visual content. Many smartphones, for instance, are moving to 5-inch or larger full HD displays to accommodate consumer desire for these experiences.

In parallel with an expanded display, the overall footprint of smartphones is likewise increasing because of larger batteries, which will then allow for more powerful processors, associated memory and sensors.

But these expanded features come at a cost to OEMs, driving up the dollar content of electronics and pushing the bill- of-materials (BOM) cost for the devices. Still, as variations in smartphone designs increase, opportunities to win design slots multiply as well for component suppliers—developments that bode well for the overall smartphone supply chain.

The latest trends, challenges and business opportunities in advanced materials for semiconductors, MEMs, power devices, storage, and other electronic devices will be addressed at the 2013 SEMI Strategic Materials Conference (SMC), to be held on October 16-17 at the Santa Clara Marriott in Silicon Valley, California. Electronic device manufacturers, materials suppliers, market analysts, and other industry experts will speak and participate in the only executive conference in the world dedicated to advanced electronic materials.  Last year’s conference sold out and attendees are encouraged to register early to ensure participation.

Organized by the Chemical and Gas Manufacturers Group (CGMG), a SEMI Special Interest Group comprised of leading manufacturers, producers, packagers and distributors of chemicals and gases used in the microelectronics industry, SMC offers presentations from leading market analysts, device manufacturers, industry consortiums, top suppliers and academic researchers, in combination with an innovative interactive format designed to facilitate business contacts and networking. SMC also provides valuable forecasting information, helps accelerate advanced materials markets, and serves as a forum for collaboration among all sectors of the advanced materials supply chain. Over 94 percent of the attendees at last year’s conference said SMC provided information useful to their jobs and provided valuable business contacts.

Featured topics for the two-day conference will include:

  • New materials and processes for next generation memory
  • Material metrology and characterization challenges at leading-edge nodes
  • Graphene and other carbon-based materials for semiconductor, storage, and industrial applications
  • Materials challenges for MEMS devices
  • Wafer processing and packaging materials outlook
  • The coming revolution in wide bandgap semiconductors
  • Latest advances in printed, large area and flexible electronics

The Strategic Materials Conference has provided valuable information and networking opportunities to materials and electronics industry professionals since 1995. Held this year at the Santa Clara Marriott in the heart of Silicon Valley, the event provides critical forecasting, emerging market, and materials trends for the microelectronics industry.

For more information and to register, visit www.semi.org/smc