Category Archives: Semicon

The Moscone Center will be undergoing major construction during Semicon West week. The major impact to attendees is that the South Hall will be closed to allow for new construction, so Semicon will take place in the North Hall and the first floor of the West Hall. The crosswalks at the corner of 3rd and Howell will also be closed.  The Intersolar North America show will occupy the West Hall Floor3 and half of the West Hall Floor2. ees North America – The International Exhibition for Batteries and Energy Storage Systems – will occupy the other half of Floor2. Expect heavy demolition operations to be underway nearby.

The Moscone Expansion Project plans to meet that need by expanding contiguous exhibition space as well as increasing the amount of flexible meeting and ballroom spaces.

In addition to adding new rentable square footage, the project architects – Skidmore, Owings and Merrill – seek to create an iconic sense of arrival that enhances Moscone’s civic presence on Howard Street and reconnects it to the surrounding neighborhood through the creation of reintroduced lost mid-block passageways. As such, the project proposes two new, enclosed pedestrian bridges connecting the upper levels of the new Moscone North and Moscone South as well as an upgrade to the existing pedestrian bridge across Howard Street. This would help to frame the main public arrival space between the two new buildings, provide enhanced circulation for Moscone convention attendees, and reduce on-street congestion all while maintaining full-time elevated public access across Howard Street from Yerba Buena Gardens to the cultural facilities.

Architect's Sketch of New Moscone

Architect’s Sketch of New Moscone

SEMI added a new high-profile program on China to its 2017 conference lineup for SEMICON West. Today at the Yerba Buena Theater, the China Strategic Innovation & Investment Forum will focus on the extensive business opportunities resulting from the semiconductor industry’s largest regional growth spurt now occurring in China.

While the global semiconductor industry continues to consolidate through large-scale mergers and acquisitions, China is embarking on a new round of expansion with heavy investment from public and private funding. China’s semiconductor industry is growing at an explosive rate, leading the rest of the world with a projected increase of 68 percent in fab equipment spending year-over-year (2017 to 2018), according to the May 2017 SEMI World Fab Forecast. China will be equipping over 50 facilities through 2018, and is forecast to spend more than US$11 billion.

The rise of the semiconductor industry in China need not be viewed as a threat to other global players, says SEMI, but rather as a significant driver of growth and business opportunity for suppliers worldwide. With its low indigenous market share for chips and nascent technical breadth in IC design, manufacturing, packaging, testing, equipment, and materials, China has become an enormous market for suppliers across the supply chain. In fact, ICs still top the list of all Chinese bulk imports in terms of U.S. dollar value.

At the China Strategic Innovation & Investment Forum, semiconductor and investment executives, as well as key China government and trade officials will share their views on the industry’s evolution and offer insights on growth, investment opportunities, M&A, and the latest innovations emerging in China. Attendees will hear from C-Level executives from Ali Cloud, AMEC, Applied Materials Venture Capital Group, Goldman Sachs, Verisilicon, Walden International, SEMI China, and more. An hour-long panel discussion, moderated by Lung Chu, president of SEMI China, will feature speakers and a Q&A session. With access to China experts presenting and multiple networking opportunities, the China forum will offer a collaborative platform where markets, technology, talent, and funding can meet up for mutual benefit.

Yerba Buena

SEMI has enriched this year’s SEMICON West by offering new, timely programs and forums for attendees to engage with peers and presenters at the three-day industry event.

“As our industry changes, we’re changing too,” said Dave Anderson, president, SEMI Americas. “Our programs are now organized around specific “Smart” applications, technologies, and adjacencies such as Smart Automotive, Advanced Packaging, 5G, and IoT, making it easy for attendees to focus on their specific needs,” he added. “We’ve reenergized the entire exposition and conference to put a laser focus on addressing challenges, finding solutions, and giving attendees everything they need to thrive in today’s disruptive business environment.”

SEMICON West offers 115 hours of advanced programming and more than 600 exhibits. The industry’s flagship event, re-imagined for 2017, will also feature inaugural programs, including:

  • China Strategic Innovation & Investment Forum — China’s semiconductor industry is going through an explosive growth phase. IC and investment executives will share their views on the industry’s evolution and offer insights on investment and M&A trends in China.
  • Meeting the Challenges of the 4th Industrial Revolution along the Microelectronics Supply Chain — The executive panel will address the opportunities and challenges facing the industry as the era of Big Data fuses the physical and digital worlds.
  • Smart Automotive, 5G Communications, MEMS & Sensors, MedTech and more will be discussed in the expanded TechXPOT sessions on the show floor.
  • IEEE Embedded Systems Training Workshops for IoT —Two exclusive IEEE workshops will cover embedded system software development, the key to optimizing performance and power in IoT devices and applications.
  • New Ways to Engage & Network — The new SMART Journey on the exposition floor will deliver stunning, hyper-visual insights into the microelectronics innovations that are revolutionizing the manufacturing supply chain, automotive, and everyday living. At the Journey’s Meet the Experts Theater, attendees will hear how breakthroughs in processes, packaging, and AI are changing the world.
  • Career Development — Amid competition from trendy companies like Google and Facebook, the semiconductor industry also needs to attract the best and the brightest. At the MicroE Career Development & Recruitment Forum, job seekers will learn about opportunities at some of the leading names in electronics.
  • On the fun front, the Summerfest at AT&T Park, home of the San Francisco Giants, will provide a bit of R&R as conference attendees network and watch the All-Star Game live on the stadium’s Big Screen.

In addition, SEMICON West features keynote talks from industry luminaries including Tetsuro Higashi of TEL, Tom Caulfield of GLOBALFOUNDRIES, Kathy Winters of Intel, and special guest Jim Morgan of Applied Materials. The World of IoT: Understanding Risks and Opportunities in Transformative Technologies — focuses on key IoT applications, big data and security, including solutions for home automation, smart cities, industrial monitoring, medical and healthcare, environmental monitoring, agriculture, and more. All of this, along with traditional favorites such as the SEMI/Gartner Bulls & Bears Industry Outlook, will be held at SEMICON West 2017.

To increase engagement with speakers and colleagues and enhance the overall Expo experience, attendees are encouraged to download the new SEMICON West Mobile App at the App Store or Google Play.

How low can we go?


July 11, 2017

By Ed Korczynski

In the advanced CMOS technology programs ongoing in the Belgium city of Leuven, imec works to extend the building-blocks of integrated circuits (IC). On the day before the opening of SEMICON West 2017, the invitation-only imec Technology Forum provided an update on the emerging opportunities in semiconductor technology and smart electronics systems. An Steegen, Executive VP Semiconductor Technology & Systems, provided the update on how small we can scale CMOS devices over the next 5-10 years. Taller finFETs will likely be used along with nano-wire FETs (NW-FET) by industry, and researchers see ways to cost-effectively combine both in future optimized System-on-Chips (SoC).

“Existing finFET technology can scale to the 5nm-node,” explained An Steegen at ITF 2017 in Antwerp, Belgium. “However, at the 3nm-node it looks like the nano-wire is comparable in performance to the finFET, but it has an additional advantage in that the nanowire is a better electro-statically controlled device so it enables gate-length scaling more than the finFET. So the contacted gate pitch (CGP) of a nano-wire can scale further than a finFET, because below ~40 nm CGP a finFET loses electro-static control which a nano-wire does not.”

While it is given that a nanowire has better electro-static control compared to a finFET, the basic trade-off is that of reduced drive current. The Figure shows that IMEC sees the possibility of System-Technology Co-Optimization (STCO) of future system-on-chip (SoC) designs using hybrid semiconductor technologies. imec’s basic process flow for NW-FETs starts with forming fins and so could be relatively easily integrated with finFETs for co-integrated hybrid CMOS.

System-Technology Co-Optimization (STCO) for future System-on-Chip (SoC) designs could integrate finFETs with Nano-Wire FETs (NW-FET) and Magnetic Random Access Memory (MRAM) for optimized performance. (Source: imec)

System-Technology Co-Optimization (STCO) for future System-on-Chip (SoC) designs could integrate finFETs with Nano-Wire FETs (NW-FET) and Magnetic Random Access Memory (MRAM) for optimized performance. (Source: imec)

“Today, this SoC is processed in one technology which means it’s sub-optimal for certain blocks on the SoC,” explained Steegen. “So imagine a future where you can choose the preferred technology for each block. I would choose finFETs for those blocks that need drive current, while I would choose nano-wire-FETs for those blocks that need more density and lower power. I would for example choose a magnetic RAM to replace my cache memory. I can optimize each sub-block for a preferred technology. Now I can do more, like sprinkle in low-energy devices like tunnel-FETs or spin-devices or 2D-materials as low-energy switches.”

Super-vias and Rutherails

Design-Technology Co-Optimization (DTCO) is imec’s term for new interconnect technologies to allow for simpler or more-compact designs. IDTCO process-scaling boosters are needed to stay with the pace of aggressive design rule targets. “We’re working on super-vias that connect more than one metal to the other and can jump a number of levels, and buried rails to support finFETs in standard-cell libraries,” explained Steegen during ITF2017.

Super-vias could be cobalt plugs that connect more than two metal levels within on-chip multi-level interconnects. The cobalt plugs would be nominally 20nm diameter and 105nm deep, and connected to a dual-damscene upper metal line. Low-k dielectric of k=2.55 uses thin silicon carbon nitride (SiCN) for definition between the damascene levels.

Ruthenium rails (Rutherails) would be buried in a front-end dielectric layer to provide electrical contacts below finFETs for 42nm CGP and 21nm MP needed for imec 3nm-Node (I3N) devices. Ruthenium rails 30nm deep and 10nm wide do not need complex barrier layers and should provide sufficient current flow for either finFETs or NW-FETs.

imec is also working on materials R&D to extend the performance of 3D-NAND. Steegen said,

“At imec we are working on improving the performance of that Flash device by introducing high-mobility channels, also by engineering the dielectric trapping layer with a barrier that can help improve the erase window and also the retention.”

9:05 am – 9:35 am
KEYNOTE: The Semiconductor Industry: Changed and Unchanged
Tetsuro Higashi, TEL
Yerba Buena Theater

9:35 am – 10:05 am
KEYNOTE: Accelerating Innovation: Intelligent is the New Smart
Thomas Caulfield, GLOBALFOUNDRIES

10:30 am – 4:00 pm
World of IoT
Understanding Risks and Opportunities
San Francisco Marriott Marquis

10:30 am – 12:45 pm
What’s next for MEMS & Sensors
Big Growth of Disruptive Applications
Moscone Morth, TechXPOT North

2:00 pm – 5:00 pm
China Strategic Innovation & Investment Forum
The Rise of the China IC Industry
Yerba Buena Theater

3:00 pm – 4:30 pm
Advanced Packaging
Meet the Experts, Day 1
Meet the Expert Theater, Moscone West

5:00 pm – 10:00 pm
Summerfest at AT&T Park
Hors d’oeuvres, beverages and MLB All-Star Game

5:00pm – 9:00pm
Leti Workshop
W Hotel – 181 3rd St., San Francisco

By Pete Singer

Luc Van den Hove, president and CEO of imec

Luc Van den Hove, president and CEO of imec

Speaking at imec’s International Technology Forum USA yesterday afternoon at the Marriott Marquis, Luc Van den Hove, president and CEO of imec, provided a glimpse of society’s future and explained how semiconductor technology will play a key role. From everything the IoT to early diagnosis of cancer through cell sorters, liquid biopsies and high-performance sequencing, technology will enable “endless complexity increase,” he said.

Other developments, almost all of which are being worked on at imec, include self-learning neuromorphic chips, brain implants, artificial intelligence, 5G, IoT and sensors, augmented and virtual reality, high resolution (5000 ppi) OLED displays, EOG based eye tracking and haptic feedback devices. He also acknowledged the critical importance of security issues, but suggested a solution. He noted that each chip has its own fingerprint due to nanoscale variability. That’s been a problem for the industry but we could “turn this limitation into an advantage,” he said, with an approach called PUFs — Physical Unclonable Functions (Figure 1).

Figure 1. Nanoscale variability has been a problem for the industry but we could be turned into an advantage with PUFs -- Physical Unclonable Functions.

Figure 1. Nanoscale variability has been a problem for the industry but we could be turned into an advantage with PUFs — Physical Unclonable Functions.

At the forum, imec also announced that its researchers, in collaboration with scientists from KU Leuven in Belgium and Pisa University in Italy, have performed the first material-device-circuit level co-optimization of field-effect transistors (FETs) based on 2D materials for high-performance logic applications scaled beyond the 10nm technology node. Imec also presented novel designs that would allow using mono-layer 2D materials to enable Moore’s law even below 5nm gate length. Additionally, imec announced that it demonstrated an electrically functional 5nm solution for Back-End-of-Line interconnects.

FETs based on 2D materials

2D materials, a family of materials that form two-dimensional crystals, may be used to create the ultimate transistor with a channel thickness down to the level of single atoms and gate length of few nanometers. A key driver that allowed the industry to follow Moore’s Law and continue producing ever more powerful chips was the continued scaling of the gate length. To counter the resulting negative short-channel effects, chip manufacturers have already moved from planar transistors to FinFETs. They are now introducing other transistor architectures such as nanowire FETs. The work reported by imec looks further, replacing the transistor channel material, with 2D materials as some of the prime candidates.

Figure 2. 2D materials, with the atomically-precise dimension control they enable, promise to become key materials for future innovations.

Figure 2. 2D materials, with the atomically-precise dimension control they enable, promise to become key materials for future innovations.

In a paper published in Scientific Reports, the imec scientists and their colleagues presented guidelines on how to choose materials, design the devices and optimize performance to arrive at circuits that meet the requirements for sub-10nm high-performance logic chips. Their findings demonstrate the need to use 2D materials with anisotropicity and a smaller effective mass in the transport direction. Using one such material, monolayer black-phosphorus, the researchers presented novel device designs that pave the way to even further extend Moore’s law into the sub-5nm gate length. These designs reveal that for sub-5nm gate lengths, 2D electrostatics arising from gate stack design become more of a challenge than direct source-to-drain tunneling. These results are very encouraging, because in the case of 3D semiconductors, such as Si, scaling gate length so aggressively is practically impossible.

“2D materials, with the atomically-precise dimension control they enable, promise to become key materials for future innovations. With advancing R&D, we see opportunities emerging in domains such as photonics, optoelectronics, (bio)sensing, energy storage, photovoltaics, and also transistor scaling. Many of these concepts have already been demonstrated in the labs,” says Iuliana Radu, distinguished member of technical staff at imec. “Our latest results presented in Scientific Reports, show how 2D materials could be used to scale FETs for very advanced technology nodes.”

5nm Solution for BEOL

The announced electrically functional solution for 5nm back-end-of-line (BEOL) is a full dual-damascene module in combination with multi-patterning and multi-blocking. Scaling boosters and aggressive design rules pave the way to even smaller dimensions.

As R&D progresses towards the 5nm technology node, the tiny Cu wiring schemes in the chips’ BEOL are becoming more complex and compact. Shrinking the dimensions also reduces the wires cross-sectional area, driving up the resistance-capacitance product (RC) of the interconnect systems and thus increasing signal delay. To overcome the RC delay challenge and enable further improvements in interconnect performance, imec explores new materials, process modules and design solutions for future chip generations.

One viable option is to extend the Cu-based dual-damascene technology – the current workhorse process flow for interconnects – into the next technology nodes. Imec has demonstrated that the 5nm BEOL can be realized with a full dual-damascene module using multi-patterning solutions. With this flow, trenches are created with critical dimensions of 12nm at 16nm. Metal-cuts (or blocks) perpendicular to the trenches are added in order to create electrically functional lines and then the trenches are filled with metal. Area scaling is further pushed through the introduction of fully self-aligned vias. Moreover, aggressive design rules are explored to better control the variability of the metal tip-to-tips (T2Ts).

Figure 3. Dense-pitch blocks enabled by a dual damascene flow and multi-patterning. The pattern is etched into the low-k and metallized.

Figure 3. Dense-pitch blocks enabled by a dual damascene flow and multi-patterning. The pattern is etched into the low-k and metallized.

Beyond 5nm, imec is exploring alternative metals that can potentially replace Cu as a conductor. Among the candidates identified, low-resistive Ruthenium (Ru) demonstrated great promise. The imec team has realized Ru nanowires in scaled dimensions, with 58nm2 cross-sectional area, exhibiting a low resistivity, robust wafer-level reliability, and oxidation resistance – eliminating the need for a diffusion barrier.

“The emergence of RC delay issues started several technology nodes ago, and has become increasingly more challenging at each node. Through innovations in materials and process schemes, new BEOL architectures and system/technology co-optimization, we can overcome this challenge as far as the 5nm node”, said Zsolt Tokei, imec’s director of the nano-interconnect program. “Imec and its partners have shown attainable options for high density area scaled logic blocks for future nodes, which will drive the supplier community for future needs.”

For the longer term, imec is investigating different options including but not limited to alternative metals, insertion of self-assembled monolayers or alternative signaling techniques such as low-energy spin-wave propagation in magnetic waveguides, exploiting the electron’s spin to transport the signal. For example, the researchers have experimentally shown that spin waves can travel over several micrometers, the distance required by short and medium interconnects in equivalent spintronic circuits.

Brewer Science Inc. today announced from SEMICON West the extension of its partnership with Arkema to develop second-generation directed self-assembly (DSA) materials using high-x (chi) block copolymers. These new materials target advanced-node wafer patterning processes, because they enable even smaller feature sizes than first-generation DSA materials. As such, they provide a cost-effective solution to achieving device nodes down to 5nm and beyond, thereby enabling the continuation of Moore’s law.

“There have been very high expectations that DSA would solve all patterning issues,” said Darron Jurajda, Business Unit Manager, Brewer Science Inc. “Like all worthwhile technologies, there are many challenges to be solved before going into production. Leveraging our earlier DSA collaboration with Arkema offers the best path for implementing the next generation of materials. Together, we look forward to unlocking DSA’s full potential in accordance with industry timelines for manufacturing.”

High-chi block copolymers will further extend DSA’s advantages, achieving feature sizes that meet the requirements for 5nm and beyond. Extending their partnership allows these companies to build on their knowledge base, giving them a head start on developing high-chi materials.

As feature sizes shrink more aggressively with each node, it has become cost prohibitive to create them using existing patterning processes, such as EUV, self-aligned double patterning and self-aligned quad patterning. This presents a challenge for foundries and integrated device manufacturers preparing to ramp to 7nm and 5nm processes. DSA provides an alternative solution to achieving fine feature patterning; can be explored for minimal investment; and is cost efficient in final production. Development of high-chi materials also expands the opportunity for implementing DSA in other applications, including photonics, membrane applications and other areas of microelectronics.

The original collaboration between the two companies combined Brewer Science’s know-how in patterning and process integration with Arkema’s leading-edge expertise in block copolymer development to develop polystyrene-polymethyl methacrylate DSA materials, which are now production-ready to manufacture sub-22nm features.

At its annual Imec Technology Forum USA in San Francisco, imec today presented an electrically functional solution for the 5nm back-end-of-line (BEOL). The solution is a full dual-damascene module in combination with multi-patterning and multi-blocking. Scaling boosters and aggressive design rules pave the way to even smaller dimensions.

As R&D progresses towards the 5nm technology node, the tiny Cu wiring schemes in the chips’ BEOL are becoming more complex and compact. Shrinking the dimensions also reduces the wires cross-sectional area, driving up the resistance-capacitance product (RC) of the interconnect systems and thus increasing signal delay. To overcome the RC delay challenge and enable further improvements in interconnect performance, imec explores new materials, process modules and design solutions for future chip generations.

Dense-pitch blocks enabled by a dual damascene flow and multi-patterning. The pattern is etched into the low-k and metallized.

Dense-pitch blocks enabled by a dual damascene flow and multi-patterning. The pattern is etched into the low-k and metallized.

One viable option is to extend the Cu-based dual-damascene technology – the current workhorse process flow for interconnects – into the next technology nodes. Imec has demonstrated that the 5nm BEOL can be realized with a full dual-damascene module using multi-patterning solutions. With this flow, trenches are created with critical dimensions of 12nm at 16nm.  Metal-cuts (or blocks) perpendicular to the trenches are added in order to create electrically functional lines and then the trenches are filled with metal. Area scaling is further pushed through the introduction of fully self-aligned vias. Moreover, aggressive design rules are explored to better control the variability of the metal tip-to-tips (T2Ts).

Beyond 5nm, imec is exploring alternative metals that can potentially replace Cu as a conductor. Among the candidates identified, low-resistive Ruthenium (Ru) demonstrated great promise. The imec team has realized Ru nanowires in scaled dimensions, with 58nm2 cross-sectional area, exhibiting a low resistivity, robust wafer-level reliability, and oxidation resistance – eliminating the need for a diffusion barrier.

“The emergence of RC delay issues started several technology nodes ago, and has become increasingly more challenging at each node. Through innovations in materials and process schemes, new BEOL architectures and system/technology co-optimization, we can overcome this challenge as far as the 5nm node,” said Zsolt Tokei, imec’s director of the nano-interconnect program. “Imec and its partners have shown attainable options for high density area scaled logic blocks for future nodes, which will drive the supplier community for future needs.”

For the longer term, imec is investigating different options including but not limited to alternative metals, insertion of self-assembled monolayers or alternative signaling techniques such as low-energy spin-wave propagation in magnetic waveguides, exploiting the electron’s spin to transport the signal. For example, the researchers have experimentally shown that spin waves can travel over several micrometers, the distance required by short and medium interconnects in equivalent spintronic circuits.

Imec’s research into advanced logic scaling is performed in cooperation with imec’s key partners in its core CMOS programs including GlobalFoundries, Huawei, Intel, Micron, Qualcomm, Samsung, SK Hynix, Sony Semiconductor Solutions and TSMC.

By Paula Doe, SEMI

SEMI adds a new speaker program called “Meet the Experts” at SEMICON West (July 11-13) in San Francisco this year. Complementing the more formal TechXPOTs, “Meet the Experts” is on a smaller scale, more relaxed format, with more time for discussion, and a wider variety of speakers. We’ve invited 25 diverse experts to speak on the challenges and opportunities for the semiconductor supply chain from smart automobiles and the Internet of Things, and the smarter next-generation manufacturing technology needed to enable this smart, connected future.

What does the IoT really mean for the semiconductor world?

The exciting emerging opportunities for smart connected objects ─ from cars to industrial systems ─ that are changing our lives also mean change for our semiconductor manufacturing business, suggests Tom Walsh, president of Tokyo Electron NEXX, who will speak on the issue in the new Meet the Experts program at SEMICON West on July 12. “These new applications require many and various new materials and packaging solutions,” he says. “But the technical challenges are not as big as the economic ones —these automotive and consumer products need equipment that is cheaper than the typical advanced front end tools, and fewer tools will be required to manufacture some of the smaller die.” That means more standardized baselines platforms for packaging, and more options for creative solutions to retrofit existing tools for new applications. “Maybe we can remove some unneeded features — sort of like taking out the heated seats,” he quips, to meet a specific technical need at lower cost.

The wildcard for this new reality is augmented reality headsets. “If eye-glasses come to replace the mobile phone as consumers’ main device, that changes the world,” he notes.

Emerging industrial applications for virtual reality

In the past year the automotive industry has increasingly come to rely on virtual reality for mockups and design reviews to save the time and cost involved in making clay models, and the technology is also finding use in employee training and the semiconductor supply chain, notes David Chang, HTC director of Corporate Development and Partnerships, another speaker in the SEMICON West “Meet the Experts” program. “We’re starting to see some users in the semiconductor industry use VR for exposition displays,” he says, noting the appeal of the more immersive working demonstrations of equipment without the cost and limitations of bring actual equipment to a show. “Virtual reality isn’t just for gaming any more, but for serious business,” he contends. HTC will be demonstrating automotive and manufacturing applications of virtual reality in the Smart Journey area at SEMICON West.

Chang says the 2Kbit resolution and 90 frames/second refresh of the HTC VIVE system is now close to that of human vision, and the lighthouse base-station system that tracks the position and orientation of the head adjusts appropriately for a realistic view that makes the system sufficiently precise for serious industrial applications. It integrates with Dassault Système’s CATiA CAD software so designers can physically view their designs without extra effort.

New data base tracks packaging technologies across the changing OSAT sector

As the OSAT industry matures, the way we do packaging and assembly is changing dramatically, as advanced packaging moves more to a wafer-level technology in a more fab-like environment, and much of the growth moves to China, notes Jan Vardaman, president of TechSearch International, speaking in the Advanced Packaging program.  She’ll introduce the new Worldwide OSAT Manufacturing Site Database, developed by SEMI and TechSearch, which tracks what types of packages are made in which facilities of 120 OSATs worldwide. Based on two years of factory visits and personal interviews, this detailed analysis allows fabless companies to easily see the full options for the packaging and assembly technologies they need, and equipment and materials suppliers to quickly see the needs of customers worldwide. “I think this is one of the greatest services that SEMI can offer its audience, says Vardaman. “It will save people a huge amount of time.”

Big changes from artificial intelligence

A number of other speakers at SEMICON West will focus on the use of data analytics, machine learning, and other types of AI in enabling the emerging generation of both semiconductor applications and semiconductor manufacturing. GE Global Research Lead Machine learning researcher Weina Ge, Ericsson Research director of IoT & Analytics Zsolt Parnaki, and NVIDIA technical marketing lead Tim Wong will cover automotive and IoT applications, while Coventor CTO David Fried, Nanotronics CRO Justin Stanwix, Motivo Data Analytics CTO Luigi Capodieci, and Siemens director, Industry Solutions, PLM Software, Tim Hewitt will address uses in semiconductor manufacturing.

Speakers from Lawrence Livermore National Lab, Multibeam Corp, NeoSpectra, NXP, Quarnergy Systems, SAE, Synopsis, andYole Développement are also talking on automotive and IoT technologies. ASE, ASM Pacific Technology, Edwards Vacuum, EV Group, SPTS, and the Heterogeneous Integration Roadmap will cover next generation IC process and packaging issues.

These SEMICON West 2017 programs, included in the basic Expo Only pass, run all day within the Smart Journey demonstration area in West Hall, with its virtual and augmented reality experiences which highlight the smart, connected future.

SUNY Polytechnic Institute (SUNY Poly), in partnership with Empire State Development (ESD), the American Institute for Manufacturing Integrated Photonics (AIM Photonics), and the New York Power Electronics Manufacturing Consortium (NY-PEMC) today announced that a number of the institution’s leading researchers, scientists from a number of SUNY Poly’s corporate partners, and New York State economic development experts will share research and development updates at the globally recognized SEMICON West 2017 conference, which is taking place July 11 through 13 in San Francisco, California.

During this year’s engagement, researchers based at SUNY Poly’s Albany campus will present progress reports for a number of initiatives it is spearheading across New York State, including updates on AIM Photonics and the NY-PEMC, which are ramping up capabilities related to the development of next-generation photonics-based technologies, quantum computing, and silicon carbide-based power electronics, respectively, in addition to spurring economic engagement activities throughout New York State.

“Empire State Development is proud to once again collaborate with our partners at SUNY Poly and Upstate New York’s economic development organizations to showcase New York State’s high-tech research, development and business growth opportunities at SEMICON West,” said Empire State Development President, CEO & Commissioner Howard Zemsky. “Our strategic approach and improved business climate are successfully attracting innovative firms and entrepreneurs, and we’re looking forward to sharing our story with attendees and business leaders from around the world, particularly those who can benefit from the cutting-edge work being done in power electronics and photonics.”

“As a leading member of the AIM Photonics and NY-PEMC initiatives that are driving R&D in key areas, SUNY Poly is proud to work with Empire State Development at SEMICON West 2017 to share current progress with industry leaders who will be attending this year’s conference and exhibition,” said SUNY Poly Interim President Dr. Bahgat Sammakia. “By partnering with world-leading corporations, institutions, and organizations in the high-tech arena to share how further collaboration can help drive innovation and growth in New York State, SUNY Poly is thrilled once again to play a significant role at SEMICON West.”

At this year’s SEMICON West conference, SUNY Poly presenters, including SUNY Poly Vice President for Research and CEO of AIM Photonics Dr. Michael Liehr and SUNY Poly Associate Vice President for Business, Wafer Processing and CMO of AIM Photonics Frank Tolic will provide updates on the SUNY Poly-led AIM Photonics initiative as it begins building and equipping the Rochester-based photonics Test, Assembly, and Packaging (TAP) facility. To date, AIM Photonics has seen increasing interest in membership, with more than 80 signed members and additional interested collaborators from across the United States, including those representing areas ranging from industry and academia to government. More specifically, AIM Photonics and SUNY Poly leaders will provide presentations on topics such as, “The integrated silicon photonics 21st century revolution,” and “Leveraging state-of-the-art fabrication to advance quantum computing technologies,” among others. In addition, presentations will also detail AIM Academy and workforce development efforts meant to ensure that AIM Photonics-related jobs will be filled from a pool of diverse, highly qualified candidates.

“As the national AIM Photonics initiative hits its stride, initializing important research and development work and the high-tech infrastructure to drive New York State’s innovative ecosystem, as well as significant R&D nodes across the United States, we are thrilled to be able to share AIM’s opportunities with the many researchers and business leaders at SEMICON West,” said Dr. Liehr. “During this year’s engagement, AIM Photonics is eager to share updates related to the development of the TAP facility in Rochester, New York, as well as its latest offerings which can enable meaningful, cost-effective collaborations via the leveraging of the initiative’s PDK (Process Design Kit) and MPW (Multi Project Wafer) capabilities.”

A New York Nanotechnology Summit, scheduled to take place Wednesday, July 12, from 8am – Noon at the PARC55 Hotel, will provide SEMICON West participants with an opportunity to network and learn more about New York State’s research and business opportunities in the nanotechnology sector, especially as it relates to semiconductor, integrated photonics, power electronics, packaging, and other nanotechnology-related R&D and commercialization efforts. Representatives from AIM Photonics, NY-PEMC, SUNY Poly, New York Economic Development Agencies, and industry leaders IBM, GE, TEL, Mentor, Infinera, Coventor, Cadence, and Eastman Business Park will offer key technology insights, program updates, and information about future partnership and business opportunities, in addition to details about shovel ready, cost-effective and efficient locations for companies that are looking for growth.

Additionally, at this year’s SEMICON West engagement, NY-PEMC representatives will also provide presentations detailing the initiative’s progress as SUNY Poly, in partnership with General Electric, drive the high volume manufacturing and packaging of power electronic devices and systems that are smaller, faster, and more efficient than current silicon-based computer chips. The presentations will offer details related to the successful first production of silicon carbide-based patterned wafers at the NY-PEMC’s 150mm SiC foundry, which was announced in February. For example, NY-PEMC’s Brian Sapp will present, “The New York Power Electronics Manufacturing Consortium: Enabling the Power Electronics Revolution,” which will offer further insight into SUNY Poly’s Albany NanoTech Complex and its power electronics capabilities, as well as the state-of-the-art power electronics packaging facility at SUNY Poly’s Computer Chip Commercialization Center (Quad-C) fab, which is located in Utica, New York, where partner Danfoss Silicon Power will package modules and power blocks for industrial, automotive, and renewable energy applications.

Complementing the various research-based presentations by AIM Photonics and NY-PEMC-focused researchers and partners, the more than 26,000 expected attendees of the SEMICON West 2017 conference and exhibition will also be able to learn more about those initiatives and SUNY Poly’s top tier resources and capabilities by visiting the New York State Pavilion in Booth #7837, which will feature representatives from SUNY Poly, Empire State Development, NY Loves Nanotech, AIM Photonics, and NY-PEMC, as well as a patterned 150mm SiC wafer produced by the consortium. At the prominently located exhibition booth, program leaders, scientists, and others will provide information about New York State’s high-tech corridor and related economic engagement incentives, as well as opportunities for interested organizations in a number of innovation-based industries. Booth number 7837 will be located in the Moscone Center’s West Hall, Level One, and representatives will be available from Tuesday, July 11 through Wednesday, July 12 from 10 a.m. to 5 p.m. and on Thursday, July 13 from 10 a.m. to 4 p.m.

SEMICON West is an annual tradeshow for the microelectronics manufacturing industries and their supply chains. There, researchers present their cutting-edge work via keynote addresses, executive panels, and technical and business sessions to attendees from around the world. In addition to the more than 600 expected exhibitors and hundreds of product displays, the event also features applications and topics ranging from micro-electromechanical systems (MEMS) to nanoelectronics and the internet of things (IoT).