November 30, 2010 – Applied Materials and Samsung Electronics have come to a settlement agreement over allegations earlier this year that the equipment maker may have been leaked to rival Hynix.

Terms of the deal, which resolves potential civil claims and litigation over "alleged acquisition, misappropriation and misuse" of sensitive chip manufacturing data, include "volume-based rebates" on chip tool purchases and upgrades for three years for Samsung and affiliated companies, including for new areas of work (including joint development) in which they aren’t currently partnered. The settlement does not cover, however, any actions Samsung is pursuing against individual employees of AMAT and other involved companies, including current proceedings in Seoul courts.

To recap: back in February, news broke that dozens of memory and other chip technologies were allegedly obtained during equipment installation/maintenance at Samsung, pilfered by AMAT Korea and Samsung employees; some of that technology allegedly found their way to Korean memory rival Hynix. Samsung estimated the leaks could cost it in the hundreds of millions of US dollars (directly), and possibly indirectly in the hundreds of billions.

The financial impact of the settlement, AMAT says, will depend on how much Samsung purchases from it over the three-year period — the chipmaker represented about 10% of AMAT’s $5B net sales in FY09 — but the company expects a dent of only a single percentage point in the low end of its chip tool division’s operating margins (currently a range of 33%-38%). Deutsche Bank’s Peter Kim thinks it could be up to 2% of the SSG group’s margins (translating to ~$100M/year for three years).

But ultimately it’s not so much about the money lost, as a customer regained. Samsung is AMAT’s biggest customer and arguably the biggest and most important chip tool purchaser (alongside Intel). Clearing the litigious air means the two can get back to business, and the newly attractive pricing means Samsung might expand its use of AMAT tools, thus giving AMAT some share gains at this key account.

by Karey Holland, Techcet Group

November 29, 2010 – Overall, the >50 presentations and posters at this year’s International Conference on Planarization Technology (ICPT, Nov. 15-16 in Phoenix) exceeded my expectations for technical content. The presentations fit into general areas of front-end (STI, HKMG, and new device designs), back-end (Cu interconnect, barrier, etc.), emerging/non-traditional (quite an interesting mix), cleans and metrology, and modeling (including CMP mechanistic characterization). An electrochemist by training, I particularly appreciated the Porbaix diagrams and potentiometric polarization curves that were presented.

A series of presentations focused on the two CMP processes used in forming the high-k dielectric/metal electrode gate (HKMG) devices. Matt Prince of Intel led off Tuesday afternoon with a well-attended presentation about "Moore’s Law and Front-End CMP Challenges," in which he reviewed the roadmap that led to new CMP processes in fabricating the basic HKMG devices at 45nm. (This talk nicely complemented the keynote address from Intel 11X fab manager Ann Kelleher.) "Film thickness control and defects" were the "top concerns" during development, Prince stated, and they "will continue to be a challenge for new applications." (In support of this, an immediately preceding talk from Intel’s G. Kim focused on understanding/modeling within-die [WID] uniformity.) Prince hinted that new CMP technologies will be required after 32nm; what these are he left to our imaginations. The CMP aspects of HKMG process flow was shown with typical defect challenges. A key message (thanks to Intel’s Kelin Kuhn): Scaling drives down cost, but performance is now driven by materials rather than scaling. In summary, Prince stated some needs which elicited additional (nervous?) laughter from the audience:

• R&D needs materials suppliers to deliver new slurries and pads, with tunable properties, in days not weeks;

• Slurry development must continue to evaluate multiple pad types, and vice-versa;

• More development is required on post CMP cleaning (i.e., chemistry & brushes);

• Equipment needs to deliver tighter film thickness control, while improving end-point and metrology capabilities.

A valuable reminder: the last big push for new interconnect materials, e.g., Cu and low-k, lead to careers made or broken, and businesses made and broken.

K. DeVriendt from IMEC and T. Du from Fujimi presented specific polish process papers on the poly open dielectric CMP and Al replacement metal gate planarization, respectively. While HKMG is today only a small segment of the CMP application market, this will grow as more devices make the transition from SiO₂ and silicide gates to HKMG. DeVriendt and Ong (also from IMEC) presented two new front-end processes, which may be used for technologies beyond 22nm and after HKMG devices: vertical Si nanowire tunnel FET (CMP is used to open the top of the Si nanowires) and "Ge for high mobility channels." F. LeQuéré (CEA-Leti) presented a paper on mesoporous silicon structures. H.J. Kim (Samsung) presented papers on microscratch characterization and reduction, observing that not all microscratches result in chip failure. And Intel’s Prince, reinforcing one of his key concerns, commented that while some defect may not be a killer defect in this generation, they may be in the next generation, and he could not accept any microscratches for this reason.

IBM presenters focused on interconnect technology. Papa Rao explained that low-k materials have higher dielectric constants after CMP that can be modulated by pad and slurry choice. Independent of what causes an increase in dielectric constant, either a plasma or UV treatment appeared to release the contaminants from the dielectric’s matrix and allow them to volatilize. He postulated that the plasma treatment improvement was likely caused by the UV emissions that heal the low-k film. Don Canaperi (IBM) discussed a well-balanced process optimization with low solids slurry for barrier removal. The process required a balancing act that optimized electrical yield (shorts/opens), defects (including metal residuals), remaining topography, and wiring resistivity (copper erosion).

Other CMP copper interconnect process papers were presented by X. Gu (Tohoku University), J. Koh (Hynix), L. Lu (Epoch/Cabot Micro), A. Kiesel (GlobalFoundries), S. Kondo (Renesas), and A. Natarajan (IBM), collectively doing a good job focusing on development for reducing copper erosion, CMP effects on low-k, and all defects. K. Okutani (CASMAT) discussed pattern density effects and how connecting high-density lines to large pads can effect on Cu corrosion. A few presentations focused more on the consumables interactions with each other and the interconnect process. These included new particles (F. Nemouchi, CEA-Leti with ST and BASF), scaling challenges and novel methods of passivating materials from CMP attack (L. Cook, Dow), post-CMP rinse caused Cu surface microroughness (T. Hirano, Fujimi), and the effect of pad and slurry on interlayer dielectric (ILD) polish (S. Li, Cabot Micro).

On the CMP characterization front, university and fab people are doing some intriguing work. There were several papers that used various techniques to study pad asperities, their height, contact area, and implications for scratching defects, and the presentations involved discussions of some very interesting metrology techniques. These include T. Eusner (MIT in conjunction with Intel), R. Duyos Mateo (Tohoku University + ASU), K. Kimura (Kyushu Institute of Tech), J. Chien (Berkeley), S. Bott (Fraunhofer), S. Jung (Gwangju Institute of Science & Technology), and A. Reddy (Dow). An interesting study of zeta potential on the pad materials, presented by P. Sides (Carnegie Mellon University with Intel), should continue our understanding of pad surfaces and their interaction with particles, slurry chemistry, and cleaning. C. Cheng (Dow with KLA-Tencor) discussed methods of measuring haze as a CMP defect. X. Liao (University of Arizona with Entegris) showed that slurry bow wave thickness can be changed by carrier ring design. Models to help us understand how consumables interact were presented by G.S. Kim (Intel) and J Yang (Samsung).

The general area of emerging/non-traditional CMP applications included several on GST (Ge₂SbTe₅) and through-silicon vias (TSV). M. Suzuki (Asahi Glass) presented a ceria slurry process optimized for polishing the wafers’ backs to open the bottom of the deep copper TSVs. An interesting proposal to purposefully dish Cu TSV for improved alignment was presented by H. Jeong (Pusan National University). J-Y. Cho (Hangyang University with Hynix) discussed corrosion mechanisms for GST post CMP with and without H₂O₂ slurries.

Additional CMP applications included PRAM damascene structures. V. Balan (CEA-Leti with ST) and T. Pfau (Entrepix) presented CMP process information on packaging applications for Medtronic. H. Cui (Hangyang University) found that when polishing SiO₂-Ta, polyacrylamide has a strong affinity for Ta and adsorption reduces the Ta rate, with no affect on the SiO₂ rate.

It is hard to beat the environment of Phoenix in November, and even better was to have a meeting in this environment that continues to move the industry forward in process learning, characterization and improved understanding of CMP processes.

Karey Holland, Ph.D., managing partner at Techcet Group, has >25 years of experience in semiconductor technology, including CMP equipment company SpeedFam-IPEC, IBM (where she contributed to interconnect technology development and manufacturing introduction of IBM’s 4Mb DRAM), SEMATECH’s deep-UV lithography Micrascan II project, and Motorola’s microprocessor and memory technology group. Contact: [email protected].

(November 19, 2010) — Fabless company Picochip Limited (Picochip), femtocell technology and silicon provider, completed a new $9 million debt facility with Silicon Valley Bank, the commercial banking division of SVB Financial Group (Nasdaq: SIVB). The facility consists of a $4.0 million three-year term loan and a two-year $5.0 million working capital line of credit. The combined facility will provide Picochip with access to additional working capital to support growth.

"Picochip is constantly driving to develop and commercialize innovative approaches to mobile voice and data services, with femtocells deploying and LTE following. We believe this debt facility will serve as a solid foundation for our rapid growth, providing us with the financial flexibility needed to stay ahead of the curve," commented Nigel Toon, CEO of Picochip. Picochip has worked with Silicon Valley Bank since 2004.

Separately, Picochip has announced significant expansion in its worldwide operations. The company has moved to a new headquarters and engineering center in its home city of Bath, UK; acquired an advanced test laboratory in Cambridge, UK; and announced plans to double the size of its development centre in Beijing, China.

Backed by Atlas, Highland, Intel, SEP, Pond and Rothschild, Picochip was the first company to launch a femtocell chip and has capabilities in silicon design, wireless tools, software and systems integration. Learn more at http://www.picochip.com/

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(November 18, 2010 – Marketwire) — Verigy’s (NASDAQ: VRGY), LTX-Credence (NASDAQ: LTXC) merger proposes to add scale with increased presence in the SOC test market; combine complementary products, markets, customers and channels; and generate annualized synergies of at least $25 million, following the completion of the integration.

Verigy and LTX-Credence Corporation entered into a definitive merger agreement that would create a semiconductor test company with the scale and presence to provide comprehensive solutions to customers across most major semiconductor market segments. The combined company, to be called Verigy, will feature a portfolio of semiconductor test systems to address requirements of the wireless, graphics, computing, automotive, industrial, and entertainment markets.

The new Verigy will have an expanded product portfolio, strong share position in target segments and large support network through a direct support team and key strategic partners such as Spirox in Taiwan and China, the company reports. By combining two of the industry’s most highly skilled and experienced R&D teams under a common focus and direction, Verigy anticipates creating a stronger, more competitive innovator of test cell solutions that enable semiconductor manufacturers to meet time-to-market and cost-of-test demands.

Verigy president and COO, Jorge Titinger, and LTX-Credence president and CEO, David Tacelli, will serve as co-CEOs of the new company, which will be headquartered in Singapore with U.S. headquarters in Cupertino, CA. Verigy chairman and CEO, Keith Barnes, will continue as the chairman of the board of directors, which will comprise 12 members, 7 designated by Verigy and 5 by LTX-Credence. Furthermore, to facilitate the leadership change, Keith Barnes will transition from Verigy CEO to Verigy chairman of the board of directors as of Dec. 31, 2010, and Jorge Titinger will be promoted to Verigy CEO and president.

"Verigy has a well-established presence in the high-performance digital, complex mixed-signal and RF-SOC segments while LTX-Credence has a broad SOC market footprint and expertise in cost-optimized solutions," said Jorge Titinger, Verigy president and COO. "We expect the combination will enable the new Verigy to drive sustainable long-term growth and shareholder value through the expansion of our product and technology portfolio as well as our existing customer relationships."

Under the terms of the agreement, the transaction will either be effected through a reorganization where Verigy and LTX-Credence would be wholly owned subsidiaries of Holdco, a newly created subsidiary, or through a merger where LTX-Credence would become a wholly owned subsidiary of Verigy. LTX-Credence shareholders will receive a fixed exchange ratio of 0.96 shares of Verigy stock or Holdco stock for each share of LTX-Credence stock. Upon closing, Verigy or Holdco, as applicable, will issue approximately 49 million shares on a fully diluted basis to complete the transaction. At that time, Verigy and LTX-Credence shareholders will own approximately 56 percent and 44 percent, respectively, of the combined company.

The Law Office of Jonathan M. Stei, P.L. is investigating the Board of Directors of LTX for possible breaches of fiduciary duty and other violations of state law in connection with their sale price (Source: BUSINESSWIRE). The investigation involves whether the Board of Directors of LTX breached their fiduciary duties to LTX stockholders by failing to adequately shop the Company before agreeing to enter into the transaction and whether LTX has disclosed all material information to shareholders about the proposed transaction. As recently as June 2010, LTX stock traded above $10.00 per share. According to Thompson/First Call, at least one analyst has set a price target of $18.00 per share for LTX-Credence stock. Due to these factors, Kendall Law Group also believes the transaction may be significantly undervaluing the company.

The combined company expects to realize substantial synergies within one year of the close of the deal, with annual cost savings expected to reach at least $25 million, primarily from increased efficiencies in manufacturing and reduced operating expenses.

The transaction is subject to the approval of shareholders from both companies as well as other customary closing conditions and regulatory approvals. The companies expect the transaction to close in the first half of calendar 2011.

Shares of the combined company will trade on the NASDAQ under the symbol "VRGY." Morgan Stanley acted as financial advisor and Wilson Sonsini Goodrich & Rosati acted as legal counsel to Verigy. J.P. Morgan acted as financial advisor and WilmerHale acted as legal counsel to LTX-Credence.

Verigy Odd Lot and Repurchase Program
Verigy also announced today its board of directors has authorized an odd lot program that will result in the purchase of approximately 2.3 million shares, or 4% of Verigy’s current outstanding shares, from shareholders holding less than 100 shares of the combined company following the transaction. This is expected to simplify the combined company’s capital structure. In addition, Verigy’s board has authorized an annual stock repurchase program of up to 10% of the Verigy’s current outstanding shares, effective for approximately 12 months following the transaction. The repurchases are expected to be funded from available cash and short-term investments. The odd lot repurchase and stock repurchase program are both subject to shareholder approval at Verigy’s next shareholder meeting.

Verigy provides advanced semiconductor test systems and solutions used in design validation, characterization, and high-volume manufacturing test. Additional information about Verigy can be found at www.verigy.com.

LTX-Credence is a global provider of ATE solutions designed to deliver value through innovation enabling customers to implement best-in-class test strategies to maximize their profitability. Additional information can be found at www.ltxc.com.

Merger information

For more information about the merger, visit http://investor.verigy.com/ and http://investor.ltx-credence.com/.

This communication may be deemed to be solicitation material in respect of the proposed transaction between Verigy and LTX-Credence. In connection with the transaction, Verigy and Holdco will file a registration statement on Form S-4 with the SEC containing a joint proxy statement/prospectus. The joint proxy statement/prospectus will be mailed to the shareholders of Verigy and LTX-Credence. Investors and shareholders of Verigy and LTX-Credence are urged to read the registration statement and joint proxy statement/prospectus when it becomes available because it will contain important information about Verigy, Holdco, LTX-Credence and the proposed transaction. The registration statement and joint proxy statement/prospectus (when they become available), and any other documents filed by Verigy, Holdco or LTX-Credence with the SEC, may be obtained free of charge at the SEC’s website at www.sec.gov. In addition, investors and security holders may obtain free copies of the documents filed with the SEC by Verigy and LTX-Credence by contacting, respectively, Verigy Investor Relations by e-mail at [email protected] or by telephone at 1-408-864-7549 or by contacting LTX-Credence Investor Relations by e-mail at [email protected] or by telephone at 1-781-467-5063. Investors and security holders are urged to read the registration statement, joint proxy statement/prospectus and the other relevant materials when they become available before making any voting or investment decision with respect to the proposed transaction. Verigy, LTX-Credence and their respective directors and executive officers may be deemed to be participants in the solicitation of proxies from their shareholders in favor of the proposed transaction. Information about the directors and executive officers of Verigy and LTX-Credence and their respective interests in the proposed transaction will be available in the joint proxy statement/prospectus. Additional information regarding the Verigy directors and executive officers is also included in Verigy’s proxy statement for its 2010 Annual Meeting of Shareholders, which was filed with the SEC on February 23, 2010. As of February 12, 2010, Verigy’s directors and executive officers beneficially owned approximately 1,595,151 shares, or 2.7 percent, of Verigy’s ordinary shares. Additional information regarding the LTX-Credence directors and executive officers is also included in LTX-Credence’s proxy statement for its 2011 Annual Meeting of Stockholders, which was filed with the SEC on November 8, 2010. As of September 30, 2010, LTX-Credence’s directors and executive officers beneficially owned approximately 1,940,204 shares, or 3.9 percent, of LTX-Credence’s common stock. These documents are available free of charge at the SEC’s web site at www.sec.gov and from Verigy and LTX-Credence, respectively, at the e-mail addresses and phone numbers listed above.

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(November 17, 2010) — Rochester Electronics, authorized manufacturer and distributor of end-of-life and mature semiconductors, has expanded its space-level continuing manufacturing services and product offering to provide a continuous, long-term source of certified semiconductor devices.

Since many manufacturers are discontinuing production of space-level parts due to the rigorous certification processes and expansive infrastructure required to manufacture, test, and store these low-volume parts, electronics manufacturers are often left with few places to turn for authorized space-level solutions. Contractually licensed by more than 60 original manufacturers, Rochester currently has more than two million space-level semiconductor devices in stock. In addition to the space-level finished goods inventory, Rochester is licensed to continuously manufacture space products from such manufacturers as National, Texas Instruments, Fairchild, and others.

Rochester’s combination of semiconductor re-creation and continuing manufacturing is a cost-effective and time-saving alternative to system re-design when critical semiconductors are no longer available from the original manufacturer. Rochester’s advanced re-creation process provides customers with a replicated device that matches the original semiconductor’s physical features, layer-by-layer and pin-for-pin, and is guaranteed to perform exactly as the original.

As an approved member of the Class V Qualified Manufacturer List (QML) by the Defense Supply Center of Columbus (DSCC), Rochester manufactures devices that meet MIL-PRF-38535 space-level certification requirements. This certification verifies Rochester Electronics’ capabilities in manufacturing processes, materials, and highly defined test flow to ensure the production of reliable parts that are electrically stable and can withstand harsh environmental stresses.

"Our unique Semiconductor Replication Process (SRP) guarantees that replicated devices perform as effectively as the original semiconductor devices. Rochester has successfully completed 83 semiconductor replication projects in the last 18 months and is currently engaged in more than 30 additional re-creation projects," said Paul Gerrish, co-president of Rochester Electronics. "In addition, we also maintain a large inventory of space-level parts to keep lead times as short as possible."

Rochester Electronics’ space-level certification and manufacturing capabilities enable the company to provide continuing long-term support for military and aerospace programs. For more information about Rochester Electronics’ space-level products, please visit http://www.rocelec.com/products/military_space_products/.

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(November 17, 2010 – Marketwire) — Verific Design Automation and Veridae Systems jointly announced that the Verific front-end software has been licensed to Veridae for inclusion in the new Clarus family of debug and validation products.

Verific’s Verilog analyzer and static elaborator is a platform for parsing the IEEE Verilog standard, allowing Clarus to work with a comprehensive internal representation of a register transfer level (RTL) design rather than the original Verilog language. Verific’s tools are tightly integrated with the Clarus family, technology based upon research activity at the University of British Columbia (UBC).

The Clarus family of products provides visibility into complex systems on chip (SoCs), field programmable gate arrays (FPGAs) and application specific integrated circuits (ASICs) at all stages of validation, allowing engineers to quickly pinpoint and understand unexpected behaviors, correct problems, and rapidly move devices into production. Debug problems that previously required weeks, or even months, can be resolved in hours.

Veridae chose Verific based on its reputation in the electronic design automation (EDA) and semiconductor community as the supplier of de facto standard front-end software for hardware description language (HDL) design. In addition to supplying the front-end software, Verific’s founder and president Rob Dekker provided support on the best technical approaches to interfacing the Verific software with the Clarus tools.

Veridae Systems Inc. provides debug and validation technology that enables engineers to bring complex ICs from prototype to production. Learn more at http://www.veridae.com/

Verific Design Automation provides front-end software supporting SystemVerilog, Verilog and VHDL design. Learn more at www.verific.com.

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(November 15, 2010) — SPP Process Technology Systems (SPTS) opened its new facility in San Jose, CA, the home for SPTS’ Thermal Products Division, and sales and support headquarters for North America. The Thermal Products Division was relocated from Scotts Valley, CA. Senior technical editor Debra Vogler attended and shares this report.

The new San Jose facility comprises a manufacturing space of approximately 28,000 square feet, with an additional 17,000 square feet in warehouse space. More than 80 employees will be serving the company’s global customer base out of the San Jose office.

Debra Vogler interviewed SPTS president & CEO, William Johnson, at the ribbon-cutting ceremony. Johnson told ElectroIQ that the company is pursuing alternative markets it believes are under-served by the major players: MEMS, LEDs, packaging, and compound semiconductors. In particular, as larger wafers are used in these sectors, Johnson says that annealing and heat treating will not be able to be done by horizontal furnaces, so the company’s technology will be a good fit.

Listen to Johnson’s interview: Download or Play Now

In October 2009, Sumitomo Precision Products (SPP) acquired assets of Aviza Technology and subsequently integrated them with Surface Technology Systems (STS) into the newly-formed SPTS. In 2010, SPTS has experienced tremendous growth, on course to triple revenue compared to the combined pre-acquisition entities in 2009.

SPTS is a wholly-owned subsidiary of Sumitomo Precision Products Co., Ltd, and designs, manufactures, sells, and supports advanced semiconductor capital equipment and process technologies for the global semiconductor industry and related markets.  For more information, visit www.spp-pts.com

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November 15, 2010 – Several analysts reporting from talks at AMD’s analyst day in Sunnyvale, CA, came away with the company’s for profitable growth and new products coming down the pipeline — and if its leading-edge manufacturing partners can execute, the company could offer a new challenge to longtime rival Intel.

The company has a clear focus on profitable growth, eyeing 10%-15% unit growth for MPUs and GPUs in 2011 and 44%-48% gross margins (up from 40%-45%) and a better product mix and lower opex of 35% (vs. 37%), notes John Pitzer from Credit Suisse. Moving to wafer-based pricing (from 2Q) and transitioning away from SOI on 28nm should help those margin targets, adds Doug Freedman of Gleacher & Co.

Pitzer is bullish on the company’s slated 1Q11 ramp of 40nm (via TSMC) single-chip processor + graphics "Brazos" platform for notebooks and netbooks, which he thinks could compete favorably with Intel’s 32nm Sandybridge and give "modest upside" to its notebook share. AMD’s 32nm "Llano" (made at GlobalFoundries) for midstream notebooks should start shipping in mid-2011 followed in 2012 by a 28nm version for netbooks/tablets. A 32nm "Bulldozer" chip (6-16 core variants) for servers is due in 2H11 (though a demo, according to Doug Freedman of Gleacher & Co., was "rather uninspiring"). Those offerings for notebooks/netbooks and servers "could result in AMD’s most competitive MPU line-up in 3+ years," Pitzer notes.

Execution in fleshing out that lineup is critical, though, the analysts agree, particularly with GlobalFoundries and 32nm-28mm manufacturing. Freedman notes AMD management "quickly dispelled" rumors of 32nm yields slipping again and they instead pointed to "a healthy current ramp (1H11 volume shipments) to support a 2011 product cycle" and the 28nm version ready to sample in late 2011 and ramp volume by year’s end. Nonetheless, he agrees that there needs to be visible "’meat-on-bones’ execution and volume silicon before putting all doubts to rest."

AMD seems to have plateaued at 18%-19% share in computing, by far its biggest revenue slice (73%), and being one generation behind Intel in process node (now 45nm) and a "weak roadmap to compete vs. Intel’s Atom into netbooks/tablets and Nehalem into servers" is unlikely to move the marketshare needle "until 2011 at the earliest," Pitzer suggests. Nevertheless, AMD does seem committed to closing that gap with Intel, notes FBR Research’s Craig Berger. "While AMD’s 32nm delays continue to disappoint investors, we do think AMD continues to make progress on closing the process node gap vs. Intel, and is improving its product offering with its Fusion products integrating better graphics functionality than what Intel will offer in Sandybridge," he writes.

by LeRoy Winemberg, Freescale Semiconductor, and Ken Butler, Texas Instruments

November 3, 2010 – As process geometries drop below 65nm, the differences between design models and manufactured silicon becomes unacceptably large. Material variability increases dramatically, and the results can be very unpredictable as far product performance. Up to this point, the industry-wide solution has been to use large guardbands to compensate for the delta between models and silicon. However, the use of excessive guardbanding is expensive as it tends to leave a lot of performance on the table, makes timing closure more difficult, is typically inaccurate, and in the end usually leads to lost revenue.

In a panel held at this week’s IEEE’s International Test Conference (ITC), "How smart does our silicon need to be," experts from Texas Instruments, Freescale Semiconductor, IBM, the U. of Connecticut, and the U. of Minnesota discussed methods that have been tried to help close this gap between model and silicon reality. These approaches include better pre-silicon characterization techniques and data collection, static timing analysis (STA), more recently statistical STA, and others. The consensus: with increasing random variability and increasing impact of aging effects on design reliability a gap exists that is expensive in terms of time and money.

All panelists agreed that a new approach is required to solve this problem and that a viable solution is the use of a variety of "sophisticated" on-chip sensors/monitors — i.e., embedded circuits that are more than just simple ring oscillators — to collect data from the manufactured silicon itself. The benefit of this approach is that the data collected on-chip by these circuits/sensors could be used to tune the design models for subsequent designs as proposed above.

Profs. Sachin Sapatnekar (UMinn) and Mohammad Tehranipoor (UConn) proposed this idea be taken a step further, with these sensors used by the design to adapt itself to aging/reliability effects (which can vary both temporally and spatially but not always in a uniform fashion), as well as process variations, to enable continued operation at an optimum or near-optimum point. Also, self-correction could possibly be used either at manufacturing test to increase yield, or the field to increase quality, or both.

One downside of this approach, pointed out Gordon Gammie of Texas Instruments, is the area overhead of these small circuits and their support infrastructure. If these self-tuning circuits are either inaccurate or designed improperly (i.e. without a proper understanding of their impact on the design of the "resilient" circuit itself), the financial benefit from this sensor-based self-tuning/adaptation can be lost. For example, what controls should be available to the sensor/monitor self-adaption/tuning? What about supply voltage, frequency, adaptive body bias or control of islands? And there are likely many other issues. The wrong balance/mix could result in the loss of performance, power, and reliability.

Panelist Phil Nigh of IBM was bullish on the use of these embedded circuits. He felt this idea can be further extended so that these embedded circuits can also be used for design characterization, manufacturing debug, and diagnostics — and some fraction of these circuits could even be provided to the end customer for debug and characterization at the card and system-level. Standards would be needed for connection and control of these on-chip instruments, such as the proposed P1687 standard from IEEE.

In closing, these panelists called for more research across both academia and industry on this cutting-edge topic, and the best approach for sub-65nm silicon designs. Questions under consideration are clear: which embedded circuits make the most sense (aging, enablement of more aggressive design, characterization, debug, etc.), is standardization necessary and if so how much, or are these embedded circuits not necessary in the first place because there are better approaches to the problem?

LeRoy Winemberg, ITC panel coordinator, is design-for-test manager in Freescale Semiconductor’s microcontroller solutions group. Kenneth M. (Ken) Butler, ITC panel moderator, is the chief design-for-test technologist in Texas Instruments’ analog engineering operations group.