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TechInsights-Logo-Colour

Date: April 24, 2018 at 1:00 pm ET

Free to attend

Length: Approximately one hour

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Since 2006, many of new 3D NAND Flash cells have been proposed and commercialized on the market. Already, we have seen 3D NAND cell structure up to 64L/72L with single or multi-stack NAND string architecture. The memory density on Micron/Intel’s 64L 3D NAND 256 Gb/die reached 4.40 Gb/mm2 (256 Gb/die). In this session, we’ll overview 3D NAND Flash roadmap, products, cell design, structure, materials and process integration. The 3D NAND cell architecture from major NAND manufacturers including Samsung TCAT V-NAND, Toshiba/Western Digital BiCS, SK Hynix P-BiCS and Micron/Intel FG CuA will be reviewed and compared. Current and future technology challenges on 3D NAND will be discussed as well.

Speaker:

Dr_ Jeongdong ChoeDr. Jeongdong Choe, Senior Technical Fellow, TechInsights

Jeongdong Choe is a Senior Technical Fellow for TechInsights. He has a Ph.D. in electronic engineering and over 26 years’ experience including 100+ filed/issued patents in semiconductor process integration for DRAM, (V) NAND, SRAM and logic devices. Prior to joining TechInsights in 2011, he worked as a Team Lead in R&D for SK-Hynix and Samsung where he optimized process and device architectures with state-of-the-art technologies for mass production. Jeongdong has been a member of the ‘Future Technology Roadmap’ and ‘Patent Examination’ committees at Samsung, and has led a Process Consulting Group for advanced/emerging NVM devices such as STT-MRAM, ReRAM, and PCRAM and SOI/FinFET/HKMG device for 2x/1x nm future logic and memory devices. He has also written many articles including DRAM Makers Turn to New Process for Sub 2x/1x nm Cells, and Comparing Leading-Edge 2x/1x nm NAND Flash Memories. Jeongdong annually produces a widely distributed roadmaps for Memory Technology.  At Samsung, as Team Lead of NAND FLASH Process Architecture, he advanced next-generation devices, including 42 nm, 35 nm, 27 nm, 21 nm and 19 nm process nodes with optimized DPT (double patterning technology) for 3x and 2x devices and TPT (triple patterning technology) for 1x devices, as well as for sub-20 nm terabit generation for 3D-NAND, including TCAT and VG-NAND architecture.

Sponsored by Tech Insights:

For over 25 years TechInsights has been a trusted patent and technology partner to the world’s largest and most successful companies including 37 of the top 50 U.S. patent holders. By revealing the innovation others can’t inside the broadest range of advanced technology products, we prove patent value and enable business leaders to make the best, fact-based IP and technology investment decisions.

By David W. Price, Douglas G. Sutherland and Jay Rathert

Author’s Note: The Process Watch series explores key concepts about process control—defect inspection, metrology and data analysis—for the semiconductor industry. This article is the second in a five-part series on semiconductors in the automotive industry. In the first article, we introduced some of the challenges involved in the automotive supply chain and showed that the same defects that cause yield loss are also responsible for reliability issues. In this article, we discuss the connection between baseline yield and baseline reliability and present ways that both can be improved.

The strong correlation between semiconductor IC yield and reliability has been well studied and documented. The data shown in figure 1 demonstrates this relationship. Similar outcomes have been shown at the lot, wafer and die location level. Simply put, when yield is high, reliability follows suit. As discussed in the first article of the Process Watch Automotive series, this yield-reliability correlation is not unexpected, since the defect types that cause die failures are the same as those that cause early reliability problems. Yield and reliability defects differ primarily by their size and where they occur on the device pattern in the die.

Figure 1. Data demonstrating the strong correlation between IC device reliability and yield.1

Figure 1. Data demonstrating the strong correlation between IC device reliability and yield.1

It follows that reducing the number of yield-killing defects in the IC manufacturing process will increase baseline yield and simultaneously increase device reliability in the field. Recognizing this fact, fabs serving the automotive market are faced with two critical questions. The first is economic in nature: what is the appropriate level of investment of time, money and resources in yield improvement to create the needed reliability gains? The second question is technical: what are the best defect reduction methodologies for boosting the baseline yield to the necessary levels?

For fabs that make consumer devices (ICs for mobile phones, tablets, etc.), “mature yield” is defined as the point where further improvements in yield no longer warrant the investment of time and resources. As a product matures, yield tends to stabilize at some high value, but usually well below 100%. Instead of pursuing higher yield, it makes more economic sense for the consumer fab to reallocate resources to developing the next design node’s processes and devices, or to reducing costs to improve the profitability of their legacy node.

For automotive fabs, the economic decision on whether to invest more to increase yield extends beyond the typical marginal revenue determination. When there is a reliability issue, the automotive IC manufacturer will likely bear the cost of expensive and time-consuming failure analysis, and will be held financially liable for field warranty failures, recalls and potential legal liabilities. Given that automotive IC reliability requirements are as much as two to three orders of magnitude higher than consumer IC requirements, automotive fabs must achieve higher baseline yield levels. This requires a new way of thinking about what constitutes “mature yield.”

Figure 2 highlights the difference in mature yield between consumer and automotive fabs. As either type of fab moves up the yield curve, almost all systematic sources of yield loss have been resolved. The remaining yield loss is primarily due to random defectivity, contributed by either the process tools or the environment. A consumer fab may adopt a “good enough” approach to yield and reliability at this point. However, in the automotive industry, fabs employ a continuous improvement strategy to push the yield curve even higher. By driving down the incidence of yield-limiting defects, automotive fabs also reduce latent reliability defects, thereby optimizing their profits and mitigating risk.

Figure 2. In a consumer device fab (yellow line), the top of the yield curve (Yield versus Time) is limited by diminishing returns to profitability for increased investment in defect reduction. The automotive fab yield curve, shown by the blue dashed line, also factors in reliability. Additional improvement to baseline yield must be made by automotive fabs to meet the parts per billion quality requirements. The purple shaded area highlights the difference in yield between consumer and automotive fabs – a difference that’s primarily related to process tool defectivity.

Figure 2. In a consumer device fab (yellow line), the top of the yield curve (Yield versus Time) is limited by diminishing returns to profitability for increased investment in defect reduction. The automotive fab yield curve, shown by the blue dashed line, also factors in reliability. Additional improvement to baseline yield must be made by automotive fabs to meet the parts per billion quality requirements. The purple shaded area highlights the difference in yield between consumer and automotive fabs – a difference that’s primarily related to process tool defectivity.

The automotive supply chain – from OEMs to Tier 1 suppliers to IC manufacturers – is adopting a mindset that “every defect matters” in pursuit of a Zero Defect strategy. They recognize that when latent defects escape the fab, the cost of discovery and mitigation increases as much as 10x at every additional level of the supply chain. As such, the existing over-reliance on electrical test needs to be replaced by a strategy where latent failures are stopped in the fab where the cost is lowest. Only by implementing a methodical defect reduction program will a fab move towards the Zero Defect goal and be able to pass the stringent audits required by automobile manufacturers.

In addition to robust inline defect control capability, some of the defect reduction methods that automotive purchasing managers look for include:

  • Continuous Improvement Program (CIP) for baseline defect reduction
  • Golden Tool Work Flow
  • Dog Tool Programs

Continuous Improvement in Baseline Defect Reduction

The foundation of any rigorous baseline defect reduction plan is the inline defect strategy. To successfully detect the defects that affect yield and reliability of their design rules and device types, a fab’s inline defect strategy must include both an appropriate process control toolset and an adequate sample plan. The defect inspection systems utilized must produce the required defect sensitivity, be maintained to specifications and utilize well-tuned inspection recipes. The sample plan must be set for the right process steps at sufficient frequency to quickly flag process or tool excursions. Additionally, there should be sufficient inspection capacity to support a control plan that expedites excursion detection, root cause isolation and WIP-at-risk traceability. With these elements, an automotive fab should achieve a successful baseline defect reduction plan that can demonstrate positive yield trends over time, provide goals for further improvement, and equal industry best practices.

Within a baseline defect reduction plan, one of the biggest challenges is answering the question: where did this defect come from? The answer is often not straightforward. Sometimes the defect is detected many process steps away from the defect source. Sometimes the defect becomes apparent only after the wafer has gone through several other process steps that “decorate” it – i.e., make it more visible to inspection systems. A Tool Monitoring strategy helps resolve the question surrounding a defect’s origin.

In Tool Monitoring / Tool Qualification (TMTQ) applications, a bare wafer is inspected, run through a specific process tool (or chamber) and then inspected again (figure 3). Any new defects found on the wafer with the second inspection must have been added by that specific process tool. The results are unequivocal; there is no question about the defect’s origin. Automotive fabs pursuing a Zero Defect standard recognize the benefit of a Tool Monitoring strategy: with sensitive inspection recipes, appropriate control limits and out-of-control action plans (OCAP), the sources of random yield loss contributed by each process tool can be revealed and addressed.

Figure 3. After baselining the bare wafer with a “pre” inspection, it can be cycled through some or all process tool steps. The “post” inspection reveals defects added by the process tool.

Figure 3. After baselining the bare wafer with a “pre” inspection, it can be cycled through some or all process tool steps. The “post” inspection reveals defects added by the process tool.

Furthermore, when a process tool’s contribution of adder defects is plotted over time, as in figure 4, it provides a record of continuous improvement that can be audited and used to set future defect reduction goals. The defects from every tool in the fab can be classified to generate a defect library that can be referenced for failure analysis of field returns. This approach requires very frequent tool qualification – at least once per day – and is usually used in conjunction with a Golden Tool Work Flow or Dog Tool Programs, discussed below.

Figure 4. Continuous improvement in tool cleanliness over time. The source of the problem is unambiguous and objective defect reduction targets can be set on a quarterly or monthly basis. In addition, comparing the defectivity of two process tools can show which tool is cleaner. This helps guide tool maintenance activities to pinpoint the cause of the differences between the tools.

Figure 4. Continuous improvement in tool cleanliness over time. The source of the problem is unambiguous and objective defect reduction targets can be set on a quarterly or monthly basis. In addition, comparing the defectivity of two process tools can show which tool is cleaner. This helps guide tool maintenance activities to pinpoint the cause of the differences between the tools.

Golden Tool Work Flow

A Golden Tool Work Flow is another strategy used by fabs to reach the Zero Defect standard required by the automotive industry. With a Golden Tool Work Flow or Automotive Work Flow (AWF), the wafers for automotive ICs only go through the best process tools in the fab, requiring that the fab knows the best tool for any given process step. To reliability determine which tool is best, fabs leverage data from inline and tool monitoring inspections, and then only use those tools for the Automotive Work Flow. Restricting automotive wafers to a single tool at each process step can lead to longer cycle times. However, this is usually preferable to sending automotive wafers through process flows that suffer from higher defect levels that can lead to reliability issues. When coupled with a methodical continuous improvement program, most fabs can usually get multiple tools qualified for AWF at each step by setting quarterly targets for defect reduction.

Because it is a difficult method the scale up, the Golden Tool Work Flow is best suited for fabs where only a small percentage of WIP is automotive. For fabs in high volume automotive production, a more methodical continuous improvement program, such as the Dog Tool approach described below, is preferred.

Dog Tool Programs

A Dog Tool Program is the opposite of a Golden Tool Work Flow as it proactively addresses the worst process tool – the dog tool – at any given process step. Fabs that have been most successful in driving down baseline defectivity often have done so by adopting a Dog Tool Program. They first take down the dog tool at every process step and work on that tool until it is better than the average of the remaining tools in that set. They repeat this process over and over until all tools in the set meet some minimum standard. An effective Dog Tool program requires that the fab has a methodical Tool Monitoring strategy to qualify each process tool at each step. At a minimum, this qualification procedure should be done daily on each tool to ensure there is sufficient data so that an ANOVA or Kruskal-Wallis analysis can identify the best and worst tools in each set. A Dog Tool Program, with planned process tool downtime, is the one of the fastest ways known to bring an entire fab up to automotive standards. By increasing yield and reliability, this strategy ultimately improves an automotive fab’s effective capacity and profitability.

Summary

Automotive manufacturers who demand high reliability often require the fab to change their mindset about what really defines mature yield. In this article we have discussed several ways that fabs can reduce their baseline defectivity and improve reliability and yield. In the next article in this series we will discuss some of the technical considerations regarding the sensitivity of defect inspection tools and how that helps ensure chip reliability.

About the Authors:

Dr. David W. Price and Jay Rathert are Senior Directors at KLA-Tencor Corp. Dr. Douglas Sutherland is a Principal Scientist at KLA-Tencor Corp. Over the last 15 years, they have worked directly with over 50 semiconductor IC manufacturers to help them optimize their overall process control strategy for a variety of specific markets, including automotive reliability, legacy fab cost and risk optimization, and advanced design rule time-to-market BKMs. The Process Watch series of articles attempts to summarize some of the universal lessons they have observed through these engagements.

References:

  1. Mann, “Wafer Test Methods to Improve Semiconductor Die Reliability,” IEEE Design & Test of Computers, vol. 25, pp. 528-537, November-December 2008. https://doi.org/10.1109/MDT.2008.174
  2. Price, Sutherland and Rathert, “Process Watch: The (Automotive) Problem With Semiconductors,” Solid State Technology, January 2018.

Park Systems, a manufacturer of atomic force microscopes celebrated the grand opening of their European Headquarters on February 6, 2018 in Mannheim, Germany.  The new office will serve as a central European AFM research facility, providing technical sales and service with a fully equipped Atomic Force Microscopy Nanoscience Lab on site. The ceremony was attended by many around Europe including from Deutsche Bank (Germany), Schaefer South-East Europe SRL (Romania), Milexia SAS (France), ST Instruments B.V. (Netherlands),  GambettiKenologiaSrl (Italy), Promenergolab LLC (Russia), Tekno-TIP AnalitikSistemler Ltd. (Turkey) and Park Systems representatives from Europe, US and Asia.

“The European scientific community plays a critical role in expanding cutting-edge science and research across many industries, particularly at the nanoscale,” commented Ludger Weisser, the General Manager of Park Systems Europe at the ribbon-cutting ceremony. “The new Park Systems Nanoscience Lab in Europeis a landmark opportunity to provide the best-in-class AFM technology and unparalleled technical service for our European business partners to advance scientific research and development.”

The new office will provide technical, application and sales support for all European customers. As the demand for a modern AFM technology continuously grows in Europe, Park Systems recognizes the need of serving the key European scientific laboratories and research facilities with even stronger and direct support.

“Park Systems has invested significant resources into the new Park Nanoscience Lab in Europe to offer the vast European scientific community a better opportunity to use our AFM product and make side-by-side comparisons to the well-known European AFM.  We are confident that our AFM will demonstrate in Europe as it has in North America and Asia undeniable higher performance and cost efficiencies for research and production facilities,” commented James Woo, Park Systems Global Sales Manager.  “We invite European customers to our new Park Nanoscience Lab facility to use our equipment and witness for yourself why Park has been the world-leader in AFM technology since its inception.”

The Park Nanoscience Lab at the Europe Headquarters in Manheim Germany is a new branch of Park Systems and part of a growing network of Park Global Nanoscience labs including a recently opened Park Nanoscience Center at SUNY Polytech Institute in Albany, New York.The Park Nanoscience Lab will showcase advanced atomic force microscopy (AFM) systems, demonstrate a wide variety of cutting-edge applications—ranging from materials science, to chemistry and biology, to semiconductor and data storage devices—and provide hands on experience, training and service, year-round.  It will be equipped with the latest Park AFM systems, including the Park NX20, Park NX10, and Park NX-Hivac, playing a crucial role in providing the best and direct technical, application and sales support to the European audience.

“Besides the excellent AFM technology, having a direct and reliable contact partner for inquires of any matter was surely one of the most important factors for us when we chose Park Systems half a year ago,” says Francesco Simone, the junior fellow at the University of Cambridge, UK, and Park NX10 AFM user.

Park Systems, a global AFM manufacturer, has offices in key cities worldwide, including Santa Clara, California; Tokyo, Japan; Singapore; Manheim, Germany; and Suwon, South Korea. Since becoming the only public offering for an AFM business in 2015, its stock has increased by over 300% reflecting the strong growth of its business with many company-wide global initiatives for continued future word-wide success.

Radiant Vision Systems, a provider of high-resolution imaging solutions for automated visual analysis of devices and surfaces, announces the release of the INSPECT.assembly system, a new turnkey automated visual inspection station for in-line assembly verification. The INSPECT.assembly is fully-integrated with Radiant technology and configured to precise tolerances to meet production-level inspection needs of complex electronic assemblies. The INSPECT.assembly system detects the presence, position, and integrity of components including screws, cables, connectors, and other critical features before final device enclosure to automate assembly inspection.

radiant visions

“Electronics manufacturing processes today are largely automated. However, final inspection for board-based connected assemblies has lacked an effective automated solution that ensures both consistency and accuracy,” says Davis Bowling, Radiant’s Regional Account Manager for assembly verification applications. “At the final stages of production where internal components are verified – before electronics are enclosed before or after functional testing – human inspectors remain the primary inspection method. This is due to the human’s superior visual acuity and judgment over typical machine vision systems for complex visual analysis. Humans can quickly detect very subtle defects in a variety of assembly contexts, even as parts change. However, human inspection lacks an automated system’s repeatability. To apply an automated solution in these contexts, the technology must offer the same level of visual acuity and judgment to ensure failures do not escape or result after goods are shipped.”

Radiant’s new INSPECT.assembly system is a turnkey inspection station that employs ProMetric® Y imaging systems with camera resolution (up to 29 megapixels) and dynamic range (above 70 dB) far exceeding the specifications of typical machine vision systems. Applied in photometric measurement of light and color in displays and backlit components, ProMetric cameras capture fine-detail images with a level of precision that rivals human visual acuity. Because INSPECT.assembly is fully-integrated with Radiant camera, lighting, fixturing, and software, Radiant engineers are able to design each INSPECT.assembly to match the specifications of each customer application. This advanced vision technology solves critical inspection challenges through a combination of the image registration & analysis functions of the camera with proprietary machine vision “super tools” in INSPECT Software, which blend multiple machine vision software algorithms in a single tool to enable comprehensive analysis of specific features. For instance, a tool can be engineered with the unique algorithms required to locate the routing path of a cable to ensure that it is properly seated around guides on a board-based assembly.

“Capturing precise feature flaws during final inspections is critical not only for preventing functional failures in the manufacturing process, but also latent failures that may occur after shipment,” states Bowling. “A cable that is routed away from its guide may be pinched or damaged with repeated device use. A loose connector may detach with vibration. These issues may cause a device to fail after it has left the manufacturing facility, resulting in a return or potentially a broader product recall. The INSPECT.assembly’s imaging capability combined with custom-configured software allow manufacturers to catch subtle errors like these that human inspectors, standard machine vision systems, and functional testing may miss.”

Radiant’s new INSPECT.assembly system rivals human visual acuity and judgment for detecting defects while quantifying visual data for automated operations, bridging the gap between human and machine vision inspection for the most challenging assemblies. Occupying the same physical footprint as a human operator on the line, the INSPECT.assembly system easily rolls onto moving conveyers, adjusting to heights from 525-950 mm. The system features a touch screen for results monitoring, adjustment of inspection tolerances, and part changes. The system’s INSPECT Software is pre-configured with multiple inspection tool recipes specific to each part, enabling adaptability to line changeover. The system also offers reporting functionality, barcode reading, and data output for traceability of inspection results and process control to improve operations for reducing product returns and recalls.

Applied Energy Systems (AES), provider of high and ultra high purity gas systems, services, and solutions – including design, manufacturing, testing, installation, and expert field service – is showcasing the capabilities of its SEMI-GAS® Xturion™ Blixer™ to support various processes that require forming gas mixtures. The Blixer™ provides a cost-effective alternative to purchasing expensive pre-mixed gas cylinders by enabling operators to blend their own mixtures on-site in their facility.

The ultra high purity gas mixing blender is used by customers across a diverse range of industries to uniformly mix H2 and N2 concentrations in customizable ratios that meet their distinct process requirements. Mixtures can be adjusted in real-time via the system’s GigaGuard™ PLC Controller, which features a 9” Siemens color touchscreen for intuitive operation, allowing the user to fine-tune formulations on demand. This makes the system particularly appealing for high volume applications, eliminating the need to stock a variety of pre-mixed forming gas concentrations, decreasing the frequency of cylinder change-outs, reducing tool downtime, increasing productivity, and ultimately providing the end user with a significant cost savings.

The Blixer™ system is designed to provide a continuous flow of precise gas blends and includes a static mixing tube and surge/mixing tank to address dynamic flow changes and effectively maintain mix tolerances. It is also equipped with a Thermal Conductivity Hydrogen Gas Analyzer, featuring auto-calibration capability and a low flow alarm, to ensure +/- 1% blending accuracy. Its PLC Controller includes Ethernet connectivity to allow for seamless integration with a facility’s Monitoring System, and the system’s hydrogen hazardous gas detector and automatic shutdown feature alert operators during undesirable system conditions.

“We have found the Blixer™ to be especially beneficial to customers using forming gas mixtures because it gives them flexibility to custom-blend H2/N2 concentrations in the exact ratios they desire—instead of investing in expensive pre-mixed cylinders that still may not be precisely mixed to their unique process requirements,” said Greg Havrilla, Technical Inside Sales Engineer for AES. “The system’s value spans industries. We’ve seen it support laser-based technology development, semiconductor fabrication, electrically-powered vehicle manufacturing, sustainable energy solutions, and a variety of industrial manufacturing applications. Its flexibility is reflected in its ability to satisfy a range of process-driven demands.”

AES-SEMI-GAS-Xturion-Blixer-System

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Date: October 3, 2017 at 1 p.m. ET

Free to attend

Length: Approximately one hour

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Conventional planar flash memory technology is approaching critical scaling limitations that are driving the transition to 3D solutions. 3D NAND is expected to scale in height, from 16-bit-tall strings to string heights of more than 128 bits. Meanwhile NAND makers will find ways of placing these strings closer to each other through more aggressive lithography.

Join the analysts from TechInsights as they explore 3D NAND flash technology from a process, circuit and systems perspective.

Process

With the boom in 3D NAND technology over the last couple of years, all the major NAND manufacturers such as Samsung, Toshiba, Western Digital (SanDisk), Micron, Intel and SK Hynix have already released their cutting-edge 3D NAND commercial products with 64L. Compared to their previous 32L (or 36L) and 48L, memory density per unit cell array area reached up to 3.4 Gb/mm2 which is 2.7 times higher than 15 nm 2D NAND TLC. This year, the new QLC products were introduced, which further scaled development down to n+1 (96L) and n+2 (128L). Every NAND manufacturer keeps their own 3D NAND architecture, and we’ll explore them in more detail and discuss future 3D NAND technology trends and expectations.

Circuit

With the exception of the memory cell array layout, most 3D NAND flash manufacturers have similar on die peripheral circuit block arrangements, as seen in their previous planar NAND flash products, with the exception of Micron’s latest 32L flash product. In this portion of the presentation, we will look at 3D NAND die photographs and compare die cross sections to identify some of the major differences in circuit implementation and layout arrangements. Challenges in 3D NAND circuit extractions including metal line access for internal signal probing (waveform analysis), memory addressing and programming algorithms will also be discussed.

Systems

There are many similarities between implementations of SSDs, but it is their differences with the use of latest NAND flash devices (especially 3D NAND), that have become of great interest for systems analysis, and will be the topic for discussion in this segment. One of the latest systems analyzed by TechInsights showed many interesting new features and differences in operation, on even simple de-facto standard methods of operation, such as addressing a NAND flash device, as well as read-retry situations.

Speakers

Mohammad Ahmad, Architect

Mohammad Ahmad is an Engineering Solutions Architect in the IP Services group at TechInsights. He has extensive experience with the latest non-volatile semiconductor memory devices, and provides technical support and patent analysis to help global clients maximize the return on their intellectual property investments. Mohammad is responsible for leading, executing and managing large patent portfolio assessments to identify patents for assertion and divestiture and for determining and executing the required reverse engineering in support of the patent portfolios.

He specializes in reverse engineering including circuit extraction, functional testing and internal waveform probing of various semiconductor memories (NAND and NOR Flash, embedded and system memories, DRAM and SRAM). Patent claims analysis, evidence-of-use detection, claim chart documentation, prior art searches and patent/portfolio evaluation and mining.

Dr. Jeongdong Choe, Senior Technical Fellow

Jeongdong Choe is a Senior Technical Fellow for TechInsights. He has a Ph.D. in electronic engineering and over 26 years’ experience including 100+ filed/issued patents in semiconductor process integration for DRAM, (V) NAND, SRAM and logic devices. Prior to joining TechInsights in 2011, he worked as a Team Lead in R&D for SK-Hynix and Samsung where he optimized process and device architectures with state-of-the-art technologies for mass production.

Jeongdong has been a member of the ‘Future Technology Roadmap’ and ‘Patent Examination’ committees at Samsung, and has led a Process Consulting Group for advanced/emerging NVM devices such as STT-MRAM, ReRAM, and PCRAM and SOI/FinFET/HKMG device for 2x/1x nm future logic and memory devices. He has also written many articles including DRAM Makers Turn to New Process for Sub 2x/1x nm Cells, and Comparing Leading-Edge 2x/1x nm NAND Flash Memories. Jeongdong annually produces a widely distributed roadmaps for Memory Technology.

At Samsung, as Team Lead of NAND FLASH Process Architecture, he advanced next-generation devices, including 42 nm, 35 nm, 27 nm, 21 nm and 19 nm process nodes with optimized DPT (double patterning technology) for 3x and 2x devices and TPT (triple patterning technology) for 1x devices, as well as for sub-20 nm terabit generation for 3D-NAND, including TCAT and VG-NAND architecture.

Tarek Alhajj

Tarek Alhajj is an Engineering Solutions Architect in the Intellectual Property and Technical Services group at TechInsights where he creates solutions for complex technical and intellectual property problems, especially those involving memory systems.

In his previous role with the company, Tarek was an Engineering Analyst in the systems and software analysis group, where he performed in depth analysis of various circuits and systems, mostly within downstream products, through a combination of circuit extraction, electrical functional testing and literature research. He has analyzed and tested numerous commercial electronic devices for the purposes of intellectual property support, technical intelligence and research and development. His contributions to the development of reverse engineering and testing techniques, particularly for memories and memory systems such as NAND flash and SSDs, greatly enabled detailed analysis of complex systems. Tarek then moved on to Team Lead in the systems and software analysis group to lead and manage a team of engineers.

Prior to TechInsights, he worked for MOSAID Technologies as a Patent Licensing Engineer where he lead the portfolio management, including the due diligence, licensing and litigation of all flash memory and flash memory systems patent portfolios.

Tarek received a B.Eng. degree in Electrical Engineering from Carleton University, Ottawa, Canada, and an M.A.Sc. degree in Electrical Engineering from McGill University, Montreal, Canada. His studies and research focused mainly on characterization and system level behavioral modeling of complex mixed-signal circuits and systems.

Sponsored by TechInsights

For over 25 years, TechInsights has been a trusted patent and technology partner to the world’s largest and most successful companies including 37 of the top 50 U.S. patent holders. By revealing the innovation others can’t inside the broadest range of advanced technology products, we prove patent value and enable business leaders to make the best, fact-based IP and technology investment decisions. Learn more at http://www.techinsights.com.

The labor-intensive, manual process of recording precise measurements across various wafer coordinates is now programmable for automated data collection and report generation.

ACU-THIK™ is an automated thickness measurement tool incorporating dual contact probes for high accuracy inspection of semiconductor wafers. Six Heidenhain measuring devices are integrated into the ACU-THIK™ system which can be configured to accommodate wafer diameters of 100mm – 400mm and larger. Acu-Gage customers can have a system customized for their precise needs to make differential gage measurement faster and easier.

Diagnosing as well as controlling thickness, bow and warp in semiconductor wafer production is now automated when using ACU-THIK™. Users can preprogram multiple pattern operations to fulfill planned production cycles. Additionally, the system supports robotics integration to further free up operators for other important tasks.

ACU-THIK’s automated measurements can improve quality-assured production yields by:

  • Calculating wafer thickness across X/Y points to resolution and repeatability of .00025mm/.00001 inch (10 millionths of an inch)
  • Determining the amount of bow deviation in an unclamped wafer established by three or more points at equidistant locations
  • Examining the entire wafer for warp by incorporating more comprehensive data points to provide a more useful measurement of the full wafer shape
  • Accelerating throughput with 15 data points of X/Y thickness measurements in under two minutes as well as increasing accuracy of wafer thickness and flatness definitions
  • Validating pre- and post-measurement integrity of data collection for each wafer inspection – ACU-THIK™ calculates the thickness of a certified gage block prior to as well as after the wafer inspection routine is complete.

The X/Y location for each thickness data point automatically outputs to Excel for further analysis. Programming software runs on Windows 7. Both hardware and software come delivered as a turnkey system including installation and training.

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Date: Wednesday, August 9, 2017 at 1 p.m. ET

Free to attend

Length: Approximately one hour

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The slowing down of Moore’s Law even at leading CMOS Fabs due to approaching Physics limits, while at the same time the explosion in demand for chips and systems across a wide range of market segments (compact wearable / portable consumer systems, the transfer and processing of data to and from the cloud, at the high performance end specialized architectures e,g for AI) has revived interest in Dense Off Chip Integration (DOCI ), first used in MCMs (Multi Chip Modules) for mainframes some 3 decades ago.

DOCI can be a lower cost alternative to integration of many functions on a single large chip that is often associated with low fab yields at immature nodes. In the consumer end DOCI is an enabler of compactness and power efficiency. To be accepted in the high performance end DOCI must deliver electrical performance not too inferior to single chips or provide efficient package level integration of heterogeneous designs and Fab technologies e,g. Processor and Memory, that are not easily manufactured on a single wafer. In all cases dense and compact package level interconnects with low parasitics using current and emerging Advanced Packaging (AP) technologies are key to wide adoption of DOCI.

Using metrics like electrical performance, density and cost of package level interconnects we will assess various AP technologies ranging from package substrates/interposers, packages like FO WLPS, flip chip, 2.5d modules, 3d stacks such as PoP, and those using TSVs. Recent commercial examples of integrating processor to memory by different approaches to DOCI will be compared.

Lastly emerging AP technologies (substrates cheaper than dual damascene interposers and TSVs) to reduce the cost of DOCI will be compared and opportunities for further development and implementation identified.

Speakers: 

dev guptaDr. Dev Gupta, CTO, APSTL llc, Scottsdale, AZ, USA

While at Motorola and Intel, Dr. Dev Gupta invented many of the Advanced Packaging technologies ( electroplated solder bump flip chip, robotic assembly, organic substrates w/ and w/o core, pillar flip chip, integrated passives, .. ) that have become industry standards today. The micro pillar and thermocompression flip chip technology he invented at Motorola nearly 25 years ago for Gallium Arsenide PAs is now used for building 3d Memory Stacks. He pioneered and managed the transfer of these AP technologies to high volume manufacturing in both the US and Japan. At APSTL he is responsible for identifying technology gaps, developing new technologies to address them, licensing, turn key engineering of Fabs for Advanced Packaging. He also takes an active role in mentoring and training Customer Engineers. Dr. Gupta has many Patents and Publications and often teaches at Conferences the theoretical aspects of Package Level Interconnects, Advanced Packaging and Systems Optimization. The current emphases at APSTL is to lower the cost Adv. Packaging by replacing TSVs, process innovations in die stacking etc. and license them.

  • Why there is such renewed interest in DOCI, first used in Multi-Chip Modules for mainframes some 3 decades ago.
  • Hear why and how DOCI can be a lower cost alternative to integration of many functions on a single large chip that is often associated with low fab yields at immature nodes.
  • Learn how to assess various Advanced Packaging technologies using metrics such as electrical performance, density and cost of package level interconnects.

Silicon Wafer Integrated Fan-out Technology (SWIFT®) Packaging

curtisCurtis Zwenger, VP Adv. Package & Technology Integration

Curtis joined Amkor in 1999 and has held leadership roles in developing Amkor’s Fine Pitch Copper Pillar, Through Mold Via, and MEMS packaging technologies. He is currently responsible for the development and commercialization of Amkor’s Advanced Wafer Level Fan-Out package technologies, including WLFO and SWIFT®. Prior to joining Amkor, Curtis worked for Motorola. He holds a degree in mechanical engineering from Colorado State University and an MBA from the University of Phoenix.

Curtis will discuss:

  • The development of SWIFT® technology and its extension into unique 3D structures.
  • The advantages of SWIFT® designs as compared to current competing packaging technologies.
  • How the SWIFT® process is poised to provide robust, reliable, and low-cost 3D packaging solutions for advanced mobile and networking products.

 

Sponsored by Amkor Technology

Amkor Technology, Inc. is one of the world’s largest providers of state-of-the-art packaging design, assembly and test services. As a strategic partner to leading semiconductor companies and electronics OEMs, operations include over 10M ft2 of volume production, development, sales and support services in Asia, Europe and the United States. Our solutions enable customers to focus on semiconductor design and wafer fabrication while utilizing Amkor as their turnkey provider and packaging technology innovator. Additional information at: www.amkor.com.

The gate etch in a finFET process requires that 3D corners be accurately resolved to maintain a uniform gate length along the height of the fin. In so doing, the roughness of the etch surface and the exact etch depth per cycle (EPC) are not as critical as the ability of ALE to be resistant to aspect ratio dependent etching (ARDE).

Researchers Chad Huard et al. from the University of Michigan and Lam Research recently published “Atomic layer etching of 3D structures in silicon: Self-limiting and nonideal reactions” in the latest issue of the Journal of Vacuum Science & Technology A. Proper control of sub-cycle pulse times is the key to preventing gas mixing that can degrade the fidelity of ALE.

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The Figure shows that the geometry modeled was a periodic array of vertical crystalline silicon fins, each 10nm wide and 42nm high, set at a pitch of 42 nm. For continuous etching (a-c), simulations used a 70/30 mix of Ar/Cl gas and RF bias of 30V. Just before the etch-front touches the underlying SiO2 (a), the profile has tapered away from the trench sidewalls and the etch-front shows some micro-trenching produced by ions (or hot neutrals) specularly reflected from the tapered sidewalls. After a 25% over-etch (b), a significant amount of Si remains in the corners and on the sides of the fins. Even after an over-etch of 100% (c), Si still remains in the corners.

In comparison, the ALE process (d-f) shows that after 25% over-etch (e) the bottom SiO2 surface would be almost completely cleared with minimal corner residues, and continuing to 100% over-etch results in little change to the profile. The ALE process times shown here do not include the gas purge and fill times between plasma pulses; to clear the feature using ALE required 200 pulses and assuming 5 seconds of purge time between each pulse results in a total process time of 15–20 min to clear the feature. This is a significant increase in total process time over the continuous etch (2 min).

One conclusion of this ALE modeling is that even small deviations from perfectly self-limited reactions signifi- cantly compromise the ideality of the ALE process. For example, having as little as 10 ppm Cl2 residual gas in the chamber during the ion bombardment phase produced non-idealities in the ALE. Introducing any source of continuous chemical etching into the ALE process leads to the onset of ARDE and roughening of the etch front. These trends have significant implications for both the design of specialized ALE chambers, and also for the use of ALE to control uniformity.

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Date: Thursday, May 17, 2018 at 1:00 p.m. ET

Free to attend

Length: Approximately one hour

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The increased use of artificial intelligence (AI) and machine learning (ML) techniques such as deep learning is creating a myriad of both challenges and opportunities for enhancements in manufacturing in terms of improved capacity, quality, and efficiency. The semiconductor industry poses somewhat unique challenges arising from its complex, high precision and highly dynamic production environment. One key way that these challenges are being addressed in semiconductor is by using an approach called “computational process control” or “CPC” in which AI and ML are combined with subject matter expertise to provide higher quality analytical solutions. This webcast will look at the AI/ML explosion, what it means to the semiconductor industry, and how CPC is being used to enhance the benefits of these analytical techniques.

What You’ll Learn:

  • Learn how AI and machine learning can help semiconductor manufacturers improve capacity, quality, and efficiency.
  • Find out why the semiconductor industry poses somewhat unique challenges arising from its complex, high precision and highly dynamic production environment.
  • Hear about how new computational process control (CPC) techniques, which combine AI, ML and subject matter expertise, provide higher quality analytical solutions.

Speaker: 

James Moyne_SpeakerDr. James Moyne is a consultant for standards and technology in the Applied Global Services group at Applied Materials. He received his Ph.D. degree from the University of Michigan, where he is currently an associate research scientist in the Department of Mechanical Engineering. James has been involved with machine learning solutions for the semiconductor industry since the early 90s starting with his founding of MiTeX Solutions, Inc. in 1995, which provided the first 3rd party advanced process control solutions for semiconductor manufacturing. He has experience in advanced process control, prediction technology (predictive maintenance, virtual metrology, and yield prediction), and big data technology (focusing on machine learning and data quality); and is the author of a number of refereed publications and patents in these areas. James is currently chair of the Factory Integration Technical Working Group of the International Roadmap for Devices and Systems, and is technical chair of the annual Advanced Process Control conference for the microelectronics industry (www.apcconference.com).

Sponsored by XtremeEDA: 

Founded in 2002, XtremeEDA is a preferred North American based provider of front-end design and verification services for the semiconductor industry.  Our team is unparalleled – with employees averaging 20+ years of semiconductor industry experience and expertise that spans most major sectors.

Our business approach emphasizes enduring and transformational relationships to employ creative solutions that enable extraordinary results for all stakeholders. For more information, visit us at: www.xtreme-eda.com.