Device Architecture

DEVICE ARCHITECTURE ARTICLES



Leti touts planar SOI for LP 22nm

10/21/2009 

French R&D organization Leti says its work with SOI-based planar CMOS meets requirements for low-power (LP) 22nm node device requirements, e.g. consumer electronic devices such as 4G mobile phones.

IMEC: 3D challenges, integrating DRAM on logic

10/20/2009 

Bart Swinnen, IMEC's director of interconnect and process technology unit, discusses with SST/AP the research center's 3D program, from its annual press event in Leuven, Belgium.

ITRI adds AMAT tools for 3D IC work

10/16/2009 

Taiwan's Industrial Technology Research Institute (ITRI) will add Applied Materials to its partners for developing 3D chip stacking technology, by placing "a full line" of AMAT processing tools in its labs.

Leti: Cu-based catalysts can make Si nanowires

10/08/2009 

Researchers at French R&D institute Leti say they have overcome incompatibilities of metallic catalysts with CMOS manufacturing in order to make silicon nanowires, bridging a gap between CMOS technology and bottom-up growth of nanowires and enabling new functionality to be added to chipmaking processes.

Reports: US to challenge Elpida subsidies

10/06/2009 

The US is ready to press the World Trade Organization to investigate alleged government subsidies of memory chip maker Elpida Memory, a move that would have significant implications in both Japan and Taiwan, according to multiple reports.

IMEC Tech forum: Leading-edge "insight," radio chips, multithreaded processors

10/06/2009 

Among a spate of presentations at IMEC's annual Technology Forum this week, the European R&D consortium trotted out a new program for foundries and fabless companies, an "incubation" pact with TSMC, and developments in multithreading and radio chips.

IMEC sets major step towards 3D integration of DRAM on logic

09/30/2009 

IMEC and its 3D integration partners have taped-out Etna, a new 3D chip integrating a commercial DRAM chip on top of a logic IC. The new 3D stack resembles as close as possible to future commercial chips. It consists of a 25µm thick logic die on top of which a commercial DRAM is stacked using through-silicon vias (TSVs) and micro-bumps.

New cell could extend DRAM scalability improve performance

09/29/2009 

Researchers from Yale University and the Semiconductor Research Corp. discuss development of a new DRAM cell using ferroelectric layers that could significantly improve the technological and market competiveness for DRAM technology.

IC Insights: V-shaped industry recovery is here, but whither capex?

09/18/2009 

Key metrics presented and analyzed at IC Insights' fall forecast seminar suggest the industry is enjoying a strong, swift recovery -- but a disconnect between rising demand and sluggish capex could cause problems soon.

Elpida stacks 8 DRAMs with TSV

09/16/2009 

Elpida Memory recently pushed vertical stacking of DRAM to new heights by connecting eight 1G chips using through-silicon vias, creating what it calls the world's largest-capacity DRAM with ~8GB of storage.

Gartner darkens 2009 outlook, but brightens 2010-2012

09/14/2009 

September 14, 2009 - A 2H09 rebound in the chipmaking equipment sector won't be enough to make up for the horrid performance in late 2008 andearly 2009, but analyst firm Gartner does see much better times in 2010 and beyond, according to its newly updated forecast.

DALSA to play major role in Quebec Microelectronics Innovation Center

09/04/2009 

DALSA Semiconductor VP/GM Claude Jean talks with SST about the new $218M microelectronics center being formed in Quebec, and how the company will contribute to its focus on MEMS and 3D wafer-level packaging and vice-versa.

HDD patterned media using jet-and-flash imprint lithography

09/04/2009 

This article from Molecular Imprints describes how te addition of patterned media to HDD disk fabrication presents a number of new challenges to magnetic media manufacturers, and how J-FIL systems and materials can provide the foundation for successful high-volume manufacturing.

Japan's chipmakers mapping out independent futures

09/01/2009 

Semiconductor units of Japan's electronic giants are struggling to figure out their place in the future, battered by the global economic slump and pressured to reduce dependence on their parents.

Bart Swinnen, IMEC, Discusses TSVs

08/28/2009 

In this video interview from SEMICON West 2009, Bart Swinnen, reviews the established interconnect bonding and through-silicon via (TSV) technologies at the system-integration level. He also discusses the newer TSV possibilities and different application-specific TSVs.

Elpida takes 2Q DRAM crown

08/25/2009  Better pricing for specialty DRAM made Elpida the poster child of the DRAM market in 2Q09, according to data from iSuppli. And signs point to continued tight supplies of DDR3 as firms continue to delay capex plans that would support their 5x-node migration.

siXis partners with SVTC to commercialize silicon circuit boards

08/24/2009  August 24, 2009 -- SVTC was chosen by technology startup siXis, Inc. to supply silicon manufacturing services for their compact, high-speed embedded computing modules that bridge the gap between programmable devices and costly, customized semiconductors.

Bosch buys Akustica, gains MEMS consumer inroads

08/21/2009  August 21, 2009: In what seems to be a bid to expand beyond its auto position into an increasingly crowded (and promising) consumer sphere, Robert Bosch's US division is acquiring MEMS microphone maker Akustica.

Analyst: Image sensors end growth run, entering smaller cycles

08/20/2009  August 19, 2009: Image sensor sales will decline 11% in 2009 to $6.4B, the first decline in at least 12 years, and after a decade of 22% CAGR will settle into single-digit growth in coming years, according to a new report from Strategies Unlimited.

Samsung upgrading Austin site to 300mm NAND

08/18/2009  Samsung is revamping its 200mm memory line in Austin, TX, upgrading it to a 300mm NAND line, reportedly in a push to support solid-state drives. The kicker: hundreds of jobs will be lost.




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Environment, Safety & Health

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The semiconductor industry is an acknowledged global leader in promoting environmental sustainability in the design, manufacture, and use of its products, as well as the health and safety of its operations and impacts on workers in semiconductor facilities (fabs). We will examine trends and concerns related to emissions, chemical use, energy consumption and worker safety and health.

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Wafer Processing

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As the industry moves to 10nm and 7nm nodes, advances in wafer processing – etch, deposition, planarization, implant, cleaning, annealing, epitaxy among others – will be required. Manufacturers are looking for new solutions for sustained strain engineering, FinFETs, FDSOI and multi-gate technologies, 3D NAND, and high mobility transistors.

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