Device Architecture

DEVICE ARCHITECTURE ARTICLES



CSP Test Socket Features Adjustable Pressure Pad

06/25/2009  Aries Electronics, an international manufacturer of standard, programmed and custom interconnection products, now offers its 27mm CSP (chip scale package)/MicroBGA (ball grid array) test and burn-in sockets with an optional adjustable pressure pad.

Interactive data eyeglasses opens up new worlds

06/09/2009  June 9, 2009: A group of scientists at the Fraunhofer Institute for Photonic Microsystems IPMS is working on a device which incorporates eye tracking to create bidirectional "data eyeglasses," opening up hands-free applications generally associated with spy movies and fighter pilots.

Luc Van den hove helms IMEC, discusses strategy

06/09/2009  Amid preparations for IMEC's 25th anniversary celebration, SST spoke with Luc Van den hove, now president/CEO of European R&D consortium IMEC, who discussed the research center's strategy and the keys to its success over the years.

ALD enables thin films for next-generation flash and NVM

06/08/2009  In this article, ASM and Numonyx explain that ALD of high-k dielectrics and novel metal layers will be prevalent in producing next-generation NVMs, because it has been shown to address many of the issues related to speed, endurance, and reliability of these devices.

GA Tech: Graphene could replace Cu for IC interconnects

06/04/2009  Researchers at Georgia Tech say they have experimentally demonstrated the potential for graphene to replace copper for on-chip interconnects and help extend performance scaling for silicon-based ICs.

Applied targets 22nm copper barrier or seed PVD

06/02/2009 

Applied Materials exec Marek Radko gives SST a tour of its new Endura CuBS RFX PVD system, qualified for copper barrier/seed deposition technology at 32nm and 22nm for production of logic and flash memory.

Applied targets 22nm copper barrier/seed PVD

06/02/2009  Applied Materials exec Marek Radko gives SST a tour of its new Endura CuBS RFX PVD system, qualified for copper barrier/seed deposition technology at 32nm and 22nm for production of logic and flash memory.

ECS Days 4-5: Emerging dielectrics, SOI, graphene, batteries

06/01/2009  Day 4 of the ECS Spring 2009 Meeting saw the continuation of symposia on flexible electronics, emerging dielectrics, SOI, and graphene, reports Techcet's Michael A. Fury in his exclusive daily blog for SST. And discussions of battery/energy and SOI device technology indicated the global breadth of research interest and funding in these fields.

ECS Day 3: Signs of life after all

05/29/2009  Day 3 of the ECS Spring 2009 Meeting showed signs of normalization: good sized audiences in right-sized rooms, and presentations proceeding as scheduled, reports Techcet's Michael A. Fury in his exclusive daily blog for SST. Topics today touched on work in semiconductor-biocell interfaces, organic TFTs, alternative phase-change material, high-k dielectrics, SiGe PMOS/NMOS integration, post-32nm MugFET designs, and graphene aerogels.

ECS Day 2: "Tantalizing" ZnO; cost-effective microfluidics; "Fox News flu"

05/28/2009  Techcet's Michael A. Fury reports exclusively for SST from this week's spring meeting of the Electrochemical Society. On tap for Day 2: "Tantalizing" advancements in ZnO as a future semiconductor material, cost-effective 2D microfluidics, triple-junction solar cells, a supersensitive toxin-detecting HEMT device, and feeling the effects of "Fox News flu."

Memory sector upended, driven by 3D packaging tech, says Yole

05/15/2009  New integration trends and disruptive packaging technologies, notably 3D TSVs, will cause major technical changes in the memory semiconductor sector, but ultimately pave the way for future growth, according to a recent report from Yole Développement.

Yole Report: Memory Packaging & Integration Trends

05/08/2009  The memory semiconductor industry is about to go through major technological changes as new integration trends and disruptive packaging technologies pave the way to the future growth, reports Yole. The study presents the end applications driving the use of 3D integrated memories and their key players. It also includes an overview of the memory packaging market, its forecasted evolutions with new applications and growth in flash and DRAM.

IMEC's "noble" efforts to integrate nanophotonics with hi-speed CMOS

05/06/2009  IMEC researcher Pol Van Dorpe gives SST a look at the physics and structure behind a new method to integrate high-speed CMOS electronics and nanophotonic circuitry based on plasmonic effects, which has promise in applications from biosensing to thin-film solar cells.

Method integrates nanophotonic circuitry with ICs

05/04/2009  May 4, 2009: European independent nanoelectronics research consortium IMEC says it has developed a method to integrate high-speed CMOS electronics and nanophotonic circuitry based on plasmonic effects.

The reliability margin of interconnects for advanced memory technologies

05/01/2009  The trends of decreasing dimensions and new materials motivated the investigation of how these may affect the dielectric reliability of the interconnect structures.

Memory sector ready to rebound? Not quite

05/01/2009  Signs that the DRAM market hit a bottom in 1Q and is poised to rebound don't quite paint the whole picture, which from a broader perspective still shows things plodding along, far from a meaningful recovery.

IITC 2009 preview: Innovation in copper contacts, 3D, metrology

04/29/2009  IITC 2009 program chair Mike Shapiro (IBM) and publicity chair Mike Armacost (Applied Materials) brief SST on selected papers from the more than 80 technical presentations expected at the summer conference, held for the first time in Japan.

Inside Novellus's tungsten CVD process for 32nm

04/27/2009  Get a sneak-peek at Novellus' new CoolFill tungsten CVD process, which the company says offers a larger process window to achieve void-free fill that meets the ITRS' electrical property requirements for 32nm DRAM and logic devices.

Toppan's Kalk: 28nm tapeouts proceeding according to plan

04/27/2009  Toppan Photomasks exec Franklin Kalk talks with SST about the joint work with IBM on photomasks for 32nm and 28nm semiconductor manufacturing, the key differences vs. 45nm-40nm work, the emergence of OMOG and SMO -- and eventually (and carefully), EUV.

MRS Spring 2009: Working on HK+MG, solar cell efficiency, flash replacements

04/22/2009  In an SST exclusive, Intermolecular CTO Tony Chiang summarizes several talks from last week's MRS Spring meeting, on materials characterization, solar-cell technology, CMOS gate-stacks (high-k/metal gates), and the search to replace traditional flash memory with a manufacturable alternative.




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Environment, Safety & Health

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The semiconductor industry is an acknowledged global leader in promoting environmental sustainability in the design, manufacture, and use of its products, as well as the health and safety of its operations and impacts on workers in semiconductor facilities (fabs). We will examine trends and concerns related to emissions, chemical use, energy consumption and worker safety and health.

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Wafer Processing

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As the industry moves to 10nm and 7nm nodes, advances in wafer processing – etch, deposition, planarization, implant, cleaning, annealing, epitaxy among others – will be required. Manufacturers are looking for new solutions for sustained strain engineering, FinFETs, FDSOI and multi-gate technologies, 3D NAND, and high mobility transistors.

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