Device Architecture

DEVICE ARCHITECTURE ARTICLES



Elpida, UMC pair up for foundry services

03/18/2008  Mar. 18, 2008 - Elpida Memory and Taiwan's United Microelectronics Corp. (UMC) are expanding their partnership to target Japanese foundry customers, combining Elpida's 300mm fab capacity with UMC's IP and logic technologies. The deal gives UMC inroads into Japanese foundry customers, while Elpida gets to utilize excess DRAM production capacity.

Alchimer CEO Predicts Demise of Vapor Deposition Processes for TSVs by 2009

03/18/2008  ; After being appointed CEO of Alchimer SA, Steve Lerner immediately predicted the demise of vapor deposition processes for depositing nanoscale films in through silicon vias (TSVs) within a year. Steve Lerner is a technologist with 29 years' experience in semiconductor development and manufacturing. He founded advanced packaging and device companies Alpha Szenszor, GigSys, and CS2, and has held executive positions at Amkor, Swire, and AME.

Flash Vector Programming System
BPM Microsystems


03/17/2008  The Flashstream Flash Vector programming system offers a fast flash programming of NAND and NOR flash memory at speeds as low as 2.5% over theoretical programming minimum. This speed is due to the creation of this company's proprietary co-processor technology called Vector Engine, which accelerates flash memory waveforms during the programming cycle.

IBM tips nanophotonic switch for on-chip optical network

03/17/2008  Mar. 17, 2008 - IBM says it has developed a silicon broadband optical switch, a key component to enable on-chip optical interconnects. The device helps "direct traffic" of electrical signals, converted into light pulses so optical messages can efficiently get form one processor core to another -- enabling up to 100x more information to be sent between cores, using 10x less power.

Tessera Receives Job Development Investment Grant from North Carolina

03/17/2008  ; The North Carolina Economic Investment Committee has awarded a job development investment grant (JDIG) to Tessera Technologies Inc., a provider of miniaturization technologies for the electronics industry. This grant will support Tessera's consumer optics plans, enabling the company to add 185 jobs and invest approximately $30 million in its Charlotte-based wafer-level optics facilities during the next five years.

JSR touts "freezing material" for double patterning

03/13/2008  Mar. 13, 2008 - JSR says it has achieved 32nm line and space patterns for 22nm node semiconductor devices with a new "freezing material" used in double patterning. Results were presented at last month's SPIE Advanced Lithography conference.

SPIE report: ...and EUVL, eventually

03/12/2008  by M. David Levenson, Editor-in-Chief, Microlithography World
Progress continued in EUV lithography, but at a rate well below that needed for insertion at 32nm. AMD described the patterning of an entire metal-1 layer for a full exposure field chip and the integration of EUVL into the process flow. Sources remain an issue, though some think solid state lasers could help improve efficiency. Others are thinking ahead to 22nm. (Second in a four-part series)

SPIE report: Nonstarters, and dark options

03/12/2008  by M. David Levenson, Editor-in-Chief, Microlithography World
Intel chose this SPIE conference to present five papers on pixelated masks, an apparently abandoned program on pixelated masks that had pre-occupied litho engineers for several years. Elsewhere, prospects for high-index immersion technology seem to be dimming, and progress remains sluggish on a promising medium-throughput e-beam direct write for imprint litho. (Third in a four-part series)

SEMATECH's Arkalgud: A 3D/TSV route to higher IC densities

03/11/2008  by Bob Haavind, Editorial Director, Solid State Technology
An insightful update on three key semiconductor technologies -- SOI, TSV/3D, and SOI -- sparked a lively Q&A following a SEMI-sponsored breakfast near Boston (Mar. 5). Here, Sitaram Arkalgud, head of SEMATECH's 3D interconnect program in Albany, discusses the expected evolution of through-silicon vias (TSVs) and 3D chip stacks for future electronics.

U. Albany's Denbeaux: EUV works, though far from what's needed

03/11/2008  by Bob Haavind, Editorial Director, Solid State Technology
An insightful update on three key semiconductor technologies -- SOI, TSV/3D, and SOI -- sparked a lively Q&A following a SEMI-sponsored breakfast near Boston (Mar. 5). Here, Gregory Denbeaux, assistant professor of nanotechnology at the U. of Albany, gave an overview of progress needed in EUV to make it suitable for high volume manufacturing.

IBM's Starkey: The case for SOI won't diminish w/ shrink

03/11/2008  by Bob Haavind, Editorial Director, Solid State Technology
An insightful update on three key semiconductor technologies -- SOI, TSV/3D, and SOI -- sparked a lively Q&A following a SEMI-sponsored breakfast near Boston (Mar. 5), held at an MKS Instruments facility. Here, Gordon Starkey, a senior engineer in technical operations for IBM, explained how silicon-on-insulator (SOI) has made a transition from a niche to mainstream technology.

Analyst: 2Q holds key to 2008 chip industry growth

03/11/2008  Mar. 10, 2008 - The current sluggish growth and mounting economic worries are calling into question whether the semiconductor industry can regain momentum and manage any growth this year, and the second quarter -- traditionally a period of accelerating growth -- will be the key, according to a recent report by iSuppli.

Reports: Hynix eyeing ProMOS tech transfer, Samsung steamed

03/11/2008  Mar. 10, 2008 - Hynix Semiconductor reportedly is in negotiations to send 54nm DRAM process technology to Taiwan's ProMOS, a year after a similar deal for 66nm process technology raised eyebrows.

TSMC, SanDisk working on 45nm NAND

03/11/2008  Mar. 10, 2008 - SanDisk and TSMC have verified SanDisk's 80nm OTP NAND chip at TSMC, and the two firms are now progressing to 45nm chip development -- work that is raising industry eyebrows since Spansion is also a top TSMC client with its competitive ORNAND chips, according to the Taiwan Economic News.

IBM, Hitachi ink 32nm dev pact

03/10/2008  Mar. 10, 2008 - IBM and Hitachi say they have signed a two-year deal to research 32nm and beyond semiconductor technologies, particularly methods for analyzing devices and structures to improve characterization and measurement of transistor variation.

Micron reforms imaging biz as Aptina

03/07/2008  Mar. 6, 2008 - Micron Technology has separated its CMOS image sensor business into an independent division, Aptina Imaging, to better focus on delivering the technology to customers while Micron focuses its efforts on the memory sector.

Gartner: NAND woes already denting 2008 outlook

03/04/2008  Mar. 4, 2008 - Visibility isn't improving much in the semiconductor industry, but Gartner Dataquest already doesn't like what it sees, particularly in the memory sector -- this time it's NAND flash -- so the analyst firm is chopping its outlook for 2008 growth nearly in half to 3.4%.

Intel: NAND slump cutting into margins

03/04/2008  Mar, 4, 2008 - Intel has lowered its outlook for 1Q08 gross margins to 53%-55% from ~56% (vs. 58% in 4Q07), citing lower than expected pricing for NAND flash memory chips. All other expectations for the quarter remain unchanged.

SPIE REPORT: Optics, EUV competing for the 22nm node

03/04/2008  by Griff Resor, Resor Associates
Mar. 4, 2008 - With 38nm half-pitch seemingly the limit for single image 193nm immersion lithography, how the industry will reach the 32nm and 22nm nodes was the focus of last week's SPIE Advanced Lithography conference. Optics with double patterning, EUV, and e-beam direct write -- which will it be for 22nm? After a decade as a doubting Thomas, here's why I think the biggest IC companies will use EUV for the most difficult layers at the 22nm node.

Zarlink: Take our analog fab, please!

02/29/2008  Feb. 29, 2008 - In what is essentially the last in a divestiture of its semiconductor foundry operations, Zarlink Semiconductor has sold its analog foundry in Swindon, UK to a subsidiary of domestic electronics component supplier MHS Electronics -- with a grand pricetag of €1 (~$1.51).




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Environment, Safety & Health

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The semiconductor industry is an acknowledged global leader in promoting environmental sustainability in the design, manufacture, and use of its products, as well as the health and safety of its operations and impacts on workers in semiconductor facilities (fabs). We will examine trends and concerns related to emissions, chemical use, energy consumption and worker safety and health.

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Wafer Processing

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As the industry moves to 10nm and 7nm nodes, advances in wafer processing – etch, deposition, planarization, implant, cleaning, annealing, epitaxy among others – will be required. Manufacturers are looking for new solutions for sustained strain engineering, FinFETs, FDSOI and multi-gate technologies, 3D NAND, and high mobility transistors.

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